System Drivers Chapter

18 July 2001 Work In Progress – Not for Publication

ITRS-2001 Design ITWG

July 18, 2001

Europe: W. WeberJapan: Y. Furui, T. Kadowaki, H. Taguchi, K. UchiyamaUSA: A. Kahng, K. Kolwicz


System Drivers ChapterSystem Drivers Chapter• Define IC products that drive mfg, design technologies• Replace the 1999 SOC Chapter• ORTCs + SDs = “consistent framework for tech requirements”• Four system drivers

– (HVC) MPU – traditional processor core– SOC (focus on “ASIC-LP”, + high-pins, high-signaling network driver)– AM/S – four basic circuits and FOMs– (HVC) DRAM

• Each driver section• Nature, evolution, formal definition of this driver• What market forces apply to this driver ?• What technology elements (process, device, design) does this drive?• Key figures of merit, and roadmap

• Working text material (handout): (MPU) , (SOC) , AMS• Inputs from Test, A&P, Litho/PIDS/FEP, Interconnect


MPU DriverMPU Driver

• Old MPU model – 3 flavors • New MPU model - 2 flavors

• Cost-performance at production (CP) – 140 mm2 die, “desktop”

• High-performance at production (HP) – 310 mm2 die, “server”

• Both have multiple cores (“helper engines”), on-board L3 cache, …– Multi-cores == more dedicated, less general-purpose logic; driven by

power and reuse considerations; reflect convergence of MPU and SOC

• Doubling of transistor counts is each per each node, NOT per each 18 months

• Clock frequencies stop doubling with each node


Example Supporting Analyses (MPU)Example Supporting Analyses (MPU)

• Diminishing returns– Pollack’s Rule: In a given process technology, new microarchitecture takes 2-3x

area of previous generation one, and provides only 50% more performance– Corroboration: SPECint/MHz, SPECfp/MHz, SPECint/Watt all decreasing

• Power knob running out– Speed == Power– Large switching currents, large power surges on wakeup, IR drop control issues

all limited by A&P roadmap (e.g., improvement in bump pitch, package power)

• Power management: 2500% improvement needed by 2016• Speed knob running out (new clock frequency model)

– Historically, 2x clock frequency every node• 1.4x/node from device scaling but running into tox, other limits (PIDS)• 1.4x/node from fewer logic stages (from 40-100 down to around 14 FO4 INV delays)

– Clocks cannot be generated with period < 6-8 FO4 INV delays– Pipelining overhead (1-1.5 FO4 INV delay for pulse-mode latch, 2-3 for FF)– Around16 FO4 INV delays is limit for clock period in core (L1 $ access, 64b add)– Cannot continue 2x frequency per node trend in ITRS


• Logic Density: Average size of 4t gate = 32MP2 = 320F2

– MP = lower-level contacted metal pitch– F = min feature size (technology node)– 32 = 8 tracks standard-cell height times 4 tracks width (average NAND2)– Additional whitespace factor = 2x (i.e., 100% overhead)– Custom layout density = 1.25x semi-custom layout density

• SRAM Density: (used in MPU) – bitcell area (units of F^2) near flat: 223.19*F (um) + 97.748 – peripheral overhead = 60% – memory content is increasing (driver: power) and increasingly fragmented– will see paradigm shifts in architecture/stacking; eDRAM, 1-T SRAM, 3D integ…

• Significant SRAM density increase, slight Logic density decrease, compared to 1999 ITRS– 130nm node: old ASIC logic density = 13M tx/cm2, new = 11.6M tx/cm2

– 130nm node: old SRAM density = 70M tx/cm2, new = 140M tx/cm2– Chief impact: power densities, logic-memory balance on chip

Example Supporting Analyses (MPU)Example Supporting Analyses (MPU)


SOC-LP Driver (STRJ)SOC-LP Driver (STRJ)• Power gap

– Must reduce dynamic and static power to avoid zero logic content limit– Hits low-power SOC before hits MPU– SOC degree of freedom: low-power (not high-perf) process

• SOC-LP model drives ASIC-LP (PIDS) device model– Lgate lags high-performance devices by 2 years– Accompanying device parameter changes

• Vth higher (up to .5 x Vdd limit)• Ig, Ioff starts at 100pA/um (L(Operating)P), 1pA/um (L(STandby)P)• Tox higher• Slower devices (higher CV/I)

– Four LP device flavors: Design still faces 40-1000%/node static power management challenge, and must address multi (Vt,tox,Vdd)

• SOC-LP driver: low-power PDA– Composition: CPU cores, embedded cores, SRAM/eDRAM– Roadmap for IO bandwidth, processing power, GOPS/mW efficiency– Die size grows at 20% per node


SOC-LP Driver ModelSOC-LP Driver Model

• Required performance trend of SOC-LP PDA driver• Drives PIDS/FEP LP device roadmap, Design power

management challenges

Year of Products 2001 2004 2007 2010 2013 2016Process Technology (nm) 130 90 65 45 32 22Operation Voltage (V) 1.2 1 0.8 0.6 0.5 0.4Clock Frequency (MHz) 150 300 450 600 900 1200Application Still Image Processing Real Time Video Code Real Time Interpretation (MAX performance required) (MPEG4/CIF)Application Web Browser TV Telephone (1:1) TV Telephone (>3:1)(Others) Electric Mailer Voice Recognition (Input) Voice Recognition (Operation)

Scheduler Authentication (Crypto Engine)Processing Performance (GOPS) 0.3 2 15 103 720 5042Communication Speed (Kbps) 64 384 2304 13824 82944 497664Power Consumption (mW/MOPS) 0.3 0.2 0.1 0.03 0.01 0.006Peak Power Consumption (W) 0.1 0.3 1.1 2.9 10.0 31.4(Requirement) 0.1 0.1 0.1 0.1 0.1Standby power consumption (mW) 2.1 2.1 2.1 2.1 2.1 2.1Addressable System Memory (Gb) 0.1 1 10 100 1000 10000


Mixed-Signal DriverMixed-Signal Driver(Europe)(Europe)

Ralf Brederlow°, Stephane Donnay+,Joseph Sauerer#, Maarten Vertregt*,Piet Wambacq+, and Werner Weber°

°Infineon Technologies, +IMEC, #Fraunhofer-Instutitut for

Integrated Circuits , *Philips Semiconductor


• Today, the digital part of circuits is most critical for performance and is dominating chip area

• But in many new IC-products the mixed-signal part becomes important for performance and cost

• This shift in paradigms leads to the need for a definition of the analog boundary conditions in the design part of the ITRS roadmap

• The goal is to define criteria for needs of future analog/RF circuit performance and compare it to device parameters:

choose critical and important analog/RF circuits identify circuit performance needs and related device parameter needs

OverviewOverview


Roadmap for basic Roadmap for basic analog / RF circuitsanalog / RF circuits

Concept for the Mixed-Signal-RoadmapConcept for the Mixed-Signal-Roadmap

• Figures of merit for four important basic analog building blocks are defined and estimated for future circuit design

• From these figures of merit related future device parameter needs are estimated (PIDS-table partially owned by design)

Roadmap for device Roadmap for device parameter (needs)parameter (needs)

AA//DD--CConverteronverter

LLow-ow-NNoise oise AAmplifiermplifierVVoltage-oltage-CControlled ontrolled OOscillatorscillatorPPower ower AAmplifiermplifier

LLminmin 2001 … 20152001 … 2015

…………

mixed-signal device parametermixed-signal device parameter

…………


Figure of Merit for LNAsFigure of Merit for LNAs

PNF

fIIPGFOM LNA

)1(

3

G gainNF noise figureIIP3 third order intercept pointP dc supply powerf frequency

LNA performance:

• dynamic range

• power consumption

1 / minimum gate length [µm-1]

1 10 100F

oM

LN

A [G

Hz]

1

10

100


Figure of Merit for VCOsFigure of Merit for VCOs

f0 carrier frequencyf frequency offset from f0

L{f } phase noiseP supply power

VCO performance:

PfLf

fFoMVCO

}{

12

0

• timing jitter



1 10 100F

oM

VC

O [1

/J]

1020

1021

1022

1023

1024

1025


Figure of Merit for PAsFigure of Merit for PAs

Pout output powerG gainPAE power added efficiencyIIP3 third order intercept pointf frequency

PA performance:

• output power


2fPAEGPFoM outPA


1 10 100

Fo

M P

A [W

GH

z²]

103

104

105

106

107


Figure of Merit for ADCsFigure of Merit for ADCs

ENOB0 effective number of bitsfsample sampling frequencyERBW effective resolution bandwidthP supply power

P

ERBWfFoM sample

ENOB

ADC

})2{},min({2 0

ADC performance:

• dynamic range

• bandwidth


year of publication

1990 1995 2000 2005 2010 2015

FoM

AD

C [

1/Jo

ule]

1010

1011

1012

1013


Mixed-Signal Device ParametersMixed-Signal Device Parameters(1) 2001 2002 2003 2004 2005 2006 2007 O WN ER

130 115 100 90 80 70 65 O RTC

150 130 105 90 80 70 65 O RTC

90 75 65 53 45 40 35 O RTC

65 53 45 37 32 30 25 O RTC

O RTC

100 90 80 70 65 55 50 O RTC

90 80 70 65 60 50 45 O RTC

(2) M inim um Sup p ly Vo lta g e Dig ita l De sig n (V) 0.9-1.3 0.8-1.2 0.8-1.1 0.7-1.0 0.6-0.9 0.55-0.8 0.5-0.7 PIDS

(3) Ana lo g De sig n (V) De sig n

(14) nM O S RF De vic e To x (nm ) 1.2-1.5 1.0-1.5 1.0-1.4 0.9-1.3 0.8-1.2 0.7-1.0 0.6-0.8 PIDS

(15) fm a x (G Hz) 50 55 60 65 70 75 80 De sig n

(16) ft (G Hz) 95 105 120 130 140 170 190 PIDS

(17) G m / G d s @ Lm in-d ig ita l 20 20 20 20 20 20 20 De sig n

(18) @ 10 Lm in-d ig ita l 100 100 100 100 100 100 100 De sig n

(19) 1/f N o ise (µV 2 µm 2 / Hz) 500 500 300 300 300 200 200 De sig n

(20) 3 Vth m a tc hing (m V µm ) 15 15 15 12 12 9 9 De sig n

(21) nM O S Ana lo g De vic e To x (nm ) 7-2.5 7-2.5 5-2.5 5-2.5 5-2.5 5-2.5 5-2.5 PIDS

(22) Ana lo g Vth (V) 0.5-0.3 0.5-0.2 0.5-0.2 0.5-0.2 0.4-0.2 0.4-0.2 0.4-0.2 De sig n

(23) G m / G d s @ 10 Lm in-d ig ita l 200 200 200 200 200 200 200 De sig n

(24) 1/f N o ise (µV 2 µm 2 / Hz) 1000 500 500 500 300 300 300 De sig n

(25) 3 Vth m a tc hing (m V µm ) 21 21 15 15 15 15 15 De sig n

(26) Ana lo g C a p a c ito r De nsity (fF/µm 2 ) 2 3 3 3 4 4 4 De sig n

(27) Q (1 / k 2 µm 2 G Hz) 200 300 300 300 450 450 450 De sig n

(28) Vo lta g e line a rity (p p m / V2 ) 100 100 100 100 100 100 100 De sig n

(29) Le a ka g e (fA / [p F V]) 7 7 7 7 7 7 7 De sig n

(30) 3 M a tc hing (% µm2 ) 4.5 3 3 3 2.5 2.5 2.5 De sig n

(34) Re sisto r Re sista nc e ( / ) 100 100 100 100 100 100 100 De sig n

(35) Q (k 2 µm 2 G Hz) 1000 1500 1500 1500 2000 2000 2000 De sig n

(36) Te m p . line a rity (p p m / C ) 60 60 50 50 50 40 40 De sig n

(37) 3 M a tc hing (% µm ) 9 8 8 8 7 7 7 De sig n

(38)

1/f c urre nt no ise p e r c urre nt2

(1 / [µm 2 Hz])10 -18 10 -18 10 -18 10 -18 10 -18 10 -18 10 -18

De sig n

(39) Ind uc to r De nsity (nH/µm 2 ) 0.03 0.03 0.03 0.03 0.03 0.03 0.03 De sig n

(40) Q 3d B 12 15 17 18 19 20 20 De sig n

(41) Sig na l Iso la tio n S21 (d B) -100 -100 -100 -100 -120 -120 -120 PIDS

DRAM Pitc h (Sc 2.0) (nm )

M PU Pitc h (Sc 3.7) (nm )

M PU Printe d G a te Le ng th (Sc 3.7) (nm )

M PU Physic a l G a te Le ng th (Sc 3.7) (nm )

ASIC /Lo w Po we r Pitc h (Sc 3.x) (nm )

ASIC /Lo w Po we r Printe d G a te Le ng th (Sc 3.x) (nm )

ASIC /Lo w Po we r Physic a l G a te Le ng th (Sc 3.x) (nm )

2.5-1.8

Ye a r o f Pro d uc tio n

3.3-1.8


Mixed-Signal Market DriversMixed-Signal Market Drivers

Signal Bandwidth

468

10121416182022

1kHz 10kHz100kHz 1MHz 10MHz100MHz1GHz

Res

olu

tio

n(b

it)

1 W

1mW 1 W1 kW

System drivers for mass markets can be identified from the FoM approach

super

audio

GSMGSM Basestation

telephony

audio

video

Cable DTV

Intercon-

nectivity

Storage

UMTS

Bluetooth


Design Chapter OutlineDesign Chapter Outline• Introduction

– Scope of design technology– Complexities (silicon, system, design process)– How design technology is driven by System Drivers– Design Grand Challenges

• Details of challenges/needs and potential solutions (metrics)– One section for each of:

• Design Process (quality/cost model )• Functional Verification (escapes, fault tolerance)• System-Level (embedded software productivity, reuse, quality)• Logical/Physical/Circuit (power management, AM/S circuit FOMs)• Test (%BIST, …)

– In each section:• Overview of detailed issues and challenges• Near-term / long-term needs related to driver classes• Key quality metrics (tables or figures)


Design Grand Challenges > 65nmDesign Grand Challenges > 65nm• Scaling of maximum-quality design implementation productivity

• Overall design productivity of quality- (difficulty-) normalized functions on chip must scale at 2x / node

• Reuse (including migration) of design, verification and test effort must scale at > 2x/node

• Develop analog and mixed-signal synthesis, verification and test • Embedded software productivity

• Power Management• Off-currents in low-power devices increase 10x/node; design technology must

maintain constant static power• Power dissipation for HP MPU exceeds package limits by 25x in 15 years; design

technology must achieve power limits • Power optimizations must simultaneously and fully exploit many degrees of freedom -

multi-Vt, multi-Tox, multi-Vdd in core - while guiding architecture, OS and software

• Deeper integration of Design technology with other ITRS technology areas• Example: Die-package co-optimization• Example: Design for Manufacturability (sharing variability burden with

Litho/PIDS/FEP and Interconnect, reduction of system NRE cost)• Example: Design for Test


Design Grand Challenges < 65nmDesign Grand Challenges < 65nm• (Three Grand Challenges from > 65nm, and)• Noise Management

• Lower noise headroom especially in low-power devices; coupled interconnects; supply voltage IR drop and ground bounce; thermal impact on device off-currents and interconnect resistivities; mutual inductance; substrate coupling; single-event upset (alpha particle); increased use of dynamic logic families

• Modeling, analysis and estimation at all levels of design

• Error-Tolerant Design• Relaxing 100% correctness requirement may reduce manufacturing, verification, test

costs• Both transient and permanent failures of signals, logic values, devices, interconnects• Novel techniques: adaptive and self-correcting / self-repairing circuits, use of on-chip

reconfigurability


Design Cost AnalysisDesign Cost Analysis• “Largest possible ASIC” design cost model (Dataquest)

• engineer cost per year increases 5% per year ($181,568 in 1990)• EDA tool cost per year increases 3.9% per year ($99,301 in 1990)• #Gates in largest ASIC/SOC design (.25M in 1990, 250M in 2005)• %Logic Gates constant at 70% • #Engineers / Million Logic Gates decreasing from 250 in 1990 to 5 in

2005• Productivity due to 8 major Design Technology innovations (3.5 of

which are still unavailable) : RTL methodology; In-house P&R; Tall-thin engineer; Small-block reuse; Large-block reuse; IC implementation suite; Intelligent testbench; ES-level methodology

• Small refinements: (1) memory content; (2) other design NRE (mask cost, etc.)

– #Engineers per ASIC design still rising 20x in 15 years despite assumed 50x improvement in designer productivity


(Dataquest, 2001) Cost Metrics Forecast

$10,000,000

$100,000,000

$1,000,000,000

$10,000,000,000

$100,000,000,000

1990 1991 1992 1993 1994 1995 1996 1997 1998 1999 2000 2001 2002 2003 2004 2005

Design Cost for Largest Possible ASIC

Same Cost RTL Methodology Only

Design Cost and Quality RequirementDesign Cost and Quality Requirement• Design cost of “largest ASIC” rises despite major DT innovations• Other Dataquest #’s confirm slight increase in memory content• Must complement with requirements for design quality


Design Quality ModelDesign Quality Model

• “Normalized transistor” quality model normalizes:• speed, power, density in a given technology• analog vs. digital• custom vs. semi-custom vs. generated• first-silicon success• other: simple / complex clocking, verification/test effort

and coverage, manufacturing cost, …

• Design process quality model: in development• Many private commercial and/or in-house analogues• Survey methodology being used (US, MARCO GSRC)

System Drivers Chapter

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