SYNTHESIS OF COMBINATIONAL &

SEQUENTIAL LOGIC

Various ways to describe combinational logic with

verilog HDL, but some are not supported by

synthesis tool

Continuous assignment statements are

synthesizable.

Expressions that assigns value to a netlist will be

translated by synthesis tool, which can be

optimized and synthesized in physical hardware

Combinational Logic Synthesis

Synthesized by contineous

assignment

Circuit synthesized from a

MUX with Selector Logic

SYNTHESIS OF PRIORITY STRUCTURE

An if statement implies higher priopity to the

first branch than to the remaining branches

Circuit synthesized from a mux with

priority decode of input conditions

SYNTHESIS OF SEQUENTIAL LOGIC

WITH FLIPFLOPS

SYNTHESIS CKT OF 4 D FF, A 4 BIT

PARALLEL LOAD DATA REGISTER

Synthesis of

Counters

Structure of 4- bit ripple counter

SYNTHESIZED CKT OF 4-BIT RIPPLE

COUNTER

Synthesis of Shift Registers

STRUCTURE OF SHIFT REGISTER WITH

REGISTERED COMBINATIONAL LOGIC

SHIFT REGISTER WITH UN-

REGISTERED COMBINATIONAL

LOGIC

STRUCTURE OF SHIFT REGISTER WITH UN-

REGISTERED COMBINATIONAL LOGIC

IMPLEMENTATION

TECHNOLOGY (PLD & FPGA)

SIMPLIFIED PLD SYMBOLOGY

O1 = A B + A B

O2 = A B

O3 = 0

O4 = 1

Implementation approaches

Custom

Standard Cells MacroCells

Cell-based

Pre-diffused(Gate Arrays)

Pre-wired(FPGA's)

Array-based

Semi-custom

Digital Circuit Implementation Approaches

Impact of Implementation ChoicesE

ne

rgy

Eff

icie

ncy

(in

MO

PS

/m

W)

Flexibility

(or application scope)

0.1-1

1-10

10-100

100-1000

None Fully

flexible

Somewhat

flexible

Ha

rdw

ire

d c

usto

m

Co

nfi

gu

rab

le/P

ara

me

teri

zab

le Do

ma

in-s

pe

cif

ic p

roce

sso

r

(e.g

. D

SP

)

Em

be

dd

ed

mic

rop

roce

sso

r

The Full Custom Approach

Intel 4004

Standard Cell - Example

3-input NAND cell

(from ST Microelectronics):

C = Load capacitance

T = input rise/fall time

Pre-diffused(Gate Arrays)

Pre-wired(FPGA's)

Array-based

Gate Array — Sea-of-gates

rows of

cells

routing channel

uncommitted

VDD

GND

polysilicon

metal

possiblecontact

In1 In2 In3 In4

Out

Uncommitted

Cell

Committed

Cell

(4-input NOR)

Pre-wired arrays

Array-Based Programmable Logic

PLA PROM PAL

I 5 I 4

O 0

I 3 I 2 I 1 I 0

O 1O 2O 3

Programmable AND array

Programmable

OR array I 5 I 4

O 0

I 3 I 2 I 1 I 0

O 1O 2O 3

Programmable AND array

Fixed OR array

Indicates programmable connection

Indicates fixed connection

O 0

I 3 I 2 I 1 I 0

O 1O 2O 3

Fixed AND array

ProgrammableOR array

Programming a PROM

f0

1 X 2 X 1 X 0

f1NANA

: programmed node

More Complex PAL

i inputs, j minterms/macrocell, k macrocells

Altera MAX 7000 CPLD

Programmable logic Devices (PLD)

Xilinx XC9500 CPLD

Macrocell Architecture

Field Programmable Gate Arrays

Elements of an FPGA fabric

Logic.

Interconnect.

I/O pins.

…

LE LE LE

LE LE LE

LE LE LE

interconnect

IOB IOB IOB …

Terminology

Configuration: bits that determine logic function + interconnect.

CLB: combinational logic block = logic element (LE).

LUT: Lookup table = SRAM used for truth table.

I/O block (IOB): I/O pin + associated logic and electronics.

Logic element

Programmable Input connections.

Internal function.

Coarser-grained than logic gates. Typically 4 inputs.

Generally includes register.

May provide specialized logic. Adder carry chain.

Full FPGA ArchitectureConfigurable

logic block

Cell Based Design

Mutiplexers based logic cells

Look-up table based logic cells

Logic Cell of Actel Fuse-Based FPGA

A

B

SA Y

1

C

D

SB

1

S0S1

1

How to realise XOR gate

by using the logic cell?

A=1, B=0, C=0, D=1,

SA=SB=In1, S0=S1=In2;

Look-up Table Based Logic Cell

Out

ln1 ln2

Me

mo

ry

In Out

00 00

01 1

10 1

11 0

0

Any complex function can be realised by using either a bigger

size LUT or a number of LUTs

LUT-Based Logic Cell

G 4

C 1....C 4

K

CLOCK

G 3

G 2

G 1

F4

F3

F2

F1

Logic

function

of

G1-G4

Logic

function

of

F,G, H1

Logic

function

of

F1-F4

Din

H1

4

FGH

DinFGH

GH

DIN/H2SR/H0 EC

HF

Bitscontrol

Bitscontrol

Multiplexer Controlledby Configuration Program

D

Y1

1

EC

QSD YQ

Bypass

x

XQ

Bypass

RD

D

EC

QSD

RD

Xilinx 4000 Series Configurable Logic Block

Configurable Logic Block

It combines two four-input LUTs feeding a three-input

LUT.

The cell has two FFs whose inputs can be any of the LUT

outputs or an external input.

X any Y outputs of LUTs are used to build complex

combinational functions.

C1-C4 can be used as inputs or SR or for clock enable

Evaluation of SRAM-based LUT

All logic functions take the same amount

of space.

All functions have the same delay.

SRAM is larger than static gate equivalent

of function.

SRAM-based FPGA’s

Program logic functions, interconnect

using SRAM.

Advantages: Re-programmable;

dynamically reconfigurable;

uses standard processes.

Disadvantages: SRAM burns power.

Possible to steal, disrupt configuration bits.

MOS switch controlled by configuration bit

D Q

Programmable interconnect

Programmable vs. fixed

interconnect

Switch adds delay.

Transistor off-state is worse in advanced

technologies.

FPGA interconnect has extra length =

added capacitance.

Interconnect strategies

Some wires will not be utilized.

Congestion will not be same throughout the chip.

Types of wires: Short wires: local LE connections.

Global wires: long-distance, buffered communication.

Special wires: clocks, etc.

Programmable Interconnection

Input/output pinProgrammed interconnection

Interconnect

Point

Horizontal

tracks

Vertical tracks

Cell

M

Mesh-based Interconnect Network

Switch Box

Connect Box

CLB CLB

CLB CLB CLB

CLBCLBCLB

Transistor Implementation of Mesh

I/O Blocks

Fundamental selection: input, output,

three-state ?

Additional features: Register.

Voltage levels.

Slew rate.

Configuration

Must set control bits for: LE.

Interconnect.

I/O blocks.

Usually configured off-line. Separate burn-in step (antifuse).

At power-up (SRAM).

Programming technologies

SRAM (Xilinx and Altera) Can be programmed many times.

Must be programmed at power-up.

Antifuse (Actel) Programmed once.

Flash. Similar to SRAM but using flash memory.

Configuration ROM

Configured on start-up from ROM

FPGA

Configuration

memory

Configuration length depends on size of

the chip

200,000 to 1.3 million bits

Heterogeneous Programmable Platforms

Xilinx Vertex-II Pro

High-speed I/O

Embedded PowerPc

Embedded memories

Hardwired multipliers

FPGA Fabric

10 million gate FPGA is available

Structured ASIC is a new Technology on the horizon

Design at a crossroad

System-on-a-Chip

RAM

500 k Gates FPGA

+ 1 Gbit DRAM

Preprocessing

Multi-

Spectral

Imager

mC

system

+2 Gbit

DRAMRecog-

nition

Anal

og

64 SIMD Processor

Array + SRAM

Image Conditioning

100 GOPS

Embedded applications

where cost, performance,

and energy are the real

issues!

DSP and control intensive

Mixed-mode

Combines programmable

and application-specific

modules

Software plays crucial role

Addressing the Design Complexity Issue

Architecture Reuse

Reuse comes in generations

Generation Reuse element Status

1st Standard cells Well established

2nd IP blocks Being introduced

3rd Architecture Emerging

4th IC Early research

DESIGN WITH FPGAS

1. Design at the behavioral level using either Verilog or VHDL

2. Choose the appropriate FPGA vendor library at the time of

synthesis.

3. Implement the design into FPGA by using vendor specific tools

from the gate level netlist. (The gate level netlist is broken in

terms of CLBs and their interconnections- placement and

routing )

4. The implementation tool generates the configuration bitstream

which is used for actually configuring the FPGA as per the

design.

5. Carry out hardware debugging by monitoring the internal signals

in a FPGA.

6. Carry out PCB level testing for final verification.

FPGA fabric architecture

questions

Given limited area budget: How many logic elements?

How much interconnect?

How many I/O blocks?

FPGA architecture evaluation

methodology

FPGA

fabric

architecture

Logic

benchmarks

Place +

route

Area and

performance

evaluation

metrics

Evaluation metrics

Structural: Size of the logic element.

Size of interconnect.

Mapping-related: Logic utilization.

Interconnect utilization.

Delay.

Power consumption.

Logic element or CLB parameters

How many inputs? Too few inputs---more overhead per LE.

Too many inputs---wasted capacity when mapping logic to LEs.

Depends on circuit design of LE and

characteristics of logic.

Typical choice: 4-inputs.

Types of FPGAs

1. Fine grained

2. Coarse grained