Logic Design Basics - UC Santa Barbarastrukov/ece154aFall2012/lecture2.pdfClock + sequential logic =...
Transcript of Logic Design Basics - UC Santa Barbarastrukov/ece154aFall2012/lecture2.pdfClock + sequential logic =...
Logic Design BasicsLogic Design Basics
• Information encoded in binaryInformation encoded in binary– Low voltage = 0, High voltage = 1
One wire per bit– One wire per bit
– Multi‐bit data encoded on multi‐wire buses
Grouping of signalsGrouping of signals
How to build combinational elements?
• AND‐gate AY+
Adder– Y = A & B
AY
B
Y+ Y = A + B
BY
Multiplexer Arithmetic/Logic Unit
Multiplexer Y = S ? I1 : I0
A
Y = F(A, B)
I0I1
YMux B
YALU
S F
Gate level design: NAND
N instances of 1‐bit wide multiplexorN instances of 1 bit wide multiplexor
1‐bit‐wide multiplexor
Implementation of 1‐bit‐wide multiplexormultiplexor
4‐to‐1 multiplexor
Hierarchical construction of MUXes
Building adder
Building adder
Building adder
Ripple carry adder
Circuit delay
Simple ALU
Combinational logicCombinational logic
• Complex logic blocks are built from basic ANDComplex logic blocks are built from basic AND, OR, NOT building blocks we will see shortly
• A combinational logic block is one in which• A combinational logic block is one in which the output us a function only of its current inputinput
• Combination logic cannot have memory
Sequential logic = State elements+ combination logic
How to implement?How to implement?
Will that work?Will that work?
Sequential Elements• Flip flop: stores data in a circuit
Uses a clock signal to determine when to update– Uses a clock signal to determine when to update the stored value
– Edge‐triggered: update when Clk changes from 0Edge‐triggered: update when Clk changes from 0 to 1
D QClk
D
Clk
D
Q
Sequential Elements
• Flip flop with write control– Only updates on clock edge when write control input is 1
– Used when stored value is required later
Clk
D Q Write
Clk
ClkWrite D
Q
RegisterRegister
D flip flop gate designD flip flop gate design
Second try for previous example
Clock + sequential logic = synchronous design
• Clock rate (clock cycles per second in MHz or GH ) i i f l k l ti ( l k i d)
design
GHz) is inverse of clock cycle time (clock period)CC = 1 / CR
one clock period
10 nsec clock cycle => 100 MHz clock rate10 nsec clock cycle 100 MHz clock rate
5 nsec clock cycle => 200 MHz clock rate
2 nsec clock cycle => 500 MHz clock rate
1 nsec (10‐9) clock cycle => 1 GHz (109) clock rate
500 psec clock cycle => 2 GHz clock rate
250 psec clock cycle > 4 GHz clock rate250 psec clock cycle => 4 GHz clock rate
200 psec clock cycle => 5 GHz clock rate
Clocking Methodology• Combinational logic transforms data during clock cyclesy– Between clock edges– Input from state elements, output to state p , pelement
– Longest delay determines clock period
CPU Overview
… with muxes
Can’t just join wires togethertogether Use multiplexers
… with muxes
A Few Words About Where We Are Headed
Performance = 1 / Execution time simplified to 1 / CPU execution time
CPU execution time = Instructions CPI / (Clock rate)
Performance = Clock rate / ( Instructions CPI )
Define an instruction set;
Design hardware for CPI = 1; seek improvements with
Try to achieve CPI = 1 with clock that is as high as that for CPI > 1
make it simple enough to require a small number of cycles and allow high
improvements with CPI >1
high as that for CPI > 1 designs; is CPI < 1 feasible?
clock rate, but not so simple that we need many instructions, even for very simple taskssimple tasks
Strategies for Speeding Up Instruction Execution
Performance = 1 / Execution time simplified to 1 / CPU execution time
CPU execution time = Instructions CPI / (Clock rate)
Performance = Clock rate / ( Instructions CPI )
Assembly line analogyAssembly line analogy
Single-cycle (CPI = 1)
Parallel processing or pipelining
Faster
Items that take longest to inspect dictate the speed of the assembly line
Multicycle (CPI > 1)
Faster(CPI > 1)