Synergy PLC Framework for CPX

User’s

Manual

Synergy PLC Framework for CPX

Sample Application Quick Start Guide

Target Device Synergy S3/S5/S7/R9A06G037

www.renesas.comRev.1.11 March 27, 2018

All information contained in these materials, including products and product specifications, represents information on the product at the time of publication and is subject to change by Renesas Electronics Corp. without notice. Please review the latest information published by Renesas Electronics Corp. through various means, including the Renesas Technology Corp. website (http://www.renesas.com).

(1) VOLTAGE APPLICATION WAVEFORM AT INPUT PIN: Waveform distortion due to input noise or a reflected wave may cause malfunction. If the input of the CMOS device stays in the area between VIL(MAX) and VIH (MIN) due to noise, etc., the device may malfunction. Take care to prevent chattering noise from entering the device when the input level is fixed, and also in the transition period when the input level passes through the area between VIL (MAX) and VIH (MIN).

(2) HANDLING OF UNUSED INPUT PINS: Unconnected CMOS device inputs can be cause of malfunction. If an

input pin is unconnected, it is possible that an internal input level may be generated due to noise, etc., causing malfunction. CMOS devices behave differently than Bipolar or NMOS devices. Input levels of CMOS devices must be fixed high or low by using pull-up or pull-down circuitry. Each unused pin should be connected to VDD or GND via a resistor if there is a possibility that it will be an output pin. All handling related to unused pins must be judged separately for each device and according to related specifications governing the device.

(3) PRECAUTION AGAINST ESD: A strong electric field, when exposed to a MOS device, can cause destruction

of the gate oxide and ultimately degrade the device operation. Steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it when it has occurred. Environmental control must be adequate. When it is dry, a humidifier should be used. It is recommended to avoid using insulators that easily build up static electricity. Semiconductor devices must be stored and transported in an anti-static container, static shielding bag or conductive material. All test and measurement tools including work benches and floors should be grounded. The operator should be grounded using a wrist strap. Semiconductor devices must not be touched with bare hands. Similar precautions need to be taken for PW boards with mounted semiconductor devices.

(4) STATUS BEFORE INITIALIZATION: Power-on does not necessarily define the initial status of a MOS device.

Immediately after the power source is turned ON, devices with reset functions have not yet been initialized. Hence, power-on does not guarantee output pin levels, I/O settings or contents of registers. A device is not initialized until the reset signal is received. A reset operation must be executed immediately after power-on for devices with reset functions.

(5) POWER ON/OFF SEQUENCE: In the case of a device that uses different power supplies for the internal

operation and external interface, as a rule, switch on the external power supply after switching on the internal power supply. When switching the power supply off, as a rule, switch off the external power supply and then the internal power supply. Use of the reverse power on/off sequences may result in the application of an overvoltage to the internal elements of the device, causing malfunction and degradation of internal elements due to the passage of an abnormal current. The correct power on/off sequence must be judged separately for each device and according to related specifications governing the device.

(6) INPUT OF SIGNAL DURING POWER OFF STATE: Do not input signals or an I/O pull-up power supply while

the device is not powered. The current injection that results from input of such a signal or I/O pull-up power supply may cause malfunction and the abnormal current that passes in the device at this time may cause degradation of internal elements. Input of signals during the power off state must be judged separately for each device and according to related specifications governing the device.

NOTES FOR CMOS DEVICES

Contents

1. Introduction .......................................................................................................................................... 5

2. Quick Start Guide ................................................................................................................................ 6

2.1 Hardware Setup .......................................................................................................................... 6

2.1.1 CPX3 - PMOD Board .......................................................................................................... 6

2.1.2 Synergy Board Connection ................................................................................................. 7

2.2 Software Setup ........................................................................................................................... 8

2.2.1 Toolchain Installation .......................................................................................................... 8

2.2.2 Importing The Demo Application In e2 studio ..................................................................... 9

2.2.3 Importing The Demo Application In IAR EWSYN ............................................................. 15

2.2.4 Terminal Application ......................................................................................................... 19

2.2.5 Demo Application LED’s ................................................................................................... 21

2.2.6 Using Demo Application On Other Synergy Boards ........................................................ 21

2.3 Demo Application Menu ........................................................................................................... 26

2.3.1 Demo Application .............................................................................................................. 27

2.3.2 Change BandPlan ............................................................................................................. 33

2.3.3 Data Flash Menu .............................................................................................................. 33

2.3.4 SROM Sub-Menu and Firmware Boot .............................................................................. 34

Revision History........................................................................................................................................ 36

R11QS0004ED0111 Rev.1.11 of 40 March 27, 2018

Synergy PLC Framework for CPX Sample Application Quick Start Guide

1. Introduction This quick start guide describes the basic functionality of the G3-PLC demo application running on Synergy SK-S7G2, DK-S3A7 and PK-S5D9 along with CPX3 PMOD Renesas evaluation board hardware.



2. Quick Start Guide 2.1 Hardware Setup

2.1.1 CPX3 - PMOD Board The CPX3 PMOD board contains a CPX modem device for PLC with built in filters for operation in different

frequency bands.

Figure 2.1-1 CPX3 PMOD board

The CPX modem is linked with the main microcontroller via an UART interface within PMOD connector. This interface is used to download CPX firmware and to send and receive modem commands and indications as well as power line network data.

The PMOD board is powered by a separate power supply that needs to be connected to the 12V DC power jack

to allow proper operation. The actual PLC signal is provided at the line coupler connector that needs to be connected to the line coupler

provided with the PMOD packet.



2.1.2 Synergy Board Connection The hardware setup needed is exemplarily shown in Figure 2 for the SK-S7G2. Evaluation boards for S3 and S5

are connected accordingly. The CPX3 PMOD board is connected to a Renesas Synergy SK-S7G2 board and with a power line coupler and the power supply.

Figure 3 shows the two USB cables which are plugged in for the demo application. These cables are plugged into

J5 (for the serial terminal interface) and J19/DEBUG_USB (for debugging through ARM J-Link debugger). Figure 4 gives a closer view of the PMOD connection to the SK-S7G2 board.

Figure 2.1-2 Synergy board, CPX PMOD board and pow er line coupler

Figure 2.1-3 USB cable connections



Figure 2.1-4 PMOD connection (PMODB/J14)

2.2 Software Setup This section describes the setup of the tool chain, project import and the terminal program configuration.

2.2.1 Toolchain Installation The used version of compiler, ISDE and SSP are shown in the table below.

Software Version Download

e2 studio 5.4.0.023 https://www.renesas.com/en-eu/products/synergy/software/tools/e2-studio.html

Synergy Software Package (SSP) 1.2.0 1.3.0 1.3.3

https://www.renesas.com/en-eu/products/synergy/software/ssp.html

GCC toolchain 4.9.3.20150529 https://launchpad.net/gcc-arm-embedded/4.9/4.9-2015-q3-update

Synergy Software Configurator (SSC) 5.4.0.023 https://www.renesas.com/en-eu/products/synergy/software/tools/renesas-ssc.html

IAR Embedded Workbench for Synergy (IAR EWSYN)

7.71.3 https://www.renesas.com/en-eu/products/synergy/software/tools/iar-ew-for-synergy.html

Synergy PLC Framework module 1.10 https://synergygallery.renesas.com



This PLC framework can be used in either e2 studio ISDE or in IAR Embedded Workbench for Synergy. When e2

studio is used then the following software tools have to be installed: 1. GCC toolchain (if not installed automatically) 2. e2 studio – shall auto detect and register the GCC installation 3. SSP 4. Synergy PLC Framework pack file When IAR EW is used then the following software tools have to be installed: 1. IAR EWSYN 2. SSC 3. SSP - must to be installed in the same folder with the SSC 4. Synergy PLC Framework pack file It is recommended to install the required tools in the order given above. Tools downloaded from www.renesas.com.

Under Platforms ->“Renesas Synergy™ Platform for IoT” select Software. Scroll down a bit and under “Explore Tools” you can find all tools and documentation on how to install them.

The G3 PLC framework consists of two parts, one is the CMSIS pack file containing the actual PLC framework,

the other is a demo application project available for both e2 studio and IAR EWSYN development environments. To install the PLC Framework please copy the file Renesas.SynergyCPX_PLC_Framework.1.x.x.pack into the

corresponding subfolder of your SSP installation (usually inside the e2 studio or SSC installation folder) under <SSP install folder>/internal/projectgen/arm/Packs. Please note that the name of the pack file must not be changed. The numeric version from the file name is the SSP version for which this pack file is built (not the version of the PLC Framework).

To interact with the demo application on a Windows 10 host no special driver installation is necessary. On a

Windows 7 or 8 system the Renesas Synergy Signed USB CDC Driver, which is part of this package, needs to be installed. After downloading the application to the Synergy Board it will be shown in the Device Manager as an “Unknown Device”. Right-Click on the device and select “Update Driver Software”. Select the folder containing the Renesas Synergy Signed USB CDC Driver and let Windows install the driver for you. After the installation the device should be shown as “Synergy Communication Port”.

2.2.2 Importing The Demo Application In e2 studio The demo application is located in a ZIP file:

SynergyPLCFramework_v1.10/Demo/e2Studio/demo_app_e2studio.zip.

In e2 studio import the project using the “Import”->”Existing projects into workspace” functionality as shown below:



Figure 2.2-1 Importing the project



An evaluation SSP license file can be found in the SSP installation folder in file “<SSP installation folder>/internal/projectgen/arm/Licenses/SSP_License_Example_EvalLicense_20170807.xml”.

Figure 2.2-4 Selecting the license





Project files need to be generated by the Synergy configurator before building the project:



Figure 2.2-7 Building the demo application

The project with the demo application can build the application in one of the several build configurations possible, described in the table below:

Build Configuration name Description

Certification Will build an application ready to be used in an automated certification environment. There is no user interface and only minimal output on the terminal console. This build configuration also selects various settings (IP port, encryption keys, etc.) that are specifically required during certification process.

Debug Will build an application with a terminal command line interface described in section 2.3. Release

After the build is successful the project is ready to be run. A debug session can be started immediately.



Figure 2.2-8 Running the demo application with the debugger

After starting the debug session and download of the demo application on the Synergy microcontroller the execution is stopped at the reset vector. Please check in section 2.2.4 on how to continue with the setup of the PMOD board and terminal application.

2.2.3 Importing The Demo Application In IAR EWSYN IAR EWSYN requires a license in order to run. One option is to use a time limited license code that can be obtained

via e-mail from: https://register.iar.com/specialedition/RenesasSynergyBeta The license code has to be input in the “License Manager” as shown below:



Figure 2.2-9 Activating a license

Figure 2.2-10 Activating a license

After license activation unpack the demo application located in

SynergyPLCFramework_v1.10/Demo/IAR/demo_app_iar.zip/demo_app_iar and open the workspace file S7SK_GPLC_Demo_IAR.eww:



Figure 2.2-11 Opening the workspace

At this point the path to the SSC installation and an SSP License have to be configured:

Figure 2.2-12 Synergy settings

Figure 2.2-13 Synergy settings

An evaluation SSP license file can be found in the SSP installation folder in file “<SSP installation

folder>/internal/projectgen/arm/Licenses/SSP_License_Example_EvalLicense_20170807.xml”. Now the project files can be generated by the Synergy Configurator:



Figure 2.2-14 Opening Synergy configurator

Figure 2.2-15 Generate Synergy project files

And the project can be built:

Figure 2.2-16 Building the demo application

After the project is built, a debugging session can be started immediately:

Figure 2.2-17 Running the demo application with the debugger

After starting the debug session and download of the demo application on the Synergy microcontroller the

execution is stopped at the main function. Please check in section 2.2.4 on how to continue with the setup of the PMOD board and terminal application.



When starting a debug session IAR EWSYN might ask for source files for ThreadX, NetXDuo or USBX components. For accessing these files the corresponding components need to be included as source files instead of precompiled libraries. This can be changes in the Synergy Software Configurator under the ‘Components’ tab in the ‘Express Logic’ section. Please note that the SSP evaluation license does not allow to view these files in a debug session. Hence, if debugging is not needed it is recommended to ignore this dialog and to use the precompiled components.

2.2.4 Terminal Application When the debug session is started the Synergy microcontroller will stop at either the reset vector or at the main

function. Ensure that the native USB connector J5 is connected to the PC. The standard input/output of the demo application is on this port.

It is important to note that the PMOD board has to be properly powered when starting the debug session otherwise firmware download will fail.

Open “Device Manager” with the Win+Pause keyboard combination, select Device Manager, then expand Ports section. Let the demo application run and observe what new COM port appears under “Ports (COM & LPT)” section:

Figure 2.2-18 Finding the COM port

The USB VID:PID pair for this new port is 045B:5300. In this example the new port is COM12 but it can be any other COM port number (Note that Windows 7 and 8 require the installation of an USB driver as described in Section 2.2.1). The port can be opened via a serial interface program like TeraTerm or PuTTY:



Figure 2.2-19 PuTTY configuration





Note that sometimes it might be necessary to disconnect and reconnect the USB cable at connector J5 to make the corresponding COM port available in Windows environment.

There is no output on the serial port until demo application finishes the CPX firmware download successfully. The main menu of the demo application can be refreshed by pressing the ‘Enter’ key if the terminal application is launched after the CPX firmware was downloaded successfully.

2.2.5 Demo Application LED’s The demo application uses Synergy board LED’s to signal current status as follows:

• LED1 – Green – is lit when ThreadX operating system is started successfully

• LED2 – Red – is lit when there is an error and application is locked in an infinite loop

• LED3 – Yellow – is lit during firmware download to CPX. With default settings for firmware download speed this download lasts for up to 5 seconds. During normal operation firmware download succeeds from the first try but if it fails the PLC framework module will try up to 5 times to perform firmware download.

The normal case is to start with Green and Yellow LED’s on. Then, after the firmware download is done only the Green LED remains ON. When Yellow LED turns off the demo application will print to the serial port the startup screen and the main menu.

2.2.6 Using Demo Application On Other Synergy Boards The demo application is configured to run on the S7G2 board by default. By modifying the configuration it can be adapted to run on other Synergy boards. The required configuration changes for PK-S5D9 and DK-S3A7 boards are shown below:

1. select the board (and optionally the CPU type)



Figure 2.2-22 Selecting different Synergy board

2. select the pin configuration

Figure 2.2-23 Selecting different Synergy board - p in configuration

3. select CPX reset pin (please check the table below for S5D9 and S3A7 boards)



Figure 2.2-24 Selecting different Synergy board – c hanging CPX reset pin

4. select CPX UART channel (please check the table below for S5D9 and S3A7 boards)



Figure 2.2-25 Selecting different Synergy board – c hanging UART channel

5. change the flash driver if necessary (HP – high performance or LP – low power)

Figure 2.2-26 Selecting different Synergy board - r emove the flash driver



Figure 2.2-27 Changing the flash driver

Settings to be used for the different boards:

Board CPX reset pin UART channel Flash driver Pin configuration S7G2 SK IOPORT_PORT_06_PIN_03 0 HP S7G2-SK.pincfg S5D9 PK IOPORT_PORT_06_PIN_03 0 HP S5D9-PK.pincfg S3A7 DK IOPORT_PORT_08_PIN_01 1 LP S3A7-DK.pincfg

Please note that the pin configurations specified in the table above are already provided together with the demo application. For other boards this pin configurations have to be set manually.



2.3 Demo Application Menu If the CPX3 firmware was downloaded successfully then the terminal program shows a startup screen after power-

on as shown in the picture below.

Figure 2.3-1 Demo application main menu

The demo application main menu has the following options: • [1 – Demo Application] Start the demo application as either device or server • [4 – Toggle Mac promiscuous Mode] • [7 – Toggle Verbose mode] toggle verbosity of the demo application • [8 – Change BandPlan] change the band plan of the CPX modem. Available options depend on the CPX

firmware. • [s – SYS Menu] system related options: version, ping, statistics, reboot, firmware, security • [0 – Data Flash Menu] options related to the management of non-volatile settings, including the EUI device

number and storage of the frame counter



2.3.1 Demo Application When selecting the demo application the user is asked to choose between peer or coordinator type:

Figure 2.3-2 Choosing the device type

To form a PLC network several conditions must be meet: - at least one coordinator and one or more peers need to be present and connected in the same physical PLC

network - the coordinator and the peers need to use the same protocol and the same band plan - each of the peers and coordinator in the network must have their own unique EUI64. This can be set individually

in the “Data Flash Menu” by changing the last 4 hex digits of the EUI64 on each board running the demo application

If the device type was selected as a coordinator it will start a PAN network. If the device type was selected as a peer it will start searching for PAN networks to join. If a PAN network is found then it will immediatelly join it. If more PAN networks are found then the user will be asked first on which network to join.

2.3.1.1 Coordinator Main Menu

The Coordinator Main menu allows the private SAP for the coordinator device, commands like network start or kick. And the mode also allows common service for adaptation layer within the ADP common SAP menu.



Figure 2.3-3 Coordinator main menu

Coordinator main menu:

• [1 - Start network]: Re-start the PAN network.

• [2 - Show connected devices]: Shows a list of devices that are currently joined to the PAN

• [3 - Kick device]: Removes a device from the PAN.

• [4 - Toggle Mac promiscuous mode]: If turned on, macPromiscuousMode is activated over ch1 on dual stack.

• [7 – G3 common SAP]: Proceeds to ADP Common Service

• [8 - Toggle verbose mode]: Toggles verbose mode. If turned off, no information messages are displayed.

• [0 – Data Flash Menu]: Proceed to data flash configuration menu

• [z – Return]: Back to the previous menu

2.3.1.2 Peer Main Menu

The Peer Main menu allows the private SAP for peer devices, commands like join and leave. And the mode also allows common service for adaptation layer within the ADP common SAP menu.



Figure 2.3-4 Device main menu

Device main menu:

• [1 - Join a network (with discovery)]: Re-start the joining procedure, which first scans for networks invoking the network discovery primitive. The discovery procedure is repeated multiple times if no active node could be found. Once an active node has been found, the user is asked to choose the network to join.

• [2 - Leave a network]: Starts the leave procedure by sending an LBP kick frame to the coordinator using ADPM-NETOWORK-LEAVE.request. After the transmission the device resets itself.

• [4 - Toggle Mac promiscuous mode]: If turned on, macPromiscuousMode is activated over ch1 on dual stack.

• [7 – G3 common SAP]: Proceeds ADP Common Service


• [0 – Data Flash Menu]: proceed to data flash configuration menu




2.3.1.3 ADP Common Service

Figure 2.3-5 ADP common service menu

ADP common service:

• [1 - Send data frame]: Sends a UDP data frame containing random data to a specified node in the network. The user has to provide the short address, the UDP payload length and has to decide if automatic route discovery shall be allowed or not. Furthermore, the demo application allows to send the same frame multiple times.

• [2 - Start route discovery]: A manual route discovery is initiated. The result is written to the routing table.

• [3 - Start path discovery]: A path discovery is started. If successful, the list of hops is displayed.

• [4 - Scan for devices]: Starts the discovery procedure to detect neighboring nodes.

• [5 – Configuration]: Proceed to the Configuration menu

• [6 - Reset ADP]: The reset adaptation layer menu. Note that after this menu, the device has left the network.

• [7 - Statistics/Log]: Proceed to the Statistics/Log menu


• [0 – Data Flash Menu]: proceed to data flash configuration menu

• [z - Return]: Back to the previous menu



2.3.1.4 Statistics/Log Menu

Figure 2.3-6 Statistics and logs menu

Statistics/Log menu:

• [0 - Clear Statistics]: Clear all statistics on the CPX3

• [1 - Clear Log]: Clear the log on the CPX3

• [2 - Get LML Statistics]: Reads and displays the statistics of the LML layer.

• [3 - Get MAC Statistics]: Reads and displays the statistics of the MAC layer.

• [4 - Get ADP Statistics]: Reads and displays the statistics of the ADP layer.

• [5 - Get EAP Statistics]: Reads and displays the statistics of the EAP layer.

• [6 - Get LML Log]: Reads and displays the log of the LML layer.

• [7 - Get MAC Log]: Reads and displays the log of the MAC layer.

• [8 - Get ADP Log]: Reads and displays the log of the ADP layer.

• [9 - Get EAP Log]: Reads and displays the log of the EAP layer.




2.3.1.5 Configuration Menu

Figure 2.3-7 Configuration menu

Configuration menu:

• [1 - Get MAC PIB entry]: Reads an entry from the MAC layer information base. The entry is selected by providing the corresponding attribute ID, which are displayed in menu 3.

• [2 - Set MAC PIB entry]: Writes an entry to the MAC layer information base. The entry is selected by providing the corresponding attribute ID, which are displayed in menu 3.

• [3 - Show all MAC PIB entries]: Displays all entries of the MAC layer information base.

• [4 - Get ADP IB entry]: Reads an entry from the ADP layer information base. The entry is selected by providing the corresponding attribute ID, which are displayed in menu 6.

• [5 - Set ADP IB entry]: Writes an entry to the ADP layer information base. The entry is selected by providing the corresponding attribute ID, which are displayed in menu 6.

• [6 - Show all ADP IB entries]: Displays all entries of the ADP layer information base.

• [7 - Get EAP IB entry]: Reads an entry from the EAP layer information base. The entry is selected by providing the corresponding attribute ID, which are displayed in menu 9.

• [8 - Set EAP IB entry]: Writes an entry to the EAP layer information base. The entry is selected by providing the corresponding attribute ID, which are displayed in menu 9.

• [9 - Show all EAP IB entries]: Displays all entries of the EAP layer information base.




2.3.2 Change BandPlan

Figure 2.3-8 Band plan options

The user can choose between 4 different bandplans from this menu.

[0 - Cenelec-A] [1 - Cenelec-B] [2 – ARIB] [3 – FCC] [z – Return] to the previous menu

2.3.3 Data Flash Menu

Figure 2.3-9 Data flash menu

Data flash menu:

• [0 – init dev config]: Initialize data flash as follows:

� EUI64: 0xFF0102FFFE000101 � PSK: 0x00112233445566778899AABBCCDDEEFF � PanID: 0x1001 this field uses only the Coordinator.

• [1- edit dev config]: Initialize data flash with unique EUI64 address. The user can set the lesser 4 hex digits of EUI64. The address will be mapped to 0xFF0102FFFE000000 to 0xFF0102FFFE00FFFF. Other parameters are the same with certification.

• [2 – disp all config]: Shows current config parameter stored on data flash. Please scroll-up to see the configuration.

• [3 – erase preserved]: Erase preserved information like frame counter and loadng sequence number.

• [z - Return]: Back to the previous menu



2.3.4 SROM Sub-Menu and Firmware Boot CPX3 can boot with firmware stored into the serial ROM (SROM) memory chip present on the CPX module or it

can request to boot from UART. The selection of the boot source is set by a resistor (R1) mounted on the CPX module as follows:

- if R1 resistor is present then by default CPX tries to first boot from SROM. If the SROM is empty or the firmware stored into SROM is corrupt it will request to boot via UART

- if R1 resistor is not present then CPX will try to boot from UART only By default resistor R1 is present on the board but the SROM is erased. Therefore CPX will try to boot from SROM

then it will fall back to UART boot. The PLC Framework has support to read/write or erase the SROM content and the demo application uses this

facility to manipulate SROM content with the following menu:

Figure 2.3-10 SROM menu

SROM sub-menu (under “Start Menu” >> “SYS Menu” >> “S-ROM menu”): • [r – Read baud rate and firmware header]: perform dump read of the first 8 bytes from SROM that contain

the index of the baud rate (normal and inverted) and perform dump read of the firmware header that contains a magic string and details of the firmware segments

• [b – Set new baud rate]: erase and set a new baud rate index for UART communication, see table bellow • [e – Erase everything]: erase entire SROM addressable memory (not a chip erase) • [c – Copy current firmware]: copy the firmware currently stored with the demo application into SROM.

Please note that the baud rate still has to be set separately • [z – Return]: back to the previous menu

Baud rate is selected by an index value as follows:

Index value Baud rate 0 9600 1 19200 2 38400 3 57600 4 115200 5 230400 6 300000 7 375000 8 460800 9 500000 a 750000 b 937500 c 1000000

Please be advised that PLC Framework needs to know if the CPX modem will boot form SROM or from UART.

IMPORTANT: once a new firmware is written into SROM the next time the user application will call the open function of the PLC framework, the ‘fw_src’ parameter of the configuration structure must be set to SF_PLC_CPX_FIRMWARE_SRC_SROM. Otherwise this parameter shall be set to SF_PLC_CPX_FIRMWARE_SRC_MCU. The default value of this parameter at the start of the demo application can also be set from the configurator menu as shown in the following screenshot:



Figure 2.3-11 Selecting the firmware source

Revision History Date Revision Section Substance September 10, 2015 Rev.0.01 - correction of erroneous description December 1, 2015 Rev.0.02 - Add Statistics/Lod app

Add macPromiscuous mode app for Dual use December 14, 2015 Rev.0.03 2.1.2 Modify configuration setting by Dip switch February 16, 2016 Rev.0.04 2.1.2 Modify configuration setting by Dip switch March 28, 2016 Rev.0.05 2.3 Add bandplan switch, modify certification mode. July 4, 2016 Rev.0.06 All Changed Synergy board from DK-S3A7 to SK-S7G2 July 5, 2016 Rev.0.07 All Review version cleaned August 29, 2016 Rev.0.08 3.2.1 Added section September 14, 2016 Rev.0.09 All Moved to newer REL template October 3, 2016 Rev.0.10 2.1 Added PMOD hardware description October 4, 2016 Rev.0.11 All Reviewed and cleaned version December 14, 2016 Rev.0.12 All Updated menus and SSP version, added IAR EWSYN March 03, 2017 Rev.0.13 2.2.1 Add description of build configurations March 18, 2017 Rev.0.14 - Update document number for release March 27, 2017 Rev.0.15 0, 2.2.1,

2.3.1 Changed title, fixed a typo and added mention about RFP driver, add band plan Cenelec-B

May 12, 2017 Rev. 1.00

All First approved release

August 08, 2017 Rev. 1.01

2.1 – 2.3

Updated after GooBE report

August 11, 2017 Rev. 1.02

2.2.3 Added note how to handle files that cannot be found during debug session in EWSYN.

September 14, 2017 Rev 1.03 2.1 2.2.2 2.2.3 2.2.4

Updated TOC – 2.1.1 appeared twice Updated some screenshots to better fit into page or to occupy less space Added two new screenshots with PuTTY configuration

December 14, 2017 Rev 1.10 * 2.2.1 2.2

2.2.4 2.2.6 2.3

2.3.4

Updated to SSP 1.3.2 SSC, 5.4.0.023. Add figure captions Updated versions, added simplification module Renamed section 2.2.2 and 2.2.3 Add figure 2.3-1 and note about COM driver manual select Add new section: porting to different boards Remove certification menu, move and update 2.3.4 into 2.3.1, update figures Add new section for SROM

March 27, 2018 Rev 1.11 2.2.1 2.2.4 2.3

2.3.1

Modified links for toolchain Removed necessity of RFP install, added install instruction for new USB driver Modified server->coordinator, device->peer and corresponding images


Publication Date: Rev.1.11 March 27, 2018

Published by: Renesas Electronics Corporation

R11QS0004ED0111

R11QS0004ED0111

Synergy PLC Framework for CPXSample Application Quick Start Guide

Synergy PLC Framework for CPX

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