Strain-relaxation of SiGe Layers on Insulator
40
RTO RTCVD poly RTCVD nitride Clean Module Load lock ellipso- meter foup NTU GIEE NanoSiOE Po-Wen Chen 2004/06/12 1 Strain-relaxation of Strain-relaxation of SiGe Layers on Insul SiGe Layers on Insul ator ator 指指指指 指指指 指指 ： 指指 指指指 ： 指指指指指指指指指指指指
description
Strain-relaxation of SiGe Layers on Insulator. 指導教授：劉致為 博士 學生：陳博文 台灣大學電子工程學研究所. Outline. Introduction Direct Wafer Bonding Technology SiGe-on-Insulator formation by wafer bonding and layer transfer Buckled SiGe layers Summary. Introduction. - PowerPoint PPT Presentation
Transcript of Strain-relaxation of SiGe Layers on Insulator
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Strain-relaxation of SiGe Strain-relaxation of SiGe Layers on InsulatorLayers on Insulator
指導教授：劉致為 博士學生：陳博文
台灣大學電子工程學研究所
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OutlineOutline
IntroductionIntroduction
Direct Wafer Bonding TechnologyDirect Wafer Bonding Technology
SiGe-on-Insulator formation by wafer SiGe-on-Insulator formation by wafer
bonding and layer transferbonding and layer transfer
Buckled SiGe layers Buckled SiGe layers
SummarySummary
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IntroductionIntroduction
Ref ： The International Technology Roadmap for Semiconductors (ITRS), 2001 edition
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MotivationMotivation
Combining the benefits of carrier mobility enhancement of strained Sistrained Si and the advantages of SOISOI.
SGOI (Strained Si on SiGe-On-Insulator)
= Strained SiStrained Si + SOISOI.
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OutlineOutline
• IntroductionIntroduction
• Direct Wafer Bonding TechnologyDirect Wafer Bonding Technology
• SiGe-on-Insulator formation by wafer SiGe-on-Insulator formation by wafer bonding and layer transferbonding and layer transfer
• Buckled SiGe layers Buckled SiGe layers
• SummarySummary
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Stengl’s model for silicon wafer Stengl’s model for silicon wafer bonding bonding
H
Si
O
H
O
H H
O
H
Si
O
HH
O
HH
O
H7A
Wafer A surface
Wafer B surface
Bonding interface
(a)
H
Si
O
3.5A
Wafer A surface
H
H
H
HO
O
H
H
O
H
H
O
Si
O
H
Wafer B surface
(B)
Si
1.6A
Wafer A surface
Si
O
Wafer B surface
H H
O
(C)
~200℃
>700℃
~
~
~
(a)Hydrogen bonding
between adsorbed
water molecules. T=RT
(b) Water molecules form
cyclic tetramer and
increase bond strength
T=200℃
(c) Water decomposition and
diffusion. Covalent bonds
forms. T≥700 ℃
~
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Direct Wafer BondingDirect Wafer Bonding
Device wafer
Handle wafer
Device wafer
Handle wafer
Device wafer
Handle wafer
Device wafer
Handle wafer
Megasonic acoustic cleaning
SC1 cleaningNH4OH:H2O2:H2ODI water rinseHydrophilic surface (OH-)
Pre-bondingAlignmentForm a single bonding wave
High temperature treatment8000C, O2, 30minStrength the chemical bonds
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Simple bonding check by breaking the wafers
Check by Breaking Wafer Check by Breaking Wafer MethodMethod
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TEM of Wafer BondingTEM of Wafer Bonding
Using Si with BPSG + bare Si wafer bonding
No defect at interface
Si Substrate
BPSG
Si wafer
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GOI Wafer FormationGOI Wafer Formation
The GOI are formed by bonding BPSG/Si and Ge at 600°C .
The measured Energy Dispersive Spectroscopy (EDS) from the interface layers.
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Infrared transmission systemInfrared transmission system
Monitor
IR lamp
IR viewing
Camera
Light with wavelengths longer than 1.10μm (Si) can pass through silicon
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Infrared image of a bonded Si/Si pairInfrared image of a bonded Si/Si pair
Bubbles with a diameter greater than 1 mm can be observed without IR microscopy.
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OutlineOutline
• IntroductionIntroduction
• Direct Wafer Bonding TechnologyDirect Wafer Bonding Technology
• SiGe-on-Insulator formation by wafer SiGe-on-Insulator formation by wafer bonding and layer transferbonding and layer transfer
• Buckled SiGe layers Buckled SiGe layers
• SummarySummary
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SGOI Process FlowSGOI Process Flow
BPSG
Si1-xGex
Host wafer
BPSG
Si1-xGex
Host wafer
BPSG
Handle wafer
Si1-xGex
BPSG
Handle wafer
Si1-xGex
BPSG
Handle wafer
Host waferH+ H+ H+ H+H+ H+ H+
1). Hydrogen implantation
2). Hydrophilic bonding at lowtemperature
3). Splitting annealing
4). Polishing
Ion implant. (hydrogen
dose=5E16)
Direct Wafer bonding.
H induced layer transfer.
Thin down.
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The schematic illustration of the The schematic illustration of the
hydrogen-induced exfoliation of siliconhydrogen-induced exfoliation of silicon
Si wafer(handle wafer)
BPSG
Si wafer(host wafer)
Rp
400℃ Si wafer(handle wafer)
BPSG
Si wafer(host wafer)
Rpcracks
Formation of point defect in the lower concentration of hydrogen implant.
Extensive disruption of the silicon lattice and 50~100A platelet formation.
Rearrangement of the defect structure above 400 0C.
H2 trap in the microvoids.
Development of these microvoids into cracks leading to complete layer transfer.
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Depth depends only on the implant energy with about 9nm / keV in silicon and silicon oxide.
0 20 40 60 80 100 120 1400
100
200
300
400
500
600
700
Imp
lan
t D
epth
(n
m)
Implant Energy (KeV)
Ion implantation DepthIon implantation Depth
0 20 40 60 80 100 120 140 160 180 200 2200
200
400
600
800
1000
1200
1400
1600
1800
2000
2200
This work
SIMS data
Dep
th (
nm
)
Energy (KeV)
TRIM 2003 SiGe sample (TEM) Si SIMS data
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Wafer Bonding Without Smart-cutWafer Bonding Without Smart-cut
Si0.9Ge0.1
BPSG
Wafer A(Host Wafer )
Wafer B(Handle Wafer )
Bonding Interface
BPSG
Si1-xGex
Wafer A
BPSG
Wafer B
400 nm
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SGOI Wafer FormationSGOI Wafer Formation
Buried Oxide(BPSG)
Si0.9Ge0.1
Si
100nm
Si1-xGex
Si
BPSG
Handle Wafer
100nm Si0.9Ge0.1 layer and 500nm Si layer transfer upon BPSG.
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SGOI Wafer FormationSGOI Wafer Formation
Si1-xGex
Si
BPSG
Handle Wafer
rough
100 nm
500 nm
The surface is rough after smart cut process.
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Microroughness Measurement After SmartcutMicroroughness Measurement After Smartcut
Host wafer Handle wafer
Roughness(r.m.s.)=6.17nmRoughness(r.m.s.)=7.34nm
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0 20 40 60 80 100 120 140 1600
2
4
6
8
10
Roo
t-M
ean-
Sq.
(nm
)
Implant Energy (KeV)
Microroughness MeasurementMicroroughness Measurement
Interfaces microroughness (R.M.S.) increases
with implantation energy of hydrogen ions
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-1250 -1000 -750 -500 -250 0 250 5001
10
100
1000
10000
Inte
nsi
ty
ArcSec
Si0.9
Ge0.1
800oC(with O2) 30min
800oC(with O2) 30min
Thermal Budget Thermal Budget
No lattice damage at 800oC, O2, 30min (Bonding and Smartcut recipe)
BPSG
Si1-xGex
Host wafer
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Si layer thin down (KOH etching)
AnnealingSi1-xGex
BPSG
Handle Wafer
Composed of three peaks: r-Si, s-Si, and Si in SiGe.
Lorentz model is used.
Peak shift to lower wave number with high temperature anneal.
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OutlineOutline
• IntroductionIntroduction
• Direct Wafer Bonding TechnologyDirect Wafer Bonding Technology
• SiGe-on-Insulator formation by wafer SiGe-on-Insulator formation by wafer bonding and layer transferbonding and layer transfer
• Buckled SiGe layersBuckled SiGe layers
• SummarySummary
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Diagram of relaxation mechanismsDiagram of relaxation mechanisms
Substrate
Insulator
Elastic strain layer
Substrate
Viscous layer
Relaxed layer
Substrate
Viscous layer
Relaxed layer
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10µm
Buckled SiGe Layers Buckled SiGe Layers
Two-dimensional perpendicular to each other
Buckled SiGe layers on SGOI compliant substrates
Oxidized for 300 sec at 960 with 1000 sccm oxygen flow℃
Substrate
BPSG
SiGe layer
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Buckling can also be seen by optical microscopy.
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Surface roughness (r.m.s.) increase with oxidized time.
Buckling seen by AFM for oxidation time > 30 sec.
Buckling seen by optical microscopy for oxidation time > 60 sec.
Buckling seen by AFM
Buckling seen by optical microscopy
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Micro-Raman
514.5 nm (Ar+ laser)
4.5 mW power
Detectable Raman peak shift (~0.5 cm-1) after 30 sec oxidation
Micro-Raman MeasurementMicro-Raman Measurement
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w/o SiGe layer
Buckled SiGe layers
edgy
Buckled SiGe layers directions near the patterned edgy are become along one-dimension, i.e., normal to the edge
Edgy EffectEdgy Effect1010
1020
1030
1040
1050
1010
1020
1030
1040
1050
-1
-0.5
0
0.5
1010
1020
1030
1040
1050
1000
1010
1020
1030
1040
10501000
1010
1020
1030
1040
1050
-0.5
0
0.5
1000
1010
1020
1030
1040
1050
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Buckling nucleus are randomly located at the initial oxidation
The undulation was well-developed for the time exceeding 30 sec
1 sec 5 sec
10 sec 30 sec
10um 10um
10um 10um
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Sinusoidal undulations are clearly observed by TEM
TEM Analysis of Buckled SiGe LayersTEM Analysis of Buckled SiGe Layers
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The Undulation Morphology vs. The Undulation Morphology vs. Ge FractionGe Fraction
1 10 100 1000 10000
0
10
20
30
40
50
60
70
80
90
100
110
Ro
ug
hn
ess(
R.M
.S.)
(n
m)
Oxidation Time (sec)
Si0.9
Ge0.1
Si0.8
Ge0.2
100 1000 10000
3.0
3.5
4.0
4.5
5.0
5.5
6.0
Wav
elen
gth
(u
m)
Oxidation time (sec)
Si0.9
Ge0.1
Si0.8
Ge0.2
Surface roughness (r.m.s.) increase with oxidized time.
The wavelength of the buckled SiGe layer increase with oxidized time.
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0.0 0.1 0.2 0.3 0.4 0.50
100
200
300
SiGe thickness
Mes
a si
ze(
m)
Ge fraction
120nm 100nm 80nm 60nm 40nm 32nm
Theoretical limits of buckling phenomenonTheoretical limits of buckling phenomenon
Upper region (larger mesa) : w/i buckled SiGe layers
Lower region (smaller mesa) : w/o buckled SiGe layers
Si substrate
BPSG
StrainedSiGe
Si substrate
BPSG
SiGe
Si substrate
BPSG
SiGe
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Buckled SiGe layers formation on MESA after oxidation
as grown (Si0.8Ge0.2)
150×150 μm2
as grown (Si0.9Ge0.1)
200×200 μm2
oxidation
oxidation
SiGe
BPSG
~100nm
<10nm
SiGe
BPSG
~100nm
<10nm
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MESA size = 70×70 μm2 for Si0.8Ge0.2 elastic layer
NoNo buckled SiGe layers formation on MESA after oxidation
as grown (Si0.8Ge0.2)
70×70 μm2
oxidationSiGe
BPSG
~100nm
<10nm
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0 10 20 30 40 500
100
200
300
400
500
TSiGe
=100 nm
No Buckling
Buckling
200x200 (m2)
150x150 (m2)
125x125 (m2)
75x75 (m2)
25x25 (m2)
Mes
a si
ze (m
)
Ge fraction (%)
Experiment results are well consistent with theoretical buckled SiGe Layers limit
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OutlineOutline
• IntroductionIntroduction
• Direct Wafer Bonding TechnologyDirect Wafer Bonding Technology
• SiGe-on-Insulator formation by wafer SiGe-on-Insulator formation by wafer bonding and layer transferbonding and layer transfer
• Buckled SiGe layers Buckled SiGe layers
• SummarySummary
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SummarySummary
Strong buckling for exceeding 30 sec oxidation.
Strain-relaxed compliant SGOI substrate has been fabricated by wafer bonding and hydrogen-induced layer transfer techniques.
Experiment results are well consistent with theoretical buckled SiGe layers limit.
Semiconductor films on insulator are successfully achieved by wet chemical activated bonding.
