Sprinkler Buddy
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Buddy Presentation #5: “Transistor Level Schematics and Another Floor Plan” 2/21/2007 Team M3 Sasidhar Uppuluri Kalyan Kommineni Kartik Murthy Panchalam Ramanujan Design Manager: Bowei Gai “Low Cost Irrigation Management For Everyone ! ”
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Sprinkler Buddy. “Low Cost Irrigation Management For Everyone ! ”. Presentation #5: “Transistor Level Schematics and Another Floor Plan” 2/21/2007. Team M3 Sasidhar Uppuluri Kalyan Kommineni Kartik Murthy Panchalam Ramanujan Design Manager: Bowei Gai. Current Status. - PowerPoint PPT Presentation
Transcript of Sprinkler Buddy
Sprinkler Buddy
Presentation #5:
“Transistor Level Schematics
and Another Floor Plan”
2/21/2007
Team M3Sasidhar UppuluriKalyan Kommineni
Kartik Murthy Panchalam Ramanujan
Design Manager: Bowei Gai
“Low Cost Irrigation Management For Everyone ! ”
Current Status Determine Project Develop Project Specifications Plan Architectural Design
Determination of all components in design Detailed logical flowchart
Design a Floor Plan (refined again)
Create Structural Verilog Make Transistor Level Schematic (some control issues)
Layout Testing (Extraction, LVS, and Analog Sim.)
Floor Plan Old (Naïve) Floor Plan
Somewhat Better Floor Plan
Last Week’s Floor Plan
This Week’s First Try
Current Floor Plan
Individual Modules:
Block Metal Layers That Can be Used
40:20 Muxes M1 & M2
60:20 Muxes M1 & M2
Counters M1 & M2
KC ROM M1 & M2 & M3 & M4
P ROM M1 & M2 & M3 & M4
Metric Storage SRAMS M1 & M2 & M3 & M4
Constant Storage ROM M1 & M2 & M3 & M4
Floating Point Adders M1 & M2 & M3
Floating Point Multipliers M1 & M2 & M3 & M4
10 Bit Registers M1 & M2
Transistor Count …
Block (# used) Old TC New TC
40:20 Muxes (6) ~480 362
60:20 Muxes (2) ~720 644
Counter (2) ~250 220
KC ROM (1) ~778 1256
P ROM (1) ~82 122
Metric Storage SRAMS (2)
~2522 2430
Constant Storage ROM (1)
~202 428
Floating Point Adder (4)
~3000 3210
Floating Point Multiplier (2)
~2800 1398
10 Bit Registers (9)
~140 210
Datapath Logic / Misc.
~2000 2305
Total =
30,397
New Design SizeBlock (# used) Size Estimate (um)
40:20 Muxes (4) 20 x 80
60:20 Muxes (2) 20 x 120
Counter (2) 12 x 17
KC ROM (4 parts) 181 x 8
P ROM (1) 70 x 8
Metric Storage SRAMS (2)
181 x 60
Constant Storage ROM (1)
181 x 8
Floating Point Adder (4)
100 x 100
Floating Point Multiplier (2)
95 x 125
10 Bit Registers (8) 50 x 10
• 457um x 391 um• ~ 1 : 1.16 aspect ratio• .178 mm^2 area• .168 Transistor Density
Schematics: SRAM
Schematics: Flip Flops
Schematics: Read & Write to SRAM
Read
Write
Schematics: ROMs
Schematics: FP Units
Multiplier Adder
Schematics: Control
Hourly Update FP Adder
Design Challenges and Implementation
DecisionsFor The Past Week
Design Challenge
Translation to HW
Low Power Design
• Logic Reduction • Sizing of Gates According to Logical Effort
Problems/QuestionsSmall Problems with Control Logic in
Schematic Can we reduce more transistors with
better logic ? Any way to move the SRAM from the
middle of our chip?
For Next WeekPerfect our Control Logic in the
Schematic Continue to reduce and optimize gates Start Layout !
Some Other SlidesFor Reference…
Block Size Estimates
Block (# used) Size Estimate (um)
40:20 Muxes (4) 20 x 80
60:20 Muxes (2) 20 x 120
Counter (2) 12 x 17
KC ROM (4 parts) 181 x 8
P ROM (1) 70 x 8
Metric Storage SRAMS (2) 181 x 60
Constant Storage ROM (1) 181 x 8
Floating Point Adder (4) 100 x 100
Floating Point Multiplier (2) 95 x 125
10 Bit Registers (8) 50 x 10
