Sprinkler Buddy

Presentation #3:

“New and Improved Floor Plan

and Structural Verilog”

2/14/2007

Team M3Panchalam Ramanujan

Kalyan KommineniKartik Murthy

Sasidhar Uppuluri Design Manager: Bowei Gai

“Low Cost Irrigation Management For Everyone ! ”

Current Status Determine Project Develop Project Specifications Plan Architectural Design

Determination of all components in design Detailed logical flowchart

Design a Floor Plan (refined) Create Structural Verilog

(All Components done/simulated, tweaking control)

Make Transistor Level Design and Schematic Layout Testing (Extraction, LVS, and Analog Sim.)

Slightly Revised Transistor Count …

Block (# used) Transistor Count

40:20 Muxes (6) ~480

60:20 Muxes (2) ~720

Counter (2) ~250

KC ROM (1) ~778

P ROM (1) ~82

Metric Storage SRAMS (2) ~2522

Constant Storage ROM (1) ~202

Floating Point Adder (4) ~3000

Floating Point Multiplier (2) ~2800

10 Bit Registers (9) ~140

Datapath Logic / Misc. ~2000

Total =

~ 31,786

Block Size Estimates

Block (# used) Size Estimate (um)

40:20 Muxes (4) 20 x 80

60:20 Muxes (2) 20 x 120

Counter (2) 12 x 17

KC ROM (4 parts) 181 x 8

P ROM (1) 70 x 8

Metric Storage SRAMS (2) 181 x 60

Constant Storage ROM (1) 181 x 8

Floating Point Adder (4) 100 x 100

Floating Point Multiplier (2) 130 x 130

10 Bit Registers (8) 50 x 10

Floor Plan Old (Naïve) Floor Plan

Somewhat Better Floor Plan

Current Floor Plan

Individual Modules: Floating Point Add

Outputs

Inputs

Will Use Metals 1-4

No Metal 3 below here

Individual Modules: Floating Point Multiply

Outputs

Inputs

Will Use Metals 1-4

Inputs

Outputs

Individual Modules: Everything Else

Block Metal Layers That Can be Used

40:20 Muxes M1 & M2

60:20 Muxes M1 & M2

Counters M1 & M2

KC ROM M1 & M2 & M3 & M4

P ROM M1 & M2 & M3 & M4

Metric Storage SRAMS M1 & M2 & M3 & M4

Constant Storage ROM M1 & M2 & M3 & M4

Floating Point Adders M1 & M2 & M3 & M4

Floating Point Multipliers M1 & M2 & M3 & M4

10 Bit Registers M1 & M2

Metal Directionality M1, M2

Local Connections Ground and VDD

M3,M4 Clock Inside FP Units Global Routing Control Signals

New Design SizeBlock (# used) Size Estimate (um)

40:20 Muxes (4) 20 x 80

60:20 Muxes (2) 20 x 120

Counter (2) 12 x 17

KC ROM (4 parts) 181 x 8

P ROM (1) 70 x 8

Metric Storage SRAMS (2)

181 x 60

Constant Storage ROM (1)

181 x 8

Floating Point Adder (4)

100 x 100

Floating Point Multiplier (2)

130 x 130

10 Bit Registers (8) 50 x 10

• 454um x 450 um• ~ 1 : 1 aspect ratio• .2 mm^2 area• .142 Transistor Density

Control Verilog

wire [9:0] hu_temp,hu_tmax,hu_tmin,hu_temptoadd; //HU Control Signals wire hu_tmax_en,hu_tmin_en,hu_mux_sel,hu_add_start,hu_temp_en; //HU Output Signals wire hu_add_done,hu_fsm_start,hu_add_sign; wire [9:0] hu_add_out;

huFSM _huFSM(hu_tmax_en,hu_tmin_en,hu_mux_sel,hu_add_start,hu_temp_en, hu_fsm_start,hu_add_sign,hu_add_done,clk,rst);

not _hun0(not_g_dclk,g_dclk); and _huEn(hu_fsm_start,g_hclk,not_g_dclk);

reg_x #(10,0) _temp(.q(hu_temp),.d(g_temp),.clk(clk),.reset(rst),.en(hu_temp_en)); reg_x #(10,10'b0011110001) _tmax(.q(hu_tmax),.d(hu_temp),.clk(clk),.reset(rst),.en(hu_tmax_en)); reg_x #(10,10'b0011110001) _tmin(.q(hu_tmin),.d(hu_temp),.clk(clk),.reset(rst),.en(hu_tmin_en));

mux21_10 _huMux(.out(hu_temptoadd),.sel(hu_mux_sel),.a(hu_tmax),.b(hu_tmin));

fpadder _fpahr(.out(hu_add_out),.done(hu_add_done),.a(hu_temp),.b(hu_temptoadd), .addSub(1'b1),.start(hu_add_start),.clk(clk),.rst(rst)); assign hu_add_sign=hu_add_out[9];

Multiplier Verilog

wire signa,signb,cout1,cout2;

//Assign pieces of Inputs assign signa = a[9]; assign signb = b[9]; assign expa = a[8:4]; assign expb = b[8:4]; assign siga = a[3:0]; assign sigb = b[3:0];

//Calculate Exponent addSub_6 ab(preExp,cout1,{1'b0,expa},{1'b0,expb},1'b0); addSub_6 ba(postExp,cout2,preExp,6'b001111,1'b1);

//Calculate Significand uMult_5 um(postSig,{1'b1,siga},{1'b1,sigb});

//Normalize fpmultnormalize nm(postNormSig,postNormExp,postSig,postExp);

//Assign Final Output assign out[8:4]=postNormExp[4:0]; assign out[3:0]=postNormSig; xor msign(out[9],signa,signb);

endmodule

//modify if rounding later,combine adders later module fpmultnormalize(sigPostNorm,expPostNorm,sigPreNorm,expPreNorm);

output [3:0] sigPostNorm; output [5:0] expPostNorm; input [9:0] sigPreNorm; input [5:0] expPreNorm;

wire cout; wire [5:0] addAmnt;

//Adjust Significand mux21_4 mm(sigPostNorm,sigPreNorm[9],sigPreNorm[7:4],sigPreNorm[8:5]);

//Adjust Exponent mux21_6 mm5(addAmnt,sigPreNorm[9],6'b000000,6'b000001); //reduce me later addSub_6 as5(expPostNorm,cout,expPreNorm,addAmnt,1'b1); endmodule

Adder Verilog

module fpAddSigUnit(sigFinal,siga,sigb,expDiff,compExpab,clk,rst,takeShiftSig,signa,signb,compSigab,sRaEn,sRbEn);

output [8:0] sigFinal; output compSigab; input [3:0] siga,sigb; input [3:0] expDiff; input compExpab,takeShiftSig,sRaEn,sRbEn,clk,rst,signa,signb;

wire compSigab,addSub,coutFinal; wire [7:0] sigFinala,sigFinalb,sigMuxa,sigMuxb,shOut,mShiftOut; wire [9:0] sigPreOut,sigFinOut; //q,d,clk,rst,en //Choose to register original or shifted sig mux21_8 mSiga(sigMuxa,takeShiftSig,{1'b1,siga,3'b000},shOut); mux21_8 mSigb(sigMuxb,takeShiftSig,{1'b1,sigb,3'b000},shOut); reg_x #(8,0) sRa(sigFinala,sigMuxa,clk,rst,sRaEn|(takeShiftSig&(~compExpab)) ); reg_x #(8,0) sRb(sigFinalb,sigMuxb,clk,rst,sRbEn|(takeShiftSig&compExpab) );

//Choose Significand to shift and shift it //0-> b is bigger, 1-> a is bigger mux21_8 mshift(mShiftOut,compExpab,sigFinala,sigFinalb); sbshiftr_8 sbs(shOut,mShiftOut,expDiff);

//AddSub significands based on signs //10 bit adder to accomodate negative bit and adding secret bits comp8 c8(compSigab,sigMuxa,sigMuxb); xor x0(addSub,signa,signb); addSub_10 addSigs(sigPreOut,coutFinal,{2'b00,sigMuxa},{2'b00,sigMuxb},addSub);

Design Challenges and Implementation

DecisionsFor The Past Week

Design Challenge

Translation to HW

Low Power Design

• Ripple Carry Adder• Quiet Bit Line SRAM Architecture • Sense Amplifier Flip Flop

Quiet-Bitline Architecture

for SRAM No Pre-Charging One side driving scheme where only a strong

‘0’ is forced in bit or bit bar when writing 85% power reduction over traditional

methods

Citation: “A Low-Power SRAM Design Using Quiet-Bitline Architecture” by Cheng et. al.

Problems/QuestionsOur Floor plan has a hole in the top

right…Need to more accurately determine

timing delays through modules

For Next WeekMake Transistor Level SchematicBegin Layout of Smaller ModulesContinue to Revise and Update Floor

Plan