Institute of Applied Microelectronics and Computer Engineering

College of Computer Science and Electrical Engineering, University of Rostock Slide 1

Spezielle Anwendungen des VLSI – Entwurfs

Applied VLSI design

Course and contest

Results of Phase 3

Nam Pham Van

Institute of Applied Microelectronics and Computer Engineering

College of Computer Science and Electrical Engineering, University of Rostock

shift

a

s

Change of coefficient

Slide 2

• Reduce an addition to one shift operation

On FPGA no noticeable influence

On VLSI noticeable power reduction

Hex Binary CSD (Canonical Sign Digit)F9 1 1 1 1 1 0 0 1 0 0 0 0 0 -1 0 0 1 0

0 0 0 0 -1 0 0 0 0

shift

a

RCA

s

Institute of Applied Microelectronics and Computer Engineering

College of Computer Science and Electrical Engineering, University of Rostock

Assumption:

• Increase the frequency better

• Lower the voltage more effective Metric

Design assumption

Slide 3

Benchmark:

Institute of Applied Microelectronics and Computer Engineering

College of Computer Science and Electrical Engineering, University of Rostock

Behavior of the metric

Slide 4

• Metric is better with lower voltage

400 500 600 700 800 900 1000 11000

1E+027

2E+027

3E+027

4E+027

5E+027

6E+027

7E+027

8E+027

9E+027Brent Kung adder

Vdd = 1.0VVdd = 1.1VVdd = 1.2VVdd = 1.3V

f [MHz]

Metric [1/J^2]

Institute of Applied Microelectronics and Computer Engineering

College of Computer Science and Electrical Engineering, University of Rostock

Comparison of different adders

Slide 5

Values for VLSI

Brent Kung adder Han Carlson adder

Frequency - f 500 MHz 500 MHz

Voltage - Vdd 1.0 V 1.0 V

Library COREHVTtyp10V COREHVTtyp10V

Power PTotal (W) 2.7482*10-11 2.8428*10-11

Metric (1 / J2) [9.1049*1027] [8.8045*1027]

Institute of Applied Microelectronics and Computer Engineering

College of Computer Science and Electrical Engineering, University of Rostock

Design & architecture

Slide 6

Brent Kung adder (a parallel prefix adder):

• Minimum number of nodes (implies minimum area)

• Efficient

• Suitable for VLSI

• Implemented version:

10 bit

11 bit

16 bit

X0X1X2X3X4X5X6X7X8X9X10X11X12X13X14X15

S0S1S2S3S4S5S6S7S8S9S10S11S12S13S14S15

Institute of Applied Microelectronics and Computer Engineering

College of Computer Science and Electrical Engineering, University of Rostock

Filter response

Slide 7

Institute of Applied Microelectronics and Computer Engineering

College of Computer Science and Electrical Engineering, University of Rostock

Results of ASIC design

Slide 8

Mandatory values for ASIC

Frequency - f 500 MHzArea - A 3433.5598 μm²

Power - PDyn 1.5078 mW

Power - PLeak 18.2268 nW

Power - PTotal 2.7482*10-11 W

# Pipeline Stages 8

Metric (1 / J2) [9.1049*1027]

Synopsys Configuration:

Library:• COREHVTtyp10V• Vdd = 1.0 V

Power:• set_max_dynamic_power 0 mW• set_max_leakage_power 0 mW

Compile:• compile_ultra

Institute of Applied Microelectronics and Computer Engineering

College of Computer Science and Electrical Engineering, University of Rostock

Future improvements

• Dynamic Voltage Scaling (DVS)

• Dynamic Frequency Scaling (DFS)

• Reducing the parasitic capacitance C

• Special low power design e. g. stack-effect

• Reduction of unnecessary switching activity

Slide 9

Institute of Applied Microelectronics and Computer Engineering

College of Computer Science and Electrical Engineering, University of Rostock

Thank you for your attention!

Slide 10