SiGe CVD,fundamentals and device

applications

SiGe CVD,fundamentals and device

applications

Dr Derek HoughtonAixtron Inc

ICPS, Flagstaff July 2004

Dr Derek HoughtonAixtron Inc

ICPS, Flagstaff July 2004

Á OVERVIEW

1. Introduction1. Introduction

2. SiGe Market Survey2. SiGe Market Survey

3. Fundamentals of SiGe CVD3. Fundamentals of SiGe CVD

4. CVD Equipment for SiGe4. CVD Equipment for SiGe

5. Device aplications and commercialization

5. Device aplications and commercialization

6. SiGe materials engineering, metrology6. SiGe materials engineering, metrology

7. Summary and Discussion7. Summary and Discussion

SiGe’s Market Opportunity...

Si CMOS/BJTs SiGe HBTs/CMOS? III-V FETs/HBTs

RoadPricing

CollisionAvoidance

DTHDBSOC-192

ISMDCSDECT

GSM

WLANFRALMDS

FRAOC-48G-Ethernet

GPS x-bandRadar

Automotive

Navigation/Areospace

Communications

WLAN

0.1 0.2 0.5 1 2 5 10 20 50 100Frequency (GHz)

SiGe HBT device structure and process description

Only difference: BaseSiGe replaces Silicon

Key figures of SiGe HBT processKey figures of SiGe HBT process

• SiGe BiCMOS uses SiGe HBT + SiCMOS

• SiGe HBT shows same process as Si BT with exception of 30-80 nm thin SiGe base layer (Ge <25%)

• Growth rates used are about 30 nm/min (~ 2 min for base layer)

• Typically, same LPCVD growth chambers can deposite both Si and SiGe layers

• Depending on SiGe HBT process, base layer deposited either using selective or differential epitaxy

• SiGe BiCMOS uses SiGe HBT + SiCMOS

• SiGe HBT shows same process as Si BT with exception of 30-80 nm thin SiGe base layer (Ge <25%)

• Growth rates used are about 30 nm/min (~ 2 min for base layer)

• Typically, same LPCVD growth chambers can deposite both Si and SiGe layers

• Depending on SiGe HBT process, base layer deposited either using selective or differential epitaxy

SiGe‘s main market is telecommunication (wireless and datacom)SiGe IC forecast by market, 2000 to 2005, in mil. US$

0

200

400

600

800

1000

1200

1400

1600

1800

2000 2001 2002 2003 2004

YEAR

CAGR=+125%CAGR=+125%

2005

Industrial

Computer

Consumer

Communications

SiG

eIC

Mar

ket [

Mio

. US$

]

• SiGe viable alternative to GaAs

• Main markets being targeted:

• Cellular / Cordless / WLAN

• FO-Datacom(MUX/DEMUX)

• PC interface cards / LAN

• Future trends:• integrated low power RF-

front end of most handsets• First choice for up/down

conversion in tuners/ transceivers

• will dominate 40 Gbps

• SiGe viable alternative to GaAs

• Main markets being targeted:

• Cellular / Cordless / WLAN

• FO-Datacom(MUX/DEMUX)

• PC interface cards / LAN

• Future trends:• integrated low power RF-

front end of most handsets• First choice for up/down

conversion in tuners/ transceivers

• will dominate 40 Gbps

CommentsComments

Source: Strategies Unlimited, 1999CAGR: Compound Average Growth Rate

Strained Si: prototypes from Intel, IBM & UMC demonstrated

Almost all large Si-CMOS manufacturers are presenting cross sectional pictures of CMOS transistors (with gate lengths between 65 and 90 nm) which use Strained-Si technology. Intel and IBM use their own technology, whereas UMC is Amberwave’s

licensee

Strained-Si HeteroWafer® technology: process and actual status

• Strained Si technology enables improvement in CMOS performance and functionality via replacement of the bulk, cubic-crystal Si substrate with a Si substrate that contains a tetragonally distorted, biaxially strained Si thin film at the surface

• Different types of processes developed and patented by the main players: Amberwave(IQE) - AIXTRON, IBM,Toshiba & Intel

• First demos of perfect working 52 Mbit SRAMs with 90 nm CMOS devices on 300 mm wafers available from Intel. Ramp-up of Pentium 4 production with Str.-Si planned for 2H/2003 !

• Process and substrate costs still not 100% fixed. Price expectations for substrate from IC manufacturers still unknown

• Strained Si technology enables improvement in CMOS performance and functionality via replacement of the bulk, cubic-crystal Si substrate with a Si substrate that contains a tetragonally distorted, biaxially strained Si thin film at the surface

• Different types of processes developed and patented by the main players: Amberwave(IQE) - AIXTRON, IBM,Toshiba & Intel

• First demos of perfect working 52 Mbit SRAMs with 90 nm CMOS devices on 300 mm wafers available from Intel. Ramp-up of Pentium 4 production with Str.-Si planned for 2H/2003 !

• Process and substrate costs still not 100% fixed. Price expectations for substrate from IC manufacturers still unknown

Actual status Strained-Si processActual status Strained-Si process

Strained Si process of Amberwave: One of the Strained Si pioneers

•Typically, 2 to 4 µm thick graded SiGe buffer layer, followed by thin (<20 nm) strained Si channel layer

•Depending on substrate Ge concentration, clear mobility and transistor current drive improvement

• Through Amberwave’s proprietary chemical-mechanical polishing (CMP) intermediate process, SiGe buffer layer surface roughness is eliminated before Si layer deposi-tion, resulting in same quality compared to bulk Si wafers

•Typically, 2 to 4 µm thick graded SiGe buffer layer, followed by thin (<20 nm) strained Si channel layer

•Depending on substrate Ge concentration, clear mobility and transistor current drive improvement

• Through Amberwave’s proprietary chemical-mechanical polishing (CMP) intermediate process, SiGe buffer layer surface roughness is eliminated before Si layer deposi-tion, resulting in same quality compared to bulk Si wafers

Strained Silicon CMOS technology *SiGe deposited selectively,

Intel Pentium IV in production

Strained silicon mainly addresses high-end digital CMOS markets

0

20000

40000

60000

80000

1000000

20000

40000

60000

80000

100000

2003 2004 2005 2006 2007

CAGR*= 12.5%CAGR*= 12.5%

YEAR

Dig

ital C

MO

S El

ectr

onic

Mar

ket [

Mio

. US$

]

Si FPGAs

Si Digital Signal Processors (DSPs)

Si Microprocessors (MPUs)

Si Micro-controllers (MCUs)

Digital electronic market forecast and expected strained Si penetration, 2003 to 2007, in mil. US$

Source: VLSI Research, 2002

CAGR*= >200%CAGR*= >200%

YEARStra

ined

Sib

ased

CM

OS

Mar

ket [

Mio

. US$

]

2003 2004 2005 2006 2007

Source: AIXTRON estimates

AssumptionsAssumptions• Main application will be high-end

Microprocessors like IBM‘s Power-PC, SUN‘s Sparc, AMD‘s Athlon, Intel Pentium / Itanium.

• Main markets being targeted: PCs, workstations, game consoles, other internet appliances

• Future trends: Strained Si penetrates 3G/WLAN wireless applications (DSPs/MCUs)

• Main application will be high-end Microprocessors like IBM‘s Power-PC, SUN‘s Sparc, AMD‘s Athlon, Intel Pentium / Itanium.

• Main markets being targeted: PCs, workstations, game consoles, other internet appliances

• Future trends: Strained Si penetrates 3G/WLAN wireless applications (DSPs/MCUs)

CAGR: Compound Average Growth Rate

Effect of air exposure prior to HF passivationC

arbo

n an

d O

xyge

n co

ncen

trat

ions

(cm

-3)

1017

1018

1019

1020

10 21

RCA + 4 hours in air + HF dip

RCA + HF dip

Oxygen

Carbon

0 500 1000 1500 2000 2500 3000 3500

Depth (Å)

Partial pressure for oxygen incorporation from H2O and O2

AIX 2600G3: up to 7x150 or 3x200 mmTricent SiGe Cluster Tool: 150, 200 or 300 mm

Tricent® vs. Multiwafer Reactor®

AIXTRON‘s flexible epi systems for Strained Si / SiGe

SiGe UHVCVDQuartz tube

SiH4GeH4B2H6PH3

P~ 10-3 mbarTg<600C

wafers

molecular flow Ā uniform growthsticking coefficients~10-3

UHV initial conditions, P~10-9 m barhydrogen terminated Si wafers at start

Hot wall UHVCVD Batch tool

Uniform Gas Distribution byAIXTRON´s Closed Coupled Showerhead

Gro

wth

Rat

e

Distance to gas inlet

Closed Coupled Showerhead ReactorHorizontal Quarz Tube Reactor

Gro

wth

Rat

e

Distance to gas inlet

SiGe Tricent®

Dual-Chamber Showerhead (pat. pend.)

Water-Cooled Reactor LidShowerhead Detail

N2/H2Gas Mix

Temperature Control Concept

ProcessChamber

Showerhead

TSubstrTLid TSHCoated GraphiteSusceptorWafer

SiGe Tricent®Unique CVD chamber featuresdeveloped beyond industry standards

Á ShowerheadÁ Temperature controlÁ ShowerheadÁ Temperature control

Tricent®Customer Process Support

CleanRoom Wall

Cassette Station

Temp Process Gas Sources550-680°C SiGe:C SiH4 + GeH4 + SiCH6650-750°C SiGe SiH4 + GeH4730-800°C sel. SiGe SiH2Cl2 + HCl + GeH4800-900°C SEG SiH2Cl2 + HCl

Process platform for HBTs, HFETs and BiCMOS- pure Silicon Growth- differential SiGe:C growth - selective SiGe:C growth- SiGe on SOI

SiGe HBT in a BiCMOS flow

LOCOS

N+

Polysilicon Emitter

Base SiGeSpacers

Metallisation

EpitaxialLayer N

HBTMOS

n+

XTEM of Si deposition on Si/oxide

HBT base structure SIMS profiling

10 15

10 16

10 17

10 18

10 19

0

5

10

15

0 500 1000 1500

CVD-197

Bor

on c

onc.

(cm-3

)G

ermanium

conc. (%)

Depth (Å)

SIMS analysis (cameca)

Ge

Gummel Plot, npn HBT

10 -13

10 -11

10 -9

10 -7

10 -5

10 -3

0 0.2 0.4 0.6 0.8 1 1.2 1.4

IcIb

I C, I

B(A

)

VBE

(V)

NPN11A, CVD-140

Triangular SiGe base profile

AE

= 0.6 x 1.2 micron 2

VCB

= 0

CMOS transistor

Selective SiGeEpitaxy

DC Houghton J.Appl.Phys.1991

Strained Silicon on SOI wafer by layer

transfer

SOITEC

Strained Silicon on graded SiGe buffer

Amberwave

Ge%

Strained Si Strained SiSiGe stack

SiGe grade

Si substrateSi substrate

DCD x ray diffraction

SIMS profileStrained Si – Graded SiGe BufferCs Cascade Scientific

Cou

nts

Per S

econ

d

12C

16O

29Si+30Si->70GeSample A3

12/04/2003

Low O and C background No Interface peak

interface

SIMS

1E+23 1E+05

1E+221E+04

1E+17

1E+18

1E+19

1E+20

Con

cent

ratio

n 1E+211E+03

1E+02

1E+01

1E+16 1E+00

0 2 4 8 106Depth (microns)

Strained Si layers

SiGe graded 5...40%

SiGe 40%

Pure Ge on Silicon substratesLow defect density Ge without SiGe graded buffer

Ge

Si wafer

Cross sectional TEMPlan view TEM (looking down

through Ge cap)

Growth Rate vs Germanium concentration

0

2

4

6

8

10

12

0 5 10 15 20 25 30 35 40

Rate @ 495°Rate @ 525°Rate @ 570°

Gro

wth

Rat

e (n

m/m

inut

e)

Ge concentration (%)

570°C

525°C

495°C

Growth Rates vs Temperature

0.1

10

1.1 1.15 1.2 1.25 1.3 1.35

Ea = 1.6 ± 0.1 eV495°C

600°C

Reactant Limited

Si0.7 Ge 0.3

Si

Gro

wth

rate

(nm

/min

ute)

1

1000/T (k-1)

SiGe/Si Multilayer structure

SiGe

siliconAbrupt Si/SiGe interfaces and precise controlof Ge % for “PIN Photodetector”

SiGe Multi Quantum Wells (MQW)

SIMS

02468

101214161820

0 1000 2000 3000 4000 5000Depth (angstroms)

Con

cent

ratio

n (G

e%

)

1E+00

1E+01

1E+02

1E+03

1E+04

1E+05

1E+06

1E+07

30Si->

70Ge

a5321d_lin.SWFSample A

12/04/2003

Cs Cascade Scientific

SIMS

Cou

nts

Per S

econ

d

XRDA532-1

-110

010

110

210

310

410

-3000 -2000 -1000 0 1000 2000 3000

Inte

nsity (

cp

s)

th\2th (sec)

Reference (Active) Comparison

• Double crystal X-ray data

• Period of super-lattice = 39.5nm

• Mean Ge fraction of structure (Si spacers + SiGe Wells) = 0.6%

Measured by

SiGe Multi Quantum Wells (MQW)

Raman Scattering

Raman Scattering

Fourier transform low temperature photoluminescence apparatus.

Cryostat SAMPLE

MovingMirror

Beam-splitter

GermaniumDetector

Excitation Source

FourierSpectrometer

Laser

900 1000 1100

Pho

tolu

min

esce

nce

Inte

nsity

VerticalProfile SiGe

50 nm

PatternedWafer

SiGeLayer

Si SurroundSiGe

Etched Off

Energy - meV

PL spectra from SiGe HBT transistors

1015 1016 1017 10181E-3

0.01

0.1

1SiGe PL Threshold &

Saturation Effects

Sample BAs Grown

Sample BAnnealed

Sample AAs Grown

SiG

e P

L P

eak

Hei

ght

Incident Photon Flux / s-1cm-2

980 1000 1020 1040 10601

10

100

Si

NP

TA

TO

PL In

tens

ity

Energy / meV

PL SpectraSample B Annealed

1.4x1016 s-1cm-2

3.5x1016 s-1cm-2

SiGe - Graded Composition

15%

CarrierWavefunction

Ge Profile

20 nm

Si Si

PL of SiGe HBT

Photoluminescence Mapping ofComposition and Bandgap on a 6" wafer

Sample point "NP" energy(meV)

Energybandgap (meV)

Composition(% of Ge)

a 1080 1092.2 8.97

b 1082.5 1094.7 8.69

c 1085.2 1097.4 8.39

d 1083.3 1095.5 8.60

e 1082.5 1094.7 8.69

f 1084.8 1097.0 8.44

g 1083.7 1095.9 8.56

h 1079 1091.2 9.08

h

abd c

e

f

g

Auger Electron Spectroscopy Of Graded germanium concentration profiles

0

5

10

15

20

0 2000 4000 6000 8000 1 10 4

Actual profileIdeal profile

Ger

man

ium

ato

mic

con

cent

ratio

n (%

)

Sputtering time (s)

HBT profile FET profile

Trends in “novel” epitaxy in Si based materials

For graded SiGe buffersLow CoO, defect density reduction, flatness

Thin SiGe epitaxy with defect nucleation layerSOI substrates

Lower thermal budget in CMOSlow leak rate toolsnew precursors with high GR at <600C, e.g.trisilane

Selectivity, patterned wafers, SOI substrates

High mobility channelsPure Ge, III-V’s on Ge on SiGe, epitaxial metals