The German University in Cairo

Electronics Dept., Faculty of IET

Course: Microelectronics (ELCT 703)

Dr. Eman Azab Semester: 7th Electronics

Eng. Radwa Khairy Winter 2019

Sheet 6: Operational Amplifiers Compensation, Analysis and Design

Problem 1: A two-stage, Miller-compensated CMOS op amp has a RHP zero at 20GB, a dominant pole

due to the Miller compensation, a second pole at p2 and a mirror pole(due to current mirror

parasitic capacitance) at -3GB.

a) If GB is 1MHz, find the location of p2 corresponding to a 45° phase margin.

b) Assume that in part (a) that |p2| = 2GB and a nulling resistor is used to cancel p2.

What is the new phase margin assuming that GB = 1MHz?

c) Using the conditions of (b), what is the phase margin if CL is increased by a factor of

4?

Given: 𝒘𝒛 = 𝟐𝟎𝑮𝑩 ; 𝒘𝒑𝟏 ; 𝒘𝒑𝟐 ; 𝒘𝒑𝒎 = −𝟑𝑮𝑩

Solution:

a)

𝐴𝑣(𝑠) =𝐴𝑣𝑜 (1 −

𝑠𝒘𝒛

)

(1 +𝑠

𝒘𝒑𝟏) (1 +

𝑠𝒘𝒑𝟐

) (1 +𝑠

𝒘𝒑𝒎)

∵ 𝜑𝑚 = 180𝑜 + 𝑝ℎ𝑎𝑠𝑒(𝐴𝑣(𝐺𝐵))

𝜑𝑚 = 180𝑜 − tan−1 (𝐺𝐵

𝒘𝒛

) − tan−1 (𝐺𝐵

𝒘𝒑𝟏

) − tan−1 (𝐺𝐵

𝒘𝒑𝟐

) − tan−1 (𝐺𝐵

𝒘𝒑𝒎

)

𝜑𝑚 = 180𝑜 − tan−1 (𝐺𝐵

𝟐𝟎𝑮𝑩) − tan−1(𝐴𝑣𝑜) − tan−1 (

𝐺𝐵

𝒘𝒑𝟐

) − tan−1 (𝐺𝐵

𝟑𝑮𝑩)

∴ 𝜑𝑚 = 180𝑜 − 2.862𝑜 − 90𝑜 − tan−1 (𝐺𝐵

𝒘𝒑𝟏

) − 18.435𝑜

∵ 𝜑𝑚 = 45𝑜

2

∴ tan−1 (𝐺𝐵

𝒘𝒑𝟐

) = 23.703𝑜

∴𝐺𝐵

𝒘𝒑𝟐

= 0.439

∴ 𝒘𝒑𝟐 = 2.278𝐺𝐵

∴ 𝒘𝒑𝟐 =1 × 106 × 2 × 𝜋

0.439= 14.312 𝑀𝑟𝑎𝑑/𝑠𝑒𝑐

b) Nulling resistor is used to cancel P2

∴ 𝐴𝑣(𝑠) =𝐴𝑣𝑜

(1 +𝑠

𝒘𝒑𝟏) (1 +

𝑠𝒘𝒑𝒎

)

𝜑𝑚 = 180𝑜 − tan−1 (𝐺𝐵

𝒘𝒑𝟏

) − tan−1 (𝐺𝐵

𝒘𝒑𝒎

)

𝜑𝑚 = 180𝑜 − tan−1(𝐴𝑣𝑜) − tan−1 (𝐺𝐵

𝟑𝑮𝑩)

𝜑𝑚 = 71.565𝑜

c) If we increased load capacitor by factor 4

∵ 𝒘𝒑𝟐 =𝑔𝑚6

𝐶𝐿

This means that 𝒘𝒑𝟐 will be decreased by factor 4

∴ 𝒘𝒑𝟐 =2𝐺𝐵

4= 0.5𝐺𝐵

3

The zero is located at P2 in part B

∴ 𝑤𝑧 = −2𝐺𝐵

∴ 𝐴𝑣(𝑠) =𝐴𝑣𝑜 (1 +

𝑠𝒘𝒛

)

(1 +𝑠

𝒘𝒑𝟏) (1 +

𝑠𝒘𝒑𝟐

) (1 +𝑠

𝒘𝒑𝒎)

𝜑𝑚 = 180𝑜 + tan−1 (𝐺𝐵

𝒘𝒛

) − tan−1 (𝐺𝐵

𝒘𝒑𝟏

) − tan−1 (𝐺𝐵

𝒘𝒑𝟐

) − tan−1 (𝐺𝐵

𝒘𝒑𝒎

)

𝜑𝑚 = 180𝑜 + tan−1 (𝐺𝐵

𝟐𝑮𝑩) − tan−1(𝐴𝑣𝑜) − tan−1 (

𝐺𝐵

𝟎. 𝟓𝑮𝑩) − tan−1 (

𝐺𝐵

𝟑𝑮𝑩)

𝜑𝑚 = 34.4𝑜

4

Problem 2:

For the two-stage op amp of Fig.1, find W1/L1, W6/L6, and Cc if GB 1 MHz, p25 GB, z

3 GB and CL 40 pF. Use the parameter values of Table1 and consider only the two-pole

model of the op amp. The bias current in M5 is 40μA and in M7 is 320μA.

Given:

GB 1 MHz;p25 GB, z 3 GB and CL 40 pF. Use the parameter values of

Table1 and consider only the two-pole model of the op amp. The bias current in

M5 is 40μA and in M7 is 320μA,𝜇𝑛𝐶𝑜𝑥 = 110𝜇𝐴/𝑉2, 𝜇𝑝𝐶𝑜𝑥 = 50𝜇𝐴/𝑉2

𝑉𝑇𝑛 = −𝑉𝑇𝑝 = 0.7𝑉, 𝜆𝑛 = 0.04 𝑉−1, 𝜆𝑝 = 0.05 𝑉−1

5

Solution:

∵ 𝒘𝒑𝟐 =𝑔𝑚6

𝐶𝐿

∴ 𝑔𝑚6 = 2 × 𝜋 × 5 × 106 × 40 × 10−12 = 1.257 𝑚𝐴/𝑉

∵ 𝑔𝑚6 = √2𝐾6𝐼𝐷6

𝐼𝐷6 = 𝐼𝐷7 = 320 𝜇𝐴

∵ 𝐾6 =𝑔𝑚6

2

2𝐼𝐷6= 2.469 𝑚𝐴/𝑉2

𝐾6 =𝜇𝑝𝐶𝑜𝑥𝑊

𝐿

(𝑊

𝐿)

6=

𝐾6

𝜇𝑝𝐶𝑜𝑥= 49.38 ≅ 50

∵ 𝑤𝑧 =𝑔𝑚6

𝐶𝐶

∴ 𝐶𝐶 =𝑔𝑚6

𝑤𝑧=

1.257𝑚

2 × 𝜋 × 3 × 1 × 106= 66.69 𝑃𝐹

∵ 𝐺𝐵 =𝑔𝑚1

𝐶𝐶

∴ 𝑔𝑚1 = 𝐺𝐵 × 𝐶𝐶 = 2 × 𝜋 × 1 × 106 × 66.69 × 10−12 = 0.419 𝑚𝐴/𝑉

∵ 𝑔𝑚1 = √2𝐾1𝐼𝐷1

𝐼𝐷1 =𝐼𝐷5

2= 20 𝜇𝐴

∵ 𝐾1 =𝑔𝑚1

2

2𝐼𝐷1= 4.389 𝑚𝐴/𝑉2

𝐾1 =𝜇𝑛𝐶𝑜𝑥𝑊

𝐿

(𝑊

𝐿)

1=

𝐾1

𝜇𝑛𝐶𝑜𝑥= 39.9 ≅ 40

6

Problem 3:

For the CMOS op amp shown, find the following quantities. Use the MOS parameters of

Table1.

1.) Slew rate (V/sec.)

2.) Positive and negative output voltage limits (all transistors remain in saturation)

3.) Positive and negative input common voltage limits (all transistors remain in

saturation)

4.) Small signal voltage gain (V/V).

5.) Unity-gain bandwidth (MHz)

6.) Power dissipation (mW). (Include the 50_A current sink)

Solution:

1.

𝑆𝑅 =𝐼𝐷5

𝐶𝑐=

50𝜇

5𝑃= 10 𝑉/𝜇𝑠𝑒𝑐

2. The maximum output voltage when M7 is still operating in saturation

mode

𝑉𝑜𝑢𝑡,𝑚𝑎𝑥 = 𝑉𝐷𝐷 − 𝑉𝑆𝐷7,𝑠𝑎𝑡 = 𝑉𝐷𝐷 − √2𝐼𝐷7

𝐾7

7

𝑉𝑜𝑢𝑡,𝑚𝑎𝑥 = 2.5 − √2 × 250𝜇

50𝜇 × 50= 2.0527 𝑉

The minimum output voltage when M6 is still operating in saturation mode

𝑉𝑜𝑢𝑡,𝑚𝑖𝑛 = 𝑉𝑆𝑆 + 𝑉𝐷𝑆6,𝑠𝑎𝑡 = 𝑉𝑆𝑆 + √2𝐼𝐷6

𝐾6

𝑉𝑜𝑢𝑡,𝑚𝑖𝑛 = −2.5 + √2 × 250𝜇

110𝜇 × 50= −2.198 𝑉

3. The maximum input voltage when M5 is still operating in saturation mode

𝑉𝑖𝑛,𝑚𝑎𝑥 = 𝑉𝐷𝐷 − 𝑉𝑆𝐺1,𝑠𝑎𝑡 − 𝑉𝑆𝐷5,𝑠𝑎𝑡 = 𝑉𝐷𝐷 − √2𝐼𝐷1

𝐾1− |𝑉𝑇𝑝1| − √

2𝐼𝐷5

𝐾5

𝑉𝑖𝑛,𝑚𝑎𝑥 = 2.5 − √2 × 25𝜇

50𝜇 × 10− 0.7 − √

2 × 50𝜇

50𝜇 × 10= 1.0366 𝑉

The minimum input voltage when M1 is still operating in saturation mode

𝑉𝑖𝑛,𝑚𝑖𝑛 = 𝑉𝑆𝑆 + 𝑉𝐺𝑆3,𝑠𝑎𝑡 − |𝑉𝑇𝑝1| = 𝑉𝑆𝑆 + √2𝐼𝐷3

𝐾3− |𝑉𝑇𝑝1| + 𝑉𝑇𝑛3

𝑉𝑖𝑛,𝑚𝑖𝑛 = −2.5 + √2 × 25𝜇

110𝜇 × 10= −2.287 𝑉

8

4.

𝐴𝑣𝑜 = 𝑔𝑚1𝑅𝑜𝑢𝑡1 × 𝑔𝑚6𝑅𝑜𝑢𝑡2

𝑅𝑜𝑢𝑡1 = 𝑟𝑑𝑠2// 𝑟𝑑𝑠4 =1

(𝜆𝑛 + 𝜆𝑝)𝐼𝐷2

= 0.444 𝑀Ω

𝑅𝑜𝑢𝑡2 = 𝑟𝑑𝑠6// 𝑟𝑑𝑠7 =1

(𝜆𝑛 + 𝜆𝑝)𝐼𝐷7

= 44.4 𝐾Ω

∴ 𝑔𝑚1 = √2 × 25𝜇 × 10 × 50𝜇 = 0.158 𝑚𝐴/𝑉

∴ 𝑔𝑚6 = √2 × 250𝜇 × 50 × 110𝜇 = 1.658 𝑚𝐴/𝑉

∴ 𝐴𝑣𝑜 = 0.158𝑚 × 0.444𝑀 × 1.658𝑚 × 44.4𝐾 = 5164.25

5.

𝐺𝐵 =𝑔𝑚1

𝐶𝑐=

0.158𝑚

5𝑃×

1

2𝜋= 5.03 𝑀𝐻𝑧

6.

𝑝𝑑𝑖𝑠𝑠 = 2𝑉𝐷𝐷(𝐼𝐷8 + 𝐼𝐷5 + 𝐼𝐷7) = 1.75𝑚𝑊

9

Problem 4: A two-stage, BiCMOS op amp is shown. For the PMOS transistors, the model Parameters are

KP’=50_A/V2, VTP = -0.7V and _P = 0.05V-1. For the NPN BJTs, the model parameters are

βF = 100, VCE(sat) = 0.2V, VA = 25V, Vt = 26mV, Is = 10fA and η=1.

a) Identify which input is positive and which input is negative.

b) Find the numerical values of differential voltage gain, Av(0), GB (in Hertz), the slew

rate, SR, and the location of the RHP zero.

c) Find the numerical value of the maximum and minimum input common mode

voltages.

Given: KP’=50_A/V2, VTP = -0.7V and _P = 0.05V-1;For the NPN BJTs, the model

parameters are𝛽𝐹 = 100, VCE(sat) = 0.2V, VA = 25V, Vt = 26mV,Is = 10fA and

η=1.

Solution:

1. Since the gain of the input stage is inverting for V2 and non- inverting

for V1 and the gain of the second stage is inverting therefore V2 is the

positive(non-inverting) terminal; while V1 is the negative

(inverting)terminal

2.

𝐴𝑣𝑜 = 𝐴𝑣1 × 𝐴𝑣2

10

𝐴𝑣1 = −𝑔𝑚1𝑅𝑜𝑢𝑡1

∴ 𝑔𝑚1 = √2 × 25𝜇 × 10 × 50𝜇 = 0.158 𝑚𝐴/𝑉

𝑅𝑜𝑢𝑡1 = 𝑟𝑑𝑠2// 𝑟𝑜4 = 0.8𝑀Ω//1𝑀Ω = 0.44𝑀Ω

𝐴𝑣2 = −𝑔𝑚6𝑅𝑜𝑢𝑡2

𝑅𝑜𝑢𝑡2 = 𝑟𝑑𝑠7// 𝑟𝑜6 = 0.2𝑀Ω//0.25𝑀Ω = 0.111𝑀Ω

∴ 𝑔𝑚6 =𝐼𝐶6

𝑉𝑇=

100𝜇

26𝑚= 3.846 𝑚𝐴/𝑉

∴ 𝐴𝑣𝑜 = 0.158𝑚 × 0.44𝑀 × 3.846𝑚 × 0.111𝑀 = 29678.5

𝐺𝐵 =𝑔𝑚1

𝐶𝑐=

0.158𝑚

5𝑃×

1

2𝜋= 5.03 𝑀𝐻𝑧

𝑆𝑅 =𝐼𝐷5

𝐶𝑐=

50𝜇

5𝑃= 10 𝑉/𝜇𝑠𝑒𝑐

∵ 𝑤𝑧 =𝑔𝑚6

𝐶𝐶= 769.2 𝑀𝑟𝑎𝑑/𝑠𝑒𝑐

3.

The maximum input voltage when M5 is still operating in saturation

mode

𝑉𝑖𝑛,𝑚𝑎𝑥 = 𝑉𝐷𝐷 − 𝑉𝑆𝐺1 − 𝑉𝑆𝐷5,𝑠𝑎𝑡

𝑉𝑖𝑛,𝑚𝑎𝑥 = 𝑉𝐷𝐷 − √2𝐼𝐷1

𝐾1− |𝑉𝑇𝑝1| − √

2𝐼𝐷5

𝐾5

𝑉𝑖𝑛,𝑚𝑎𝑥 = 1.5 − √2 × 25𝜇

50𝜇 × 10− 0.7 − √

2 × 50𝜇

50𝜇 × 10= 0.0366 𝑉

11

The minimum input voltage when M1 is still operating in saturation

mode

𝑉𝑖𝑛,𝑚𝑖𝑛 = 𝑉𝑆𝑆 + 𝑉𝐵𝐸3 − |𝑉𝑇𝑝1|

𝑉𝑖𝑛,𝑚𝑖𝑛 = 𝑉𝑆𝑆 + 𝑉𝑇𝑙𝑛 (𝐼𝐶3

𝐼𝑜𝑠) − |𝑉𝑇𝑝1|

𝑉𝑖𝑛,𝑚𝑖𝑛 = −1.5 + (0.026 × 𝑙𝑛 (25𝜇

10𝑓)) − 0.7 = −1.637 𝑉

12

Problem 5: The figure below shows the internal circuit of the 741-opamp. Q11, Q12, and R5 generate a

reference bias current, IREF. Q10, Q9, and Q8 bias the input stage, which is composed of Q1 to

Q7. The second gain stage is composed of Q16 and Q17 with Q13B acting as active load. The

class AB output stage is formed by Q14 and Q20 with biasing devices Q13A, Q18, and Q19, and

an input buffer Q23. Transistors Q15, Q21, Q24, and Q22 serve to protect the amplifier against

output short circuits and are normally cut off.

Given: 𝛽 = 250, the reverse saturation current Io =10-14mA for all transistors except

Q14 and Q20 (Io14(or 20)) =3*10-14mA.

Required: (1) All the DC collector currents.

(2) Explain the operation of the SC protection circuit.

(3) Find the input resistance, output resistance and the voltage gain of the input and

second stages assuming the loading effect is neglected and the output stage is ideal

buffer. Assuming VAn =100 V and VAp=50V

(4) Draw the complete small signal model of the op-amp and find the overall gain.

(5) Find the high frequency gain of this op-amp assuming CC is the dominant

capacitance in the circuit.

(6) Find GB and SR of the 741-op-amp.

13

Solution:

1. All DC collector currents

a. For the input stage

The current source Q11 and Q10

𝐼𝑟𝑒𝑓 =2𝑉𝐶𝐶 − 𝑉𝐵𝐸11 − 𝑉𝐸𝐵12

𝑅5=

30 − 1.4

39𝐾= 0.73 𝑚𝐴

14

Neglecting all base currents

𝐼𝑟𝑒𝑓 = 𝐼𝐶11 = 𝐼𝐶12

Q11 and Q10 form a current mirror called Widlar current mirror; so they are

matched and operating in the active region

𝑉𝐵𝐸11 = 𝑉𝐵𝐸10 + 𝐼𝐶10𝑅4

𝑉𝐵𝐸11 − 𝑉𝐵𝐸10 = 𝐼𝐶10𝑅4

𝑉𝑇𝑙𝑛 (𝐼𝐶11

𝐼𝐶10) = 𝐼𝐶10𝑅4

Using trial and error we will calculate the

Collector current of Q10

𝐼𝐶10 = 18.4𝜇𝐴

Q10 and Q9 are connected in series and we

will neglect the base current of Q3 and Q4

𝐼𝐶10 = 𝐼𝐶9 = 18.4 𝜇𝐴

Q8 and Q9 are a current mirror and we will neglect their bases currents

∴ 𝐼𝐶8 = 𝐼𝐶9 = 18.4 𝜇𝐴

For the differential amplifier Q1 and Q2 we work at the optimum DC

operating point 𝑉𝐼𝐷 = 0𝑉

𝐼𝐶1 = 𝐼𝐶2 =𝐼𝐶8

2= 9.2 𝜇𝐴

Since all transistors have very large 𝛽 so we can assume that

𝐼𝐶 ≅ 𝐼𝐸

𝐼𝐸1 ≅ 𝐼𝐶1 = 𝐼𝐸3 ≅ 𝐼𝐶3

15

𝐼𝐶3 = 𝐼𝐶4 = 9.2 𝜇𝐴

Q5 and Q3 are in series ; Q4 and Q6 are in series neglecting the base currents

(note that Q5 and Q6 act as a current mirror)

𝐼𝐶5 = 𝐼𝐶6 = 9.2 𝜇𝐴

For Q7 we will find it’s emitter current

𝐼𝐸7 = 𝐼𝐵5 + 𝐼𝐵6 + 𝐼𝑅3

𝐼𝐸7 =𝐼𝐶5

𝛽+

𝐼𝐶6

𝛽+ 𝐼𝑅3

𝐼𝑅3 =𝑉𝐵𝐸6 + 𝐼𝐶6𝑅2

𝑅3=

𝑉𝑇𝑙𝑛 (𝐼𝐶6

𝐼𝑂𝑆) + 𝐼𝐶6𝑅2

𝑅3

𝐼𝑅3 =25𝑚 × 𝑙𝑛 (

9.2𝜇10−14) + 9.2𝜇 × 1𝐾

50𝐾= 10.5 𝜇𝐴

𝐼𝐸7 =9.2𝜇

250+

9.2𝜇

250+ 10.5 𝜇 = 10.58 𝜇𝐴

For the gain stage

Q13 is equivalent to two transistors

Each one has a part of its total collector

current

Io13B=0.75 Io

Io13A=0.25 Io

16

Q12 and Q13 form a current mirror so they have the same collector currents

∵ 𝐼𝐶,13𝐵 = 0.75𝐼𝐶12 = 547.5 𝜇𝐴

𝐼𝐶17 = 𝐼𝐶,13𝐵 = 547.5 𝜇𝐴

For Q16:

𝐼𝐸16 = 𝐼𝐵17 + 𝐼𝑅9

𝐼𝐸16 =𝐼𝐶17

𝛽+ 𝐼𝑅9

𝐼𝑅9 =𝑉𝐵𝐸17 + 𝐼𝐶17𝑅8

𝑅9=

𝑉𝑇𝑙𝑛 (𝐼𝐶17

𝐼𝑂𝑆) + 𝐼𝐶17𝑅8

𝑅9= 13.46 𝜇𝐴

∴ 𝐼𝐸16 ≅ 𝐼𝐶16 = 15.65 𝜇𝐴

For the output stage:

17

Q15, Q21, Q24, Q22 are normally off as they are turned on only when the

output node is short circuit.

Ignore the base currents for Q14 and Q20

∵ 𝐼𝐶,13𝐴 = 0.25𝐼𝐶12 = 182.5 𝜇𝐴

𝐼𝐶23 = 𝐼𝐶,13𝐴 = 182.5 𝜇𝐴

𝐼𝐶23 = 𝐼𝑅10 + 𝐼𝐸18

Assume that 𝑉𝐵𝐸18 = 0.6 𝑉

𝐼𝑅10 =𝑉𝐵𝐸18

𝑅10= 15𝜇𝐴

∴ 𝐼𝐸18 = 𝐼𝐶23 − 𝐼𝑅10 = 167.5 𝜇𝐴

∴ 𝐼𝐶19 ≅ 𝐼𝐶13,𝐴 − 𝐼𝐸18 = 15𝜇𝐴

As for Q14 and Q20 (class AB push-pull)

Assume that 𝑉𝐵𝐸14 = 𝑉𝐸𝐵20

2𝑉𝐵𝐸14 = 𝑉𝐵𝐸18 + 𝑉𝐵𝐸19

𝑉𝐵𝐸14 = 0.559𝑉

𝐼𝐶14 = 𝐼𝐶20 = 𝐼𝑂𝑆14𝑒𝑥𝑝 (𝑉𝐵𝐸14

𝑉𝑇) = 154.15 𝜇𝐴

2. If the output node is grounded and 𝑉𝑖 keeps increasing and with it the

base and collector currents of Q14 increases as well; thus the power

dissipated in Q14 increases so that it may damage or destroy the

transistor;

By connecting R6 and Q15 as the collector current of Q14 increases

the voltage drop across R6 increase till it turns on Q15 and thus part of

the base current of Q14 will flow through Q15 and the power

dissipation decreases;

18

Note that during the negative clock cycle R7 and Q23 will protect Q20

from damage by the same way.

3. AC analysis for the op-amp:

The input stage:

𝑅𝑖𝑛1 = 𝑟𝜋1 +𝑟𝜋3(1 + 𝛽1)

(1 + 𝛽3)+ 𝑟𝜋4 +

𝑟𝜋2(1 + 𝛽4)

(1 + 𝛽2)

19

Since Q1, Q2, Q3, Q4 have same 𝛽 & 𝐼𝐶 then they have same 𝑟𝜋

𝑅𝑖𝑛1 = 4𝑟𝜋1 = 2.72 𝑀Ω

𝑅𝑜𝑢𝑡1 = [𝑟𝑜4 + (1 + 𝑔𝑚4𝑟𝑜4)𝑟𝜋2

1 + 𝛽] //[𝑟𝑜6 + (1 + 𝑔𝑚6𝑟𝑜6)𝑅2]

∴ 𝑅𝑜𝑢𝑡1 = 6.26 𝑀Ω

𝑣𝑜𝑢𝑡1 = −2𝛽𝑖𝑏1𝑅𝑜𝑢𝑡1

∵ 𝑖𝑏1 =𝑣𝑖𝑛

𝑅𝑖𝑛1

∴𝑣𝑜𝑢𝑡1

𝑣𝑖𝑛=

−2𝛽𝑅𝑜𝑢𝑡1

4𝑟𝜋1=

−𝑔𝑚1𝑅𝑜𝑢𝑡1

2= −1151.84

Let

𝑔𝑚1𝑒𝑞 =𝑔𝑚1

2= 0.193 𝑚𝐴/𝑉

∴ 𝐴𝑣1 =𝑣𝑜𝑢𝑡1

𝑣𝑖𝑛= −𝑔𝑚1𝑒𝑞𝑅𝑜𝑢𝑡1

For the second stage:

20

𝑣𝑜𝑢𝑡2 = (1 + 𝛽)𝑖𝑏16𝑅9

𝑖𝑏16 =𝑣𝑜𝑢𝑡1

𝑟𝜋16 + (1 + 𝛽)𝑅9

∴𝑣𝑜𝑢𝑡2

𝑣𝑜𝑢𝑡1=

(1 + 𝛽)𝑅9

𝑟𝜋16 + (1 + 𝛽)𝑅9

∵ 𝑣𝑜𝑢𝑡 = −𝛽𝑖𝑏17𝑅𝑜𝑢𝑡2

𝑖𝑏17 =𝑣𝑜𝑢𝑡2

𝑟𝜋17 + (1 + 𝛽)𝑅8

∴𝑣𝑜𝑢𝑡

𝑣𝑜𝑢𝑡2=

−𝛽𝑅𝑜𝑢𝑡2

𝑟𝜋17 + (1 + 𝛽)𝑅8

∴𝑣𝑜𝑢𝑡

𝑣𝑜𝑢𝑡1=

𝑣𝑜𝑢𝑡2

𝑣𝑜𝑢𝑡1×

𝑣𝑜𝑢𝑡

𝑣𝑜𝑢𝑡2

∴ 𝐴𝑣2 =𝑣𝑜𝑢𝑡2

𝑣𝑜𝑢𝑡1=

−𝛽𝑅𝑜𝑢𝑡2

𝑟𝜋17 + (1 + 𝛽)𝑅8×

(1 + 𝛽)𝑅9

𝑟𝜋16 + (1 + 𝛽)𝑅9

Let

𝑔𝑚2𝑒𝑞 =𝛽

𝑟𝜋17 + (1 + 𝛽)𝑅8×

(1 + 𝛽)𝑅9

𝑟𝜋16 + (1 + 𝛽)𝑅9= 6.6 𝑚𝐴/𝑉

𝑅𝑜𝑢𝑡2 = 𝑟𝑜13𝐵//[𝑟𝑜17 + (1 + 𝑔𝑚17𝑟𝑜17)𝑅8] = 78.95𝐾Ω

∴ 𝐴𝑣2 =𝑣𝑜𝑢𝑡2

𝑣𝑜𝑢𝑡1= −𝑔𝑚2𝑒𝑞𝑅𝑜𝑢𝑡2 = −524.52

𝑅𝑖𝑛2 = 𝑟𝜋16 + (1 + 𝛽)(𝑅9//(𝑟𝜋17 + (1 + 𝛽)𝑅8)) = 5.695 𝑀Ω

21

4.

The overall gain:

𝑣𝑜𝑢𝑡1 = −𝑔𝑚1𝑒𝑞(𝑅𝑜𝑢𝑡1//𝑅𝑖𝑛2)𝑣𝑖𝑛

𝑣𝑜𝑢𝑡 = −𝑔𝑚2𝑒𝑞𝑅𝑜𝑢𝑡2𝑣𝑜𝑢𝑡1

∴𝑣𝑜𝑢𝑡

𝑣𝑖𝑛= 𝑔𝑚1𝑒𝑞𝑔𝑚2𝑒𝑞(𝑅𝑜𝑢𝑡1//𝑅𝑖𝑛2)𝑅𝑜𝑢𝑡2 = 285713.1

∴𝑣𝑜𝑢𝑡

𝑣𝑖𝑛 𝑑𝐵

= 20𝑙𝑜𝑔 (𝑣𝑜𝑢𝑡

𝑣𝑖𝑛) = 109.12 𝑑𝐵

5.

From the lectures we have

𝐴𝑣(𝑆) ≅𝐴𝑣𝑜

(1 +𝑆

𝑤1)

𝑤1 =1

𝐶𝐶𝑔𝑚2𝑒𝑞(𝑅𝑜𝑢𝑡1//𝑅𝑖𝑛2)𝑅𝑜𝑢𝑡2= 21.467 𝑟𝑎𝑑/𝑠𝑒𝑐

ineqm vg 1inv 1outv1inR 1outR

+

-

2inR 12 outeqm vg 2outR outv

ineqm vg 1inv 1outv1inR 1outR

+

-

2inR 12 outeqm vg 2outR outv

CC

22

OR using Miller theorem:

𝐶1 = 𝐶𝐶(1 − 𝐴)

𝐶2 = 𝐶𝐶(1 − 𝐴−1)

∵ 𝐴 =𝑣𝑜𝑢𝑡

𝑣𝑜𝑢𝑡1=

−𝑔𝑚2𝑒𝑞𝑅𝑜𝑢𝑡2𝑣𝑜𝑢𝑡1

𝑣𝑜𝑢𝑡1

∴ 𝐴 = −𝑔𝑚2𝑒𝑞𝑅𝑜𝑢𝑡2 = −521.07

∴ 𝐶1 = 15.67 𝑛𝐹

∴ 𝐶2 = 30.06 𝑃𝐹

∴ 𝐴𝐻𝐹 =𝑣𝑜𝑢𝑡

𝑣𝑖𝑛= 𝑔𝑚1𝑒𝑞𝑔𝑚2𝑒𝑞 (𝑅𝑜𝑢𝑡1//𝑅𝑖𝑛2//

1

𝑆𝐶1) (𝑅𝑜𝑢𝑡2//

1

𝑆𝐶2)

∴ 𝐴𝐻𝐹 =𝐴𝑀𝐹

(1 +𝑆

𝑤1) (1 +

𝑆𝑤2

)

Where

𝑤1 =1

𝐶1(𝑅𝑜𝑢𝑡1//𝑅𝑖𝑛2)= 21.27 𝑟𝑎𝑑/𝑠𝑒𝑐

𝑤2 =1

𝐶2𝑅𝑜𝑢𝑡2= 4.21 × 1023 𝑟𝑎𝑑/𝑠𝑒𝑐

It is clear that 𝑤1 is the dominant pole

6.

𝐺𝐵 = 𝐴𝑣𝑜𝑓1 = 285713.1 ×21.467

2𝜋≅ 1 𝑀𝐻𝑧

𝑆𝑅 =𝐼𝐶8

𝐶𝐶= 0.613 𝑉/𝜇𝑠𝑒𝑐