Operational Amplifiers-blocks

7/13/2019 Operational Amplifiers-blocks

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Operational Amplifiers:

The operational amplifier is a direct-coupled high gain amplifier usable from 0 to over 1MH Z to

which feedback is added to control its overall response characteristic i.e. gain and bandwidth.

The op-amp exhibits the gain down to ero fre!uenc".

#uch direct coupled $dc% amplifiers do not use blocking $coupling and b" pass% capacitors since

these would reduce the amplification to ero at ero fre!uenc". &arge b" pass capacitors ma" be

used but it is not possible to fabricate large capacitors on a '( chip. The capacitors fabricated are

usuall" less than )0 pf. Transistor* diodes and resistors are also fabricated on the same chip.

Differential Amplifiers:

+ifferential amplifier is a basic building block of an op-amp. The function of a differential

amplifier is to amplif" the difference between two input signals.

How the differential amplifier is developed, &et us consider two emitter-biased circuits as shown

infig. 1.

Fig. 1

The two transistors 1and )have identical characteristics. The resistances of the circuits are

e!ual* i.e. /1 /)* (1 ()and the magnitude of 2((is e!ual to the magnitude of 32//.These voltages are measured with respect to ground.

To make a differential amplifier* the two circuits are connected as shown in fig. 1. The two2((and 32//suppl" terminals are made common because the" are same. The two emitters are

also connected and the parallel combination of /1and /)is replaced b" a resistance /. The

two input signals v14 v)are applied at the base of 1and at the base of ). The output voltage is
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taken between two collectors. The collector resistances are e!ual and therefore denoted b" (

(1 ().

'deall"* the output voltage is ero when the two inputs are e!ual. 5hen v 1is greater then v)theoutput voltage with the polarit" shown appears. 5hen v1is less than v)* the output voltage has

the opposite polarit".

The differential amplifiers are of different configurations.

The four differential amplifier configurations are following6

1. +ual input* balanced output differential amplifier.

). +ual input* unbalanced output differential amplifier.

7. #ingle input balanced output differential amplifier.

8. #ingle input unbalanced output differential amplifier.


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These configurations are shown in fig. 2* and are defined b" number of input signals used andthe wa" an output voltage is measured. 'f use two input signals* the configuration is said to bedual input* otherwise it is a single input configuration. 9n the other hand* if the output voltage is

measured between two collectors* it is referred to as a balanced output because both the

collectors are at the same dc potential w.r.t. ground. 'f the output is measured at one of thecollectors w.r.t. ground* the configuration is called an unbalanced output.

: multistage amplifier with a desired gain can be obtained using direct connection between

successive stages of differential amplifiers. The advantage of direct coupling is that it removes

the lower cut off fre!uenc" imposed b" the coupling capacitors* and the" are therefore* capableof amplif"ing dc as well as ac input signals.

Dual Input, Balanced Output Difference Amplifier:

The circuit is shown infig. 1v1and v)are the two inputs* applied to the bases of 1and

)transistors. The output voltage is measured between the two collectors (1and ()* which are at

same dc potentials.
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Fig. 1

A.C. Analysis :

'n previous lecture dc anal"sis has been done to obtain the operatiing point of the two

transistors.To find the voltage gain :dand the input resistance iof the differential amplifier* the

ac e!uivalent circuit is drawn using r-parameters as shown in fig. 2. The dc voltages are reduced

to ero and the ac e!uivalent of (/ configuration is used.

Fig. 2
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#ince the two dc emitter currents are e!ual. Therefore* resistance r; e1and r;e)are also e!ual and

designated b" r;e. This voltage across each collector resistance is shown 1


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($ie1- ie)%

#ubstituting ie1* 4 ie)in the above expression

Thus a differential amplifier amplifies the difference between two input signals. +efining the

difference of input signals as vd v13 v)the voltage gain of the dual input balanced output

differential amplifier can be given b"

$/-)%

: dual input* balanced output difference amplifier circuit is shown infig. 1.

Fig. 1

Inverting !on " inverting Inputs:

'n differential amplifier the output voltage v9is given b"
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29:d$v13v)%

5hen v)0*v9:dv1

4 when v1 0* v9 - :dv)

Therefore the input voltage v1 is called the non inventing input because a positive voltage

v1acting alone produces a positive output voltage v9. #imilarl"* the positive voltage v)acting

alone produces a negative output voltage hence v)is called inverting input. (onse!uentl" B1is

called noninverting input terminal and B)is called inverting input terminal.

Common mode #ain:

: common mode signal is one that drives both inputs of a differential amplifier e!uall". The

common mode signal is interference* static and other kinds of undesirable pickup etc.

The connecting wires on the input bases act like small antennas. 'f a differential amplifier is

operating in an environment with lot of electromagnetic interference* each base picks up an

unwanted interference voltage. 'f both the transistors were matched in all respects then the

balanced output would be theoreticall" ero. This is the important characteristic of a differential

amplifier. 't discriminates against common mode input signals. 'n other words* it refuses to

amplif" the common mode signals.

The practical effectiveness of reCecting the common signal depends on the degree of matching

between the two (/ stages forming the differential amplifier. 'n other words* more closel" are

the currents in the input transistors* the better is the common mode signal reCection e.g. 'f v 1and

v)are the two input signals* then the output of a practical op-amp cannot be described b" simpl"

v0 :d$v13 v)%

'n practical differential amplifier* the output depends not onl" on difference signal but also upon

the common mode signal $average%.

vd $v13 vd%

and v( D $v1 v)%

The output voltage* therefore can be expressed as

v9 :1v1 :)v)

5here :14 :)are the voltage amplification from input 1$)% to output under the condition that

input ) $1% is grounded.


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The voltage gain for the difference signal is :dand for the common mode signal is :(.

The abilit" of a differential amplifier to reCect a common mode signal is expressed b" its

common mode reCection ratio $(M%. 't is the ratio of differential gain :dto the common mode

gain :(.

+ate sheet alwa"s specif" (M in decibels (M )0 log (M.

Therefore* the differential amplifier should be designed so that is large compared with the ratio

of the common mode signal to the difference signal. If = 1000, vC= 1mV, vd= 1 V, then

't is e!ual to first term. Hence for an amplifier with 1000* a 1 12 difference of potential

between two inputs gives the same output as 1m2 signal applied with the same polarit" to both

inputs.

Constant Current Bias:

'n the dc anal"sis of differential amplifier* we have seen that the emitter current ' /depends upon

the value ofdc. To make operating point stable '/current should be constant irrespective value

ofdc.

>or constant '/* /should be ver" large. This also increases the value of (M but if /value is

increased to ver" large value* '/$!uiescent operating current% decreases. To maintain same value

of '/* the emitter suppl" 2//must be increased. To get ver" high value of resistance /andconstant '/* current* current bias is used.


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Figure $.1

Fig. 1*shows the dual input balanced output differential amplifier using a constant current bias.

The resistance /is replace b" constant current transistor 7. The dc collector current in 7is

established b" 1* )* 4 /.

:ppl"ing the voltage divider rule* the voltage at the base of 7is

Because the two halves of the differential amplifiers are s"mmetrical* each has half of the current'(7.


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The collector current* '(7in transistor 7is fixed because no signal is inCected into either the

emitter or the base of 7.

Besides suppl"ing constant emitter current* the constant current bias also provides a ver" highsource resistance since the ac e!uivalent or the dc source is ideall" an open circuit. Therefore* all

the performance e!uations obtained for differential amplifier using emitter bias are also valid.

:s seen in '/expressions* the current depends upon 2B/7. 'f temperature changes* 2B/changes

and current '/also changes. To improve thermal stabilit"* a diode is placed in series withresistance 1as shown infig. 2.

Fig. 2

This helps to hold the current '/7constant even though the temperature changes. :ppl"ing ?2&to the base circuit of 7.

Therefore* the current '/7is constant and independent of temperature because of the added diode+. 5ithout + the current would var" with temperature because 2B/7decreases approximatel" b"

)m2@= (. The diode has same temperature dependence and hence the two variations cancel each


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other and '/7does not var" appreciabl" with temperature. #ince the cut 3 in voltage 2+of diode

approximatel" the same value as the base to emitter voltage 2B/7of a transistor the above

condition cannot be satisfied with one diode. Hence two diodes are used in series for 2 +. 'n thiscase the common mode gain reduces to ero.

%&e operation amplifier:

:n operational amplifier is a direct coupled high gain amplifier consisting of one or more

differential $9E:ME% amplifiers and followed b" a level translator and an output stage. :noperational amplifier is available as a single integrated circuit package.

The block diagram of 9E:ME is shown in fig. 1.

Fig. 1

The input stage is a dual input balanced output differential amplifier. This stage provides most of

the voltage gain of the amplifier and also establishes the input resistance of the 9E:ME.The

intermediate stage of 9E:ME is another differential amplifier which is driven b" the output ofthe first stage. This is usuall" dual input unbalanced output.

Because direct coupling is used* the dc voltage level at the output of intermediate stage is wellabove ground potential. Therefore level shifting circuit is used to shift the dc level at the output

downward to ero with respect to ground. The output stage is generall" a push pullcomplementar" amplifier. The output stage increases the output voltage swing and raises the

current suppl"ing capabilit" of the 9E:ME. 't also provides low output resistance.


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Fig. '

Fig. (* shows a complete 9E:ME circuit having input different amplifiers with balanced output*

intermediate stage with unbalanced output* level shifter and an output amplifier.

)evel %ranslator:

Because of the direct coupling the dc level at the emitter

rises from stages to stage. This increase in dc level tends

to shift the operating point of the succeeding stages andtherefore limits the output voltage swing and ma" even

distort the output signal.

To shift the output dc level to ero* level translator

circuits are used. :n emitter follower with voltagedivider is the simplest form of level translator as shown

infig. 2.

Thus a dc voltage at the base of produces 02 dc at the

output. 't is decided b" 1and ). 'nstead of voltage

divider emitter follower either with diode current bias orcurrent mirror bias as shown infig. ' ma" be used to get

better results.

'n this case* level shifter* which is common collector

amplifier* shifts the level b" 0.F2. 'f this shift is not

sufficient* the output ma" be taken at the Cunction of two

resistors in the emitter leg.

Fig. 2
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Fig. (

The s"mbolic diagram of an 9E:ME is shown in fig. 1.

F81c is most commonl" used 9E:ME available in '( package. 't is an


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'nput offset voltage is defined as the

voltage that must be applied between

the two input terminals of an 9E:MEto null or ero the output fig. 2* shows

that two dc voltages are applied toinput terminals to make the output

ero.

2io 2dc13 2dc)

2dc1and 2dc)are dc voltages and

#represents the source resistance.

2iois the difference of 2dc1and 2dc). 'tma" be positive or negative. >or a

F81( 9E:ME the maximum value of

2iois Gm2. 't means a voltage G m2is re!uired to one of the input to

reduce the output offset voltage to

ero. The smaller the input offset

voltage the better the differentialamplifier* because its transistors are

more closel" matched.

Fig. 2

2. Input offset Current:

The input offset current 'iois the difference between the currents into inverting and non-invertingterminals of a balanced amplifier.

'io I 'B13 'B)I

The 'io for the F81( is )00n: maximum. :s the matching between two input terminals is

improved* the difference between 'B1and 'B)becomes smaller* i.e. the 'iovalue decreases

further.>or a precision 9E:ME F81(* 'iois G n:

'.Input Bias Current:

The input bias current 'Bis the average of the current entering the input terminals of a balancedamplifier i.e.

'B $'B1 'B)% @ )

>or F81( 'B$max% F00 n: and for precision F81( 'B F n:

(. Differential Input -esistance: -i/


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iis the e!uivalent resistance that can be measured at either the inverting or non-inverting input

terminal with the other terminal grounded. >or the F81( the input resistance is relativel" high )

MJ. >or some 9E:ME it ma" be up to 1000 K ohm.

$. Input Capacitance: Ci/

(iis the e!uivalent capacitance that can be measured at either the inverting and noninverting

terminal with the other terminal connected to ground. : t"pical value of (iis 1.8 pf for the F81(.

0. Offset oltage Adustment -ange:

F81 9E:ME have offset voltage null capabilit". Eins 1 and L are marked offset null for thispurpose. 't can be done b" connecting 10 ? ohm pot between 1 and L as shown infig. '.

Fig. '

B" var"ing the potentiometer* output offset voltage $with inputs grounded% can be reduced to

ero volts. Thus the offset voltage adCustment range is the range through which the input offset

voltage can be adCusted b" var"ing 10 ? pot. >or the F81( the offset voltage adCustment range is 1L m2.

3ample 4 1

: 100 E> capacitor has a maximum charging current of 1L0 :. 5hat is the slew rate,

5olution:

( 100 E>100 x 10-1)>

' 1L0 : 1L0 x 10-G:


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#lew rate is 1.L 2 @ s.

3ample 4 2

:n operational amplifier has a slew rate of ) 2 @ s. 'f the peak output is 1) 2* what is the power

bandwidth,

5olution:

The slew rate of an operational amplifier is

:s for output free of distribution* the slews determines the maximum fre!uenc" of operation

fmax for a desired output swing.

so

#o bandwidth )G.L kH.

3ample 4 '

>or the given circuit in fig. 1. ' in$off% )0 n:. 'f 2in$off% 0* what is the differential input voltage,.

'f : 10L* what does the output offset voltage e!ual,


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Fig. 1

5olutin:

'in$off% )0 n:

2in$off% 0

$i% The differential input voltage 'in$off%x 1k )0 n: x 1 k )0 2

$ii% 'f : 10Lthen the output offset voltage 2in$off% )0 2 x 10L ) volt

9utput offset voltage ) volts.

Open loop O*A+* Configuration:

'n the case of amplifiers the term open loop indicates that no connection* exists between input

and output terminals of an" t"pe. That is* the output signal is not fedback in an" form as part of

the input signal.

'n open loop configuration* The 9E:ME functions as a high gain amplifier. There are three openloop 9E:ME configurations.

%&e Differential Amplifier:

Fig. 1* shows the open loop differential amplifier in which input signals vin1and vin)are applied

to the positive and negative input terminals.


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Fig. 1

#ince the 9E:ME amplifies the difference the between the two input signals* this configuration

is called the differential amplifier. The 9E:ME amplifies both ac and dc input signals. The

source resistance in1and in)are normall" negligible compared to the input resistance i.Therefore voltage drop across these resistances can be assumed to be ero.

Therefore

v1 vin1and v) vin).

vo :d$vin13 vin)%

where* :dis the open loop gain.

%&e Inverting Amplifier:

'f the input is applied to onl" inverting terminal and non-inverting terminal is grounded then it is

called inverting amplifier.This configuration is shown in fig. 2.

v1 0* v) vin.

vo -:dvin


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Fig. 2

The negative sign indicates that the output voltage is out of phase with respect to input 1


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Input -esistance 6it& Feed7ac8:

fig. 1* shows a voltage series feedback with the 9E:ME e!uivalent circuit.

Fig. 1

'n this circuit iis the input resistance $open loop% of the 9E:ME and ifis the input resistanceof the feedback amplifier. The input resistance with feedback is defined as

#ince :B is much larger than 1* which means that ifis much larger that i. Thus ifapproaches

infinit" and therefore* this amplifier approximates an ideal voltage amplifier.

Output -esistance 6it& Feed7ac8:

9utput resistance is the resistance determined looking back into the feedback amplifier from theoutput terminal. To find output resistance with feedback f* input vinis reduced to ero* an

external voltage 2ois applied as shown in fig. 2.
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Fig. 2

The output resistance $of% is defined as

This shows that the output resistance of the voltage series feedback amplifier is $ 1 @ 1:B %

times the output resistance oof the op-amp. 't is ver" small because $1:B% is ver" large. 'tapproaches to ero for an ideal voltage amplifier.

oltage s&unt Feed7ac8:

Fig. 1* shows the voltage shunt feedback amplifier using 9E:ME.


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Fig. 1

The input voltage drives the inverting terminal* and the amplified as well as inverted output

signal is also applied to the inverting input via the feedback resistor f. This arrangement forms a

negative feedback because an" increase in the output signal results in a feedback signal into the

inverting input signal causing a decrease in the output signal. The non-inverting terminal is

grounded. esistor 1is connected in series with the source.

The closed loop voltage gain can be obtained b"* writing ?irchoff;s current e!uation at the input

node 2).


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The negative sign in e!uation indicates that the input and output signals are out of phase b" 1


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Analog Inverter and 5cale C&anger:

The circuit of analog inverter is shown in fig. 1. 't is same as inverting voltage amplifier.

:ssuming 9E:ME to be an ideal one* thedifferential input voltage is ero.

i.e. vd 0Therefore* v1 v) 0

#ince input impedance is ver" high* therefore*

input current is ero. 9E:ME do not sink an"

current.

iin if

vin@ - v9 @ fvo - $f @ % vin

'f fthen v9 -vin* the circuit behaveslike an inverter.

'f f @ ? $a constant% then the circuit is

called inverting amplifier or scale changer

voltages.

Fig. 1

Inverting summer:

The configuration is shown infig. 2. 5ith three input voltages va* vb4 vc. +epending upon thevalue of fand the input resistors a* b* cthe circuit can be used as a summing amplifier*

scaling amplifier* or averaging amplifier.
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:gain* for an ideal 9E:ME* v1

v). The current drawn b" 9E:ME

is ero. Thus* appl"ing ?(& atv)node

This means that the output voltageis e!ual to the negative sum of all

the inputs times the gain of the

circuit f@ O hence the circuit is

called a summing amplifier. 5henf then the output voltage is

e!ual to the negative sum of all

inputs.

vo -$va vb vc%

Fig. 2

'f each input voltage is amplified b" a different factor in other words weighted differentl" at theoutput* the circuit is called then scaling amplifier.

The circuit can be used as an averaging circuit* in which the output voltage is e!ual to the

average of all the input voltages.

'n this case* a b c and f@ 1 @ n where n is the number of inputs. Here f@ 1 @

7.

vo -$va vb vc% @ 7

'n all these applications input could be either ac or dc.


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Differential Amplifier:

The basic differential amplifier is shown in fig. 1.

Fig. 1

#ince there are two inputs superposition theorem can be used to find the output voltage. 5hen

2b 0* then the circuit becomes inverting amplifier* hence the output due to 2aonl" is

2o$a% -$f@ 1% 2a

#imilarl" when* 2a 0* the configuration is a inverting amplifier having a voltage dividednetwork at the noninverting input


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Differentator:

: circuit in which the output voltage waveform is the differentiation of input voltage is called

differentiator.as shown infig. 1.

Fig. 1

The expression for the output voltage can be obtained from the ?irchoff;s current e!uation

written at node v).


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Thus the output vois e!ual to the ( times

the negative instantaneous rate of change

of the input voltage vinwith time. : cosinewave input produces sine output. fig.

1also shows the output waveform for

different input voltages.

The input signal will be differentiatedproperl" if the time period T of the input

signal is larger than or e!ual to f(.

Tf(

:s the fre!uenc" changes* the gain

changes. :lso at higher fre!uencies thecircuit is highl" susceptible at high

fre!uenc" noise and noise gets amplified.

Both the high fre!uenc" noise andproblem can be corrected b" additing* few

components. as shown in fig. 2.

Fig. 2

Current to voltage converter:

The circuit shown in fig. 1*is a current to voltage converter.

Fig. 1
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+ue to virtual ground the current through is ero and the input current flows through f.

Therefore*

vout-fP iin

The lower limit on current measure with this circuit is set b" the bias current of the invertinginput.

3ample "1:

>or the current to current converter shown infig. 2* prove that

Fig. 2

5olution:

The current through 1can be obtained from the current divider circuit.

#ince* the input impedance of 9E:ME is ver" large* the input current of 9E:ME is negligible.

Thus*


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Operational Amplifiers-blocks

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