Semiconductor Technology Research, Development

Semiconductor Technology Research, Development, & Manufacturing: Status, Challenges, & Solutions

Semiconductor Technology Semiconductor Technology Research, Development, & Research, Development, & Manufacturing: Status, Manufacturing: Status, Challenges, & SolutionsChallenges, & Solutions

C. R. Helms*Past President & CEO International SEMATECH

*Professor Emeritus, Stanford Univ.

C. R. Helms*C. R. Helms*Past President & CEO Past President & CEO International SEMATECHInternational SEMATECH

*Professor Emeritus, *Professor Emeritus, Stanford Univ.Stanford Univ.

Semiconductor Technology Research, Development, & Manufacturing: Status, Challenges, & Solutions

A New Paradigm in the Making?

Semiconductor Technology Semiconductor Technology Research, Development, & Research, Development, & Manufacturing: Status, Manufacturing: Status, Challenges, & SolutionsChallenges, & Solutions

A New Paradigm in the Making?A New Paradigm in the Making?

C. R. Helms*Past President & CEO International SEMATECH

*Professor Emeritus, Stanford Univ.

C. R. Helms*C. R. Helms*Past President & CEO Past President & CEO International SEMATECHInternational SEMATECH

*Professor Emeritus, *Professor Emeritus, Stanford Univ.Stanford Univ.

• • Slide 3

AgendaAgenda• Semiconductor Revenue Growth: Yes!

• Realize Which Roadmap?

• Technology Challenges

• R&D Cost

•• Semiconductor Revenue Growth: Yes!Semiconductor Revenue Growth: Yes!

•• Realize Which Roadmap?Realize Which Roadmap?

•• Technology ChallengesTechnology Challenges

•• R&D CostR&D Cost

• • Slide 4

• Semiconductor Revenue Growth: Yes!

• Realize Which Roadmap?

• Technology Challenges

• R&D Cost

•• Semiconductor Revenue Growth: Yes!Semiconductor Revenue Growth: Yes!

•• Realize Which Roadmap?Realize Which Roadmap?

•• Technology ChallengesTechnology Challenges

•• R&D CostR&D Cost


– Historical Perspective & Extrapolation

• Realize Which Roadmap?– End Equipment & Product– Cost per Function

• Technology Challenges– Mask Availability, Cost, Cycletime– Post – 193nm Exposure Technology– New Materials

• R&D Cost– How Many Si Tech R&D Centers Can the Industry

Support?– R&D Foundries, Partnerships, & Alliances Win!

•• Semiconductor Revenue Growth: Yes!Semiconductor Revenue Growth: Yes!–– Historical Perspective & ExtrapolationHistorical Perspective & Extrapolation

•• Realize Which Roadmap?Realize Which Roadmap?–– End Equipment & ProductEnd Equipment & Product–– Cost per FunctionCost per Function

•• Technology ChallengesTechnology Challenges–– Mask Availability, Cost, CycletimeMask Availability, Cost, Cycletime–– Post Post –– 193nm Exposure Technology193nm Exposure Technology–– New MaterialsNew Materials

•• R&D CostR&D Cost–– How Many Si Tech R&D Centers Can the Industry How Many Si Tech R&D Centers Can the Industry

Support?Support?–– R&D Foundries, Partnerships, & Alliances Win!R&D Foundries, Partnerships, & Alliances Win!

• • Slide 5

Semiconductor Industry Revenue Growth SummarySemiconductor Industry Revenue Semiconductor Industry Revenue Growth SummaryGrowth Summary• 17% CAGR in the 70’s and 80’s

• Drove High Rates of Capital Investment and R&D– In Turn Drove Better Penetration of Existing

Markets and the Opening of New Ones• In Turn Drove Revenue Growth

• This is a Cyclical Growth Industry with a 5-Year Period

• Maturation is Occurring– But not that Fast!

•• 17% CAGR in the 70’s and 80’s17% CAGR in the 70’s and 80’s

•• Drove High Rates of Capital Investment and Drove High Rates of Capital Investment and R&DR&D–– In Turn Drove Better Penetration of Existing In Turn Drove Better Penetration of Existing

Markets and the Opening of New OnesMarkets and the Opening of New Ones•• In Turn Drove Revenue GrowthIn Turn Drove Revenue Growth

•• This is a Cyclical Growth Industry with a 5This is a Cyclical Growth Industry with a 5--Year PeriodYear Period

•• Maturation is OccurringMaturation is Occurring–– But not that Fast!But not that Fast!

• • Slide 6

Projections from a Historical Study of Industry Growth TrendsProjections from a Historical Study Projections from a Historical Study of Industry Growth Trendsof Industry Growth Trends

1

10

100

1000

1970 1975 1980 1985 1990 1995 2000 2005 2010Year

Rev

enue

($B

)

HistoryModelPessimisticOptimisticCyclical Model

Models Based on Growth of Auto Industry 1900 - 2000

17%

14%

16%

10%

20+%20+%20+%

Double Digit Average Growth

Through the End of the Decade

Double Digit Average Growth

Through the End of the Decade

• • Slide 7












• • Slide 8

Roadmap HierarchyRoadmap HierarchyRoadmap Hierarchy

End Equipment (PCs, DVDs, Hand-helds, Wireless)

Products (µPU, DRAM, DSP, Baseband)

Modules (Logic, Memory, Analog)

Specifications (VDD, Freq., Pwr., Cost, Lifetime)

Layout/Architecture (Random, Gate Array, Logic-Based,

Memory-Based)Materials/ Structures

(Cu, Low K, SOI, ½ Pitch)

Processes/Tools (193nm, CMP )

Requirements Solutions

ITRS

Too Much Focus on the Lower Level “REQUIREMENTS” can Drive Unprofitable Investments, i.e.

Too Much Focus on the Lower Too Much Focus on the Lower Level “REQUIREMENTS” can Level “REQUIREMENTS” can Drive Unprofitable Drive Unprofitable Investments, i.e.Investments, i.e.

Low K InterconnectsLow K InterconnectsLow K Interconnects

• • Slide 10

Commodity DRAM Product RoadmapCommodity DRAM Product Commodity DRAM Product RoadmapRoadmap

10

100

1000

10000

100000

1994 1999 2004 2009 2014

Year

Cap

acity

(MB

its)

Commodity DRAM Doubles Every 24 Mos.Doubles Every 18 Mos.

• • Slide 11

10

100

1000

10000

100000

1994 1999 2004 2009 2014

Year

Cap

acity

(MB

its)

Commodity DRAM Doubles Every 24 Mos.Doubles Every 18 Mos.

Embedded SRAMDoubles Every 24 Mos.Doubles Every 18 Mos.

Commodity DRAM & Embedded SRAM Product RoadmapCommodity DRAM & Embedded Commodity DRAM & Embedded SRAM Product RoadmapSRAM Product Roadmap

• • Slide 12

Manufacturing Cost per Function RoadmapsManufacturing Cost per Function Manufacturing Cost per Function RoadmapsRoadmaps• Driven by Transistors per Area and Cost per Area

2-Year Cycle 3-Year Cycle

Annual Transistor per Unit Area Increase 40% 25%

Average Cost per Unit Area Increase – Constant Wafer Size 8% 4%

Average Cost Reduction for Wafer Size Conversion Every 10 Years 4% 4%

Predicted Annual Cost per Function Decrease 27% 21%

•• Driven by Transistors per Area and Cost per AreaDriven by Transistors per Area and Cost per Area

22--Year Cycle 3Year Cycle 3--Year CycleYear Cycle

Annual Transistor per Unit Annual Transistor per Unit Area IncreaseArea Increase 40%40% 25%25%

Average Cost per Unit Area Average Cost per Unit Area Increase Increase –– Constant Wafer SizeConstant Wafer Size 8%8% 4%4%

Average Cost Reduction for Wafer Average Cost Reduction for Wafer Size Conversion Every 10 YearsSize Conversion Every 10 Years 4%4% 4%4%

Predicted Annual Cost per Predicted Annual Cost per Function DecreaseFunction Decrease 27%27% 21%21%

2-Year Cycle Wins!2-Year Cycle Wins!

• • Slide 13

Validated ISMT Cost per Function ModelSlope Change in 1998 due to 2-Year Cycle300mm Cross-Over Predicted in 2004

Validated ISMT Cost per Function ModelValidated ISMT Cost per Function ModelSlope Change in 1998 due to 2Slope Change in 1998 due to 2--Year CycleYear Cycle300mm Cross300mm Cross--Over Predicted in 2004Over Predicted in 2004

1995 1997 1999 2001 2003 2005Years

Cos

t / F

unct

ion

Leading Edge Logic Products

0.35 µmY3

0.25 µmY3

0.18 µmY2

0.13 µmY2

0.13 µm 300mm

20% per Year Reduction

27% per Year Reduction

90 nmY3

• • Slide 14

Major Technology Challenge: The Major Technology Challenge: The Sub Sub –– ½ Wavelength Red Zone½ Wavelength Red Zone

0

100

200

300

400

500

1994 1998 2002 2006 2010 2014

Year

Nod

e (n

m)

248 nm193 nm

157 nm

EUV

CD < λ/2

Driving High Mask CostCD < λ/3

• • Slide 15

AgendaAgendaAgenda• Semiconductor Revenue Growth: Yes!











• • Slide 16

Mask IssuesMask IssuesMask Issues• Phase Shift & OPC Requires 2x+ Resolution

Improvement

• Infrastructure Development Cost not Supported by Revenue

• Database Size Exploding

• Cost Going up 2x per Generation– Manufacturing 130nm $ 600K– 90nm $1200K– 65nm $2400K ?

•• Phase Shift & OPC Requires 2x+ Resolution Phase Shift & OPC Requires 2x+ Resolution ImprovementImprovement

•• Infrastructure Development Cost not Infrastructure Development Cost not Supported by RevenueSupported by Revenue

•• Database Size ExplodingDatabase Size Exploding

•• Cost Going up 2x per GenerationCost Going up 2x per Generation–– ManufacturingManufacturing 130nm130nm $ 600K$ 600K–– 90nm90nm $1200K$1200K–– 65nm65nm $2400K ?$2400K ?

• • Slide 17

Mask Cost Analysis 130nm to 90nmOnly Manufacturing Considered

Mask Cost Analysis 130nm to 90nmMask Cost Analysis 130nm to 90nmOnly Manufacturing ConsideredOnly Manufacturing Considered

$1,000

$10,000

$100,000

10 100 1000 10000Advanced Technology Equivalent Wafers

Cos

t per

Equ

ival

ent A

T W

afer

Full Custom AdvancedTechnology

Previous Node FullCustom Technology

Cross-Over at 500 Wafers

• • Slide 18

Smart Gate Arrays Become More AttractiveSmart Gate Arrays Become Smart Gate Arrays Become More AttractiveMore Attractive

$1,000

$10,000

$100,000


Cos

t per

Equ

ival

ent A

T W

afer



$1,000

$10,000

$100,000


Cos

t per

Equ

ival

ent A

T W

afer



Advanced Technology StdBlock + Gate Array

Cross-Over at 1500 Wafers

• • Slide 19

Summary of Top Technical ChallengesSummary of Top Technical Summary of Top Technical ChallengesChallenges• Mask Availability, Cost, and Cycletime

– Especially for Custom Products

• Post 193nm Litho Exposure Tools– 157nm in Mainstream Production in 2006/2007– EUV in Mainstream Production in 2009/2010

• New Materials– Low K’s– High K’s– Memory Materials

•• Mask Availability, Cost, and CycletimeMask Availability, Cost, and Cycletime–– Especially for Custom ProductsEspecially for Custom Products

•• Post 193nm Litho Exposure ToolsPost 193nm Litho Exposure Tools–– 157nm in Mainstream Production in 2006/2007157nm in Mainstream Production in 2006/2007–– EUV in Mainstream Production in 2009/2010EUV in Mainstream Production in 2009/2010

•• New MaterialsNew Materials–– Low K’sLow K’s–– High K’sHigh K’s–– Memory MaterialsMemory Materials

• • Slide 20

Summary of Top Technical ChallengesSummary of Top Technical Summary of Top Technical ChallengesChallenges• Mask Availability, Cost, and Cycletime

– Especially for Custom Products

• Post 193nm Litho Exposure Tools– 157nm in Mainstream Production in 2006/2007– EUV in Mainstream Production in 2009/2010

• New Materials– Low K’s– High K’s– Memory Materials

•• Mask Availability, Cost, and CycletimeMask Availability, Cost, and Cycletime–– Especially for Custom ProductsEspecially for Custom Products

•• Post 193nm Litho Exposure ToolsPost 193nm Litho Exposure Tools–– 157nm in Mainstream Production in 2006/2007157nm in Mainstream Production in 2006/2007–– EUV in Mainstream Production in 2009/2010EUV in Mainstream Production in 2009/2010

•• New MaterialsNew Materials–– Low K’sLow K’s–– High K’sHigh K’s–– Memory MaterialsMemory Materials

• • Slide 21

AgendaAgendaAgenda• Semiconductor Revenue Growth: Yes!











• • Slide 22

The New Economy for MicroelectronicsThe New Economy for MicroelectronicsThe New Economy for Microelectronics

• A New Factory (Fab) Runs 130nm Technology with Cu Wiring at 300mm

• At a Capital Cost of $2B - $4B– Increasing at a Rate of 15% per Year

• Technology R&D to Support 2-Year Major & 1-Year Minor Product Cycles

• At a Cost of > $500M per Year for a Tier 1 Logic Manufacturer– Increasing at a Rate of > 20% per Year

•• A New Factory (Fab) Runs 130nm Technology with A New Factory (Fab) Runs 130nm Technology with Cu Wiring at 300mmCu Wiring at 300mm

•• At a Capital Cost of $2B At a Capital Cost of $2B -- $4B$4B–– Increasing at a Rate of 15% per YearIncreasing at a Rate of 15% per Year

•• Technology R&D to Support 2Technology R&D to Support 2--Year Major & 1Year Major & 1--Year Year Minor Product CyclesMinor Product Cycles

•• At a Cost of > $500M per Year for a Tier 1 Logic At a Cost of > $500M per Year for a Tier 1 Logic ManufacturerManufacturer–– Increasing at a Rate of > 20% per YearIncreasing at a Rate of > 20% per Year

• • Slide 23

Table Stakes for Independent Semiconductor ManufacturerTable Stakes for Independent Table Stakes for Independent Semiconductor ManufacturerSemiconductor Manufacturer

• Cap Ex of $1B per Year or Min. of 20% of Revenues– Implies Revenues of

$5B/yr

• Technology R&D Investment of $500M per Year– If Requirement of <5%

of Revenues for IDM Implies Revenues of $10B/yr

•• Cap Ex of $1B per Year Cap Ex of $1B per Year or Min. of 20% of or Min. of 20% of RevenuesRevenues–– Implies Revenues of Implies Revenues of

$5B/yr$5B/yr

•• Technology R&D Technology R&D Investment of $500M Investment of $500M per Yearper Year–– If Requirement of <5% If Requirement of <5%

of Revenues for IDM of Revenues for IDM Implies Revenues of Implies Revenues of $10B/yr$10B/yr

• • Slide 24

R&D Partnership Risks & RewardsR&D Partnership Risks & RewardsR&D Partnership Risks & Rewards• Rewards

– Faster Speed of Execution– Lower Costs

• Risks– Sacrifice of IP & Potential Competitive

Advantage– Cultural, Geographic, and NIH Factors

can Slow Progress– Divergence of Interests

•• RewardsRewards–– Faster Speed of ExecutionFaster Speed of Execution–– Lower CostsLower Costs

•• RisksRisks–– Sacrifice of IP & Potential Competitive Sacrifice of IP & Potential Competitive

AdvantageAdvantage–– Cultural, Geographic, and NIH Factors Cultural, Geographic, and NIH Factors

can Slow Progresscan Slow Progress–– Divergence of InterestsDivergence of Interests

• • Slide 25

SummarySummarySummary• Semiconductor Revenue Growth: Yes!

– > 10% CAGR Through the Decade



• R&D Cost– Consolidation of Si Tech R&D Centers Required– R&D Foundries, Partnerships, & Alliances Win!

•• Semiconductor Revenue Growth: Yes!Semiconductor Revenue Growth: Yes!–– > 10% CAGR Through the Decade> 10% CAGR Through the Decade



•• R&D CostR&D Cost–– Consolidation of Si Tech R&D Centers RequiredConsolidation of Si Tech R&D Centers Required–– R&D Foundries, Partnerships, & Alliances Win!R&D Foundries, Partnerships, & Alliances Win!

AddendaAddendaAddenda

• • Slide 28

Silicon Core CMOS – The Platform of Choice

Silicon Core CMOS Silicon Core CMOS –– The Platform of The Platform of ChoiceChoice

• Enabler Products– Broadband– 3+G Wireless

• Voice Recognition– No Keyboards

• BioMedical Electronics– Reduced Cost of Health Care

• Enabler Technologies– MEMS (MicroElectroMechanicalSystems)– NanoTechnology - NanoElectronics– Biotechnology - BioElectronics

•• Enabler ProductsEnabler Products–– BroadbandBroadband–– 3+G Wireless3+G Wireless

•• Voice RecognitionVoice Recognition–– No KeyboardsNo Keyboards

•• BioMedical BioMedical ElectronicsElectronics–– Reduced Cost of Health CareReduced Cost of Health Care

•• Enabler TechnologiesEnabler Technologies–– MEMS (MEMS (MicroElectroMechanicalSystemsMicroElectroMechanicalSystems))–– NanoTechnology NanoTechnology -- NanoElectronicsNanoElectronics–– Biotechnology Biotechnology -- BioElectronicsBioElectronics

Killer App for the Future?Killer App for the Future?Killer App for the Future?

Semiconductor Technology Research, Development

Documents

Transcript of Semiconductor Technology Research, Development