Semiconductor Manufacturing · PDF fileRF Power Ionized CF 4 gas Polysilicon ... Manufacturing...
Transcript of Semiconductor Manufacturing · PDF fileRF Power Ionized CF 4 gas Polysilicon ... Manufacturing...
1/41Semiconductor Manufacturing Technologyby Michael Quirk and Julian Serda
Semiconductor Manufacturing Technology
Michael Quirk & Julian Serda © October 2001 by Prentice Hall
Chapter 9
IC Fabrication Process Overview
2/41Semiconductor Manufacturing Technologyby Michael Quirk and Julian Serda
Objectives
After studying the material in this chapter, you will be able to:
1. Draw a diagram showing how a typical wafer flows in a sub-micron CMOS IC fab.
2. Give an overview of the six major process areas and the sort/test area in the wafer fab.
3. For each of the 14 CMOS manufacturing steps, describe its primary purpose.
4. Discuss the key process and equipment used in each CMOS manufacturing step.
3/41Semiconductor Manufacturing Technologyby Michael Quirk and Julian Serda
Major Fabrication Steps in MOS Process Flow
Used with permission from Advanced Micro Devices
Figure 9.1
Used with permission from Advanced Micro Devices
Oxidation(Field oxide)
Silicon substrate
Silicon dioxide
oxygen
PhotoresistDevelop
oxide
PhotoresistCoating
photoresist
Mask-WaferAlignment and Exposure
Mask
UV light
Exposed Photoresist
exposedphotoresist
GGS D
Active Regions
top nitridetop nitride
S DGG
silicon nitride
NitrideDeposition
Contact holes
S DG
ContactEtch
Ion Implantation
resist
resist
oxox D
G
Scanning ion beam
S
Metal Deposition and
Etch
drainS DG
Metal contacts
PolysiliconDeposition
polysilicon
Silane gas
Dopant gas
Oxidation(Gate oxide)
gate oxide
oxygen
PhotoresistStrip
oxide
RF Power
Ionized oxygen gas
OxideEtch
photoresistoxide
RF Power
Ionized CF4 gas
PolysiliconMask and Etch
RF Power
oxideoxide
Ionized CCl4 gas
poly
gate
RF Power
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CMOS Process Flow
• Overview of Areas in a Wafer Fab– Diffusion– Photolithography– Etch– Ion Implant– Thin Films– Polish
• CMOS Manufacturing Steps• Parametric Testing• 6~8 weeks involve 350-step
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Model of Typical Wafer Flow in a Sub-Micron CMOS IC Fab
Test/Sort Implant
Diffusion Etch
Polish
PhotoCompleted Wafer
Unpatterned Wafer
Wafer Start
Thin Films
Wafer Fabrication (front-end)
Figure 9.2
6 major production areas
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Diffusion: Simplified Schematic of High-Temperature Furnace
Gas flowcontroller
Temperaturecontroller
Pressurecontroller
Heater 1
Heater 2
Heater 3
Exhaust
Process gas
Quartz tube
Three-zoneHeating Elements
Temperature-setting voltages
Thermocouplemeasurements
Figure 9.3
Can do : oxidation, diffusion, deposition, anneals, and alloy
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Photolithography Bay in a Sub-micron Wafer Fab
Photo 9.1
Yellow fluorescent: do not affect photoresist
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Load StationVapor Prime
Soft Bake
Cool Plate
Cool Plate
Hard Bake
Transfer StationResist Coat
Develop-Rinse
Edge-Bead Removal
Wafer Transfer SystemWafer Cassettes
Wafer Stepper (Alignment/Exposure System)
Simplified Schematic of a Photolithography Processing Module
Figure 9.4
Note: wafers flow from photolithography into only two other areas: etch and ion implant
9/41Semiconductor Manufacturing Technologyby Michael Quirk and Julian Serda
Simplified Schematic of Dry Plasma Etcher
Figure 9.5
e-
e-
R+
λ Glow discharge (plasma)
Gas distribution baffle High-frequency energy
Flow of byproducts and process gases
Anode electrode
Electromagnetic field
Free electron
Ion sheath
Chamber wall
Positive ion
Etchant gas entering gas inlet
RF coax cable
Photon
Wafer
Cathode electrode
Radical chemical
Vacuum line
Exhaust to vacuum pump
Vacuum gauge
e-
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Simplified Schematic of Ion Implanter
Ion source
Analyzing magnet
Acceleration column
Beamline tube
Ion beam
Plasma
Graphite
Process chamber
Scanning disk
Mass resolving slit
Heavy ions
Gas cabinet
Filament
Extraction assembly
Lighter ions
Figure 9.6
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Thin Film Metallization Bay
Photo courtesy of Advanced Micro Devices
Photo 9.2
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Simplified Schematics of CVD Processing System
Capacitive-coupled RF input
Susceptor
Heat lamps
Wafer
Gas inlet
Exhaust
Chemical vapor deposition
Process chamber
CVD cluster tool
Figure 9.7
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Polish Bay in a Sub-micron Wafer Fab
Photo courtesy of Advanced Micro Devices
Photo 9.3
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1. Twin-well Implants
2. Shallow Trench Isolation
3. Gate Structure
4. Lightly Doped Drain Implants
5. Sidewall Spacer
6. Source/Drain Implants
7. Contact Formation
8. Local Interconnect
9. Interlayer Dielectric to Via-1
10. First Metal Layer
11. Second ILD to Via-2
12. Second Metal Layer to Via-3
13. Metal-3 to Pad Etch
14. Parametric Testing
Passivation layer Bonding pad metal
p+ Silicon substrate
LI oxide
STI
n-well p-well
ILD-1
ILD-2
ILD-3
ILD-4
ILD-5
M-1
M-2
M-3
M-4
Poly gate
p- Epitaxial layer
p+
ILD-6
LI metal
Via
p+ p+ n+n+n+ 23
1
4
5
67
8
9
10
11
12
13
14
CMOS Manufacturing Steps
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n-well Formation
3
1
2
Photo
Implant
Diffusion
4
Polish
Etch
5
Thin Films
~5 um
(Dia = 200 mm, ~2 mm thick)
Photoresist
Phosphorus implant
3
1
2
p+ Silicon substrate
p- Epitaxial layer
Oxide
5
n-well4
Figure 9.8
•Epitaxial layer : improved quality and fewer defect•In step 2, initial oxide: (1) protects epi layer from contamination, (2) prevents excessive damage to ion/implantation, (3) control the depth of the dopant during implantation•In step 5, anneal: (1) drive-in, (2) repair damage, (3) activation
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p-well Formation
Thin Films
3
1
2
Photo
Implant
Diffusion
Polish
Etch
p+ Silicon substrate
Boron implant
Photoresist1
p- Epitaxial layer
Oxide
3n-well 2 p-well
Figure 9.9
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STI Trench Etch
Thin Films
1 2
Photo
Polish
Etch
Implant
Diffusion
3 4
+Ions
Selective etching opens isolation regions in the epi layer.
p+ Silicon substrate
p- Epitaxial layer
n-well p-well
3 Photoresist
2 Nitride 4
1 Oxide
STI trench
Figure 9.10
STI: shallow trench isolation
1. Barrier oxide: a new oxide2. Nitride: (1) protect active region, (2) stop layer during CMP3. 3rd mask4. STI etching
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STI Oxide Fill
1
2
Diffusion
Polish
EtchPhoto
Implant
Thin Films
p-well
Trench fill by chemical vapor deposition
1
Liner oxide
p+ Silicon substrate
p- Epitaxial layer
n-well
2
NitrideTrench CVD oxide
Oxide
Figure 9.11
1. Liner oxide to improve the interface between the silicon and trench CVD oxide2. CVD oxide deposition
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STI Formation
Thin Films
1
2
Diffusion EtchPhoto
Implant
Polish
p-well
1
2
Planarization by chemical-mechanical polishing
STI oxide after polish
Liner oxide
p+ Silicon substrate
p- Epitaxial layer
n-well
Nitride strip
Figure 9.12
1. Trench oxide polish (CMP): nitride as the CMP stop layer since nitride is harder than oxide2. Nitride strip: hot phosphoric acid
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Poly Gate Structure Process
Thin Films
1 2
Diffusion EtchPhoto
Implant
Polish
3 4
p+ Silicon substrate
Gate oxide1
2
p- Epitaxial layer
n-well p-well
Polysilicon deposition Poly gate etch4
3 Photoresist
ARC
Figure 9.13
1. Oxide thickness 1.5 ~ 5.0 nm is thermal grown2. Poly-Si ~ 300 nm is doped and deposited in LPCVD using SiH43. Need Antireflective coating (ARC), very critical4. The most critical etching step in dry etching
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n− LDD Implant
Thin Films
1
2
Diffusion EtchPhoto
Implant
Polish
p+ Silicon substrate
p- Epitaxial layer
n-well p-welln-n-n-
1 Photoresist mask
Arsenic n- LDD implant2
Figure 9.14
1. LDD: lightly doped drain to reduce S/D leakage2. Large mass implant (BF2, instead of B, As instead of P) and amorphous
surface helps maintain a shallow junction 3. 5th mask
22/41Semiconductor Manufacturing Technologyby Michael Quirk and Julian Serda
p− LDD Implant
1
2
Diffusion EtchPhoto
Implant
PolishThin Films
p+ Silicon substrate
p- Epitaxial layer
n-well p-well
Photoresist Mask1
p-p-
Photoresist mask1
n-n-
2 BF p- LDD implant2
p-n-
Figure 9.15
1. 6th mask2. In modern device, high doped drain is used to reduce series
resistance. It called S/D extension
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Side Wall Spacer Formation
1
2
Diffusion EtchPhoto
Implant
PolishThin Films +Ions
p+ Silicon substrate
p- Epitaxial layer
n-well p-wellp-p-
1 Spacer oxide Side wall spacer
2 Spacer etchback by anisotropic plasma etcher
p-n- n-n-
Figure 9.16
Spacer is used to prevent higher S/D implant from penetrating too close to the channel
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n+ Source/Drain Implant
Thin Films
1
2
Diffusion EtchPhoto
Implant
Polish
p+ Silicon substrate
p- Epitaxial layer
n-well p-welln+
Arsenic n+ S/D implant2
Photoresist mask1
n+ n+
Figure 9.17
1. Energy is high than LDD I/I, the junction is deep2. 7th mask
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p+ Source/Drain Implant
1
2
Diffusion EtchPhoto
PolishThin Films
Implant
3
Boron p+ S/D implant2
p+ Silicon substrate
p- Epitaxial layer
n-well p-well
Photoresist Mask11 Photoresist mask
n+ p+ p+ n+ n+ p+
Figure 9.18
1. 8th mask2. Using rapid thermal anneal (RTA) to prevent dopant
spreading and to control diffusion of dopant
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Contact Formation
Thin Films
1 2
Diffusion EtchPhoto
Implant
Polish3 2 Tisilicide contact formation (anneal)Titanium etch3
Titanium depostion1
n+ p+ n-well p+ n+ p-well n+ p+
p- Epitaxial layer
p+ Silicon substrate
Figure 9.19
1. Titanium (Ti) is a good choice for metal contact due to low resistivity and good adhesion
2. No mask needed, called self-align3. Using Ar to sputtering metal4. Anneal to form TiSi2, tisilicide5. Chemical etching to remove unreact Ti, leaving TiSi2, called
selective etching
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LI Oxide as a Dielectric for Inlaid LI Metal (Damascene)
LI metal
LI oxide
Figure 9.20
LI: local interconnection
Damascene: a name doped of year ago from a practice that began thousands ago by artist in Damascus, Syria
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LI Oxide Dielectric Formation
1 Nitride CVD
p-wellp-well
p- Epitaxial layer
p+ Silicon substrate
LI oxide
2 Doped oxide CVD
4 LI oxide etchOxide polish3
Diffusion EtchPhoto
Implant
Polish
3
4
2
1Thin Films
Figure 9.21
1. Nitride: protect active region2. Doped oxide 3. Oxide polish4. 9th mask
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LI Metal Formation
Thin Films
Diffusion Photo
Implant
321 4
Etch
Polish
n-well
LI tungsten polishTungsten deposition
Ti/TiN deposition2
3 4
LI oxide
Ti deposition1 p-well
p- Epitaxial layer
p+ Silicon substrate
Figure 9.22
Ti/TiN is used: Ti for adhesion and TiN for diffusion barrier
Tungsten (W) is preferred over Aluminum (Al) for LI metal due to its ability to fill holes without leaving voids
30/41Semiconductor Manufacturing Technologyby Michael Quirk and Julian Serda
Via-1 Formation
Diffusion EtchPhoto
Implant
Polish
3
2
1 Thin Films
Oxide polishILD-1 oxide etch(Via-1 formation)2 3
LI oxide
ILD-1 oxide deposition
1
ILD-1
p-welln-well
p- Epitaxial layer
p+ Silicon substrate
Figure 9.23
1. Interlayer dielectric (ILD): insulator between metal2. Via: electrical pathway from one metal layer to adjacent metal layer3. 10 th mask
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Plug-1 Formation
Thin Films
Diffusion Photo
Implant
321 4
Etch
Polish
Tungsten polish (Plug-1)TungstendepositionTi/TiN
deposition23 4
LI oxide
Ti dep.1 ILD-1
p-welln-well
p- Epitaxial layer
p+ Silicon substrate
Figure 9.24
1. Ti layer as a glue layer to hold W2. TiN layer as the diffusion barrier3. Tungsten (W) as the via4. CMP W-polish
32/41Semiconductor Manufacturing Technologyby Michael Quirk and Julian Serda
SEM Micrographs of Polysilicon, Tungsten LI and Tungsten Plugs
Micrograph courtesy of Integrated Circuit Engineering
PolysiliconTungsten LI
Tungsten plug
Mag. 17,000 X
Photo 9.4
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Metal-1 Interconnect Formation
2 3 41
TiN deposition
Al + Cu (1%)deposition
Ti Deposition
LI oxide
ILD-1
Metal-1 etch
p-welln-well
p- Epitaxial layer
p+ Silicon substrate
Photo EtchDiffusion
Implant
4
1 32
PolishThin Films
Figure 9.25
1. Metal stack: Ti/Al (or Cu)/TiN is used2. Al(99%) + Cu (1%) is used to improve reliability3. 11th mask
34/41Semiconductor Manufacturing Technologyby Michael Quirk and Julian Serda
SEM Micrographs of First Metal Layer over First Set of Tungsten Vias
Micrograph courtesy of Integrated Circuit Engineering
TiN metal cap
Mag. 17,000 XTungsten plug
Metal 1, Al
Photo 9.5
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4
p+ Silicon substrate
p- Epitaxial layer
n-well p-well
LI oxide
ILD-1
Oxide polish
ILD-2 gap fill1
32 ILD-2 oxide
depositionILD-2 oxide etch(Via-2 formation)
Photo Etch
Polish
Diffusion
Implant
4
2 31Thin Films
Via-2 Formation
Figure 9.26
1. Gap fill: fill the gap between metal2. Oxide deposition3. Oxide polish4. 12 th mask
36/41Semiconductor Manufacturing Technologyby Michael Quirk and Julian Serda
Plug-2 Formation
LI oxide
Tungsten deposition (Plug-2)
Ti/TiN deposition2
3
Ti deposition1
ILD-1
ILD-2
p+ Silicon substrate
p- Epitaxial layer
n-well p-well
Tungstenpolish4
Thin Films
Diffusion Photo
Implant
321 4
Etch
Polish
Figure 9.27
1. Ti/TiN/W 2. CMP W polish
37/41Semiconductor Manufacturing Technologyby Michael Quirk and Julian Serda
Metal-2 Interconnect Formation
p+ Silicon substrate
p- Epitaxial layer
n-well p-well
Gap fill
3 Via-3/Plug-3 formationMetal-2 depositionto etch
ILD-3 oxidepolish
2
14
LI oxide
ILD-1
ILD-2
ILD-3
Figure 9.28
1. Metal 2: Ti/Al/TiN2. ILD-3 gap filling3. ILD-34. ILD-polish5. Via-3 etch and via deposition, Ti/TiN/W
38/41Semiconductor Manufacturing Technologyby Michael Quirk and Julian Serda
Full 0.18 µm CMOS Cross Section
Figure 9.29
Passivation layer Bonding pad metal
p+ Silicon substrate
LI oxide
STI
n-well p-well
ILD-1
ILD-2
ILD-3
ILD-4
ILD-5
M-1
M-2
M-3
M-4
Poly gate
p- Epitaxial layer
p+n+
ILD-6
LI metal
Via
p+ p+ n+n+
1. Passivation layer of nitride is used to protect from moisture, scratched, and contamination
2. ILD-6 : oxide
39/41Semiconductor Manufacturing Technologyby Michael Quirk and Julian Serda
SEM Micrograph of Cross-section of AMD Microprocessor
Micrograph courtesy of Integrated Circuit EngineeringMag. 18,250 X
Photo 9.6
40/41Semiconductor Manufacturing Technologyby Michael Quirk and Julian Serda
Wafer Electrical Test using a Micromanipulator Prober(Parametric Testing)
Photo courtesy of Advanced Micro Devices
Photo 9.7
1. After metal-1 etch, wafer is tested, and after passivation test again
2. Automatically test on wafer, sort good die (X-Y position, previous marked with an red ink)
3. Before package, wafer is backgrind to a thinner thickness for easier slice and heat dissipation
41/41Semiconductor Manufacturing Technologyby Michael Quirk and Julian Serda
Chapter 9 Review
• Summary 222• Key Terms 223• Review Questions 223• SMT Web Site• References 224