Semiconductor Fabrication Lecture Notes

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    Semiconductor Fabrication

    The process used in the creation of chips, the integrated circuits that we see being

    used in everyday electrical and electronic devices. It involves a sequence of photographic

    and chemical processing steps dealing with a piece of pure semiconducting material,

    called a wafer, upon which electronic circuits are gradually created on. The most

    commonly used semiconductor, silicon, is fabricated this way, as is other specialapplication materials such as gallium arsenide, germanium, and many others.

    Silicon

    The outer crust of this planet (the first 100 km or so) consists of all kinds of

    silicates (Si + O + something else) so there is no lack of Si as a raw material. Si, in fact,

    accounts for about 26 % of the crust, while O weighs in at about 49 %. What we need, of

    course, are Si crystals - in the form of wafers - with extreme degrees of perfection. What

    we have are inexhaustible resources of silicon dioxide, SiO2, fairly clean, if obtainedfrom the right source. Raw silicon is obtained through the reduction of the oxides by

    providing some reducing agent and sufficient energy to achieve the necessary high

    temperatures. Essentially, you have a huge furnace with three big graphite electrodes

    carrying 10A of current inside that is continuously filled with SiO2 (quartz sand) and

    carbon (coal) in the right weight relation plus a few added secret ingredients to avoid

    producing SiC. At about 2000C the chemical reaction that takes place is:

    SiO2 + 2C = Si + 2CO

    Raw Silicon Reactor

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    Wafers

    Fabrication starts with the creation of wafers. In microelectronics, it is a thin slice

    of semiconducting material, such as a silicon crystal, upon which microcircuits areconstructed by doping (for example, diffusion or ion implantation), etching, anddeposition of various materials. Wafers are thus of key importance in the fabrication of

    semiconductor devices such as integrated circuits.

    They are made in various sizes ranging from 1 inch (25.4 mm) to 11.8 inches (300

    mm), and thickness of the order of 0.5 mm. Generally, using a diamond saw they are cut

    from a boule of semiconductor made through the Czochralski process, then polished on

    one or both faces.

    Silicon Boule Czochralski process

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    Wafer Polishing

    Wafers under 200mm generally have flats indicating crystallographic planes of

    high symmetry (usually the {110} face) and, in old-fashioned wafers (those below about

    100mm diameter), the wafer's orientation and doping type. Modern wafers use a notch to

    convey this information, in order to waste less material.

    Wafer Flats Convention

    Orientation is important since many of a single crystal's structural and electronic

    properties are highly anisotropic. For instance, wafer cleavage typically occurs only in a

    few well-defined directions. Scoring the wafer along cleavage planes allows it to be

    easily diced into individual chips ("dies") so that the billions of individual circuitelements on an average wafer can be separated into many individual circuits.

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    Etched Silicon Wafer

    Structure of a 150mm wafer of 16Mb DRAM chips

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    Processing

    Once the wafers are prepared, many process steps are necessary to produce the

    desired semiconductor integrated circuit. In general the steps can be grouped into fourareas; front end processing, back end processing, testing and packaging.

    Front End Processing refers to the most crucial steps in the fabrication. In this

    stage the actual devices, including transistors and resistors are created. A typical front

    end process includes the following: preparation of the wafer surface, growth of silicon

    dioxide (SiO2), patterning and subsequent implantation or diffusion of dopants to obtain

    the desired electrical properties, growth or deposition of a gate dielectric, and growth or

    deposition of insulating materials to isolate neighboring devices.

    Once the various semiconductor devices have been created they must be

    interconnected to form the desired electrical circuits. This "Back End Processing"involves depositing layers of metal and insulating material and etching it into the desired

    patterns. Typically the metal layers consist of aluminum or more recently copper. Theinsulating material was traditionally a form of SiO2 or a silicate glass, but recently new

    low dielectric constant materials are being used. The various metal layers areinterconnected by etching holes, called "vias" in the insulating material and depositing

    tungsten in them.

    Once the Back End Processing has been completed, the semiconductor devices

    are subjected to a variety of electrical tests to determine if they function properly. Finally,the wafer is cut into individual dice, which are then packaged in ceramic or plastic

    packages with pins or other connectors to the outside world. The packaged chips are then

    retested to ensure that they were not damaged during packaging and that the die-to-pin

    interconnect operation was performed correctly.

    Steps in Fabrication

    I. Wafer fabrication

    1. Wet Cleans - non-toxic, environmentally safe dry-cleaning alternative utilizingcomputer controlled washing machines, biodegradeable soaps and conditioners,

    and specialized finishing (pressing) equipment suitable for virtually allfabric/fiber types.

    2. Photolithography - a process used to transfer a pattern from a photomask (alsocalled reticle) to the surface of a substrate. It involves a combination of substrate

    preparation, chemical deposition, photoresist spinning, soft-baking, exposure,

    developing, hard-baking, and etching.

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    Photolithography structure model

    3. Ion implantation - process by which ions of a material can be implanted intoanother solid, thereby changing the physical properties of the solid. The ions

    introduce both a chemical change in the target, in that they can be a different

    element than the target, and a structural change, in that the crystal structure of the

    target can be damaged or even destroyed. This process is commonly used toembed dopants in the wafer creating regions of increased (or decreased)

    conductivity.

    4. Dry Etching - the removal of material, typically a masked pattern ofsemiconductor material, by exposing the material to a bombardment of ions that

    dislodge portions of the material from the exposed surface. The process typicallyetches directionally or anisotropically. Also known as plasma etching.

    5. Wet Etching - the removal of material by immersing the wafer in a liquid bath ofchemical etchant. Also known as chemical etching. There are two kinds of wetetching etchants:

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    A) Isotropic etchants attack the material being etched at the same rate in all

    directions.

    Isotropic Etching

    B) Anisotropic etchants attack the silicon wafer at different rates in differentdirections. On wafers the most used etchant is KOH. Anisotropic etching does

    not cause undercutting, and is preferred in applications where straight side

    walls are essential.

    6. Plasma ashing - the process of removing the photoresist from an etched wafer.Using a plasma source, a monatomic reactive specie is generated. Oxygen and

    fluorine are the most common reactive specie. The reactive specie combines with

    the photoresist to form ash, which is removed with a vacuum pump.

    7. Thermal treatments - heating of wafers in order to affect its electrical properties.Unique heat treatments are designed for different effects. Wafers can be heated in

    order to activate dopants, change film to film or film to wafer substrate interfaces,

    densify deposited films, change states of grown films, repair damage from ion

    implantation, move dopants or drive dopants from one film into another or from afilm into the wafer substrate. It can be done by:

    A) Rapid thermal anneal - performed by equipment that heats a single wafer at a

    time using either lamp based heating, a hot chuck, or a hot plate that a wafer is

    brought near. They are short in duration, processing each wafer in severalminutes.

    B) Furnace anneals - performed by equipment especially built to heat

    semiconductor wafers. Furnaces are capable of processing lots of wafers at a

    time but each process can last between several hours and a day.

    8. Chemical vapor deposition (CVD) - process for depositing thin films of variousmaterials by chemical means. In a typical CVD process the substrate is exposed to

    one or more volatile precursors, which react and/or decompose on the substrate

    surface to produce the desired deposit. Frequently, volatile byproducts are alsoproduced, which are removed by gas flow through the reaction chamber.

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    9. Physical vapor deposition (PVD) - process for depositing thin films of variousmaterials by mechanical or thermodynamic means. The material to be deposited isplaced in a heated environment, so that particles of material escape its surface.

    Facing this source is a cooler surface that draws energy from these particles asthey arrive, allowing them to form a solid layer. The whole system is kept in avacuum deposition chamber, to allow the particles to travel as freely as possible.

    Since particles tend to follow a straight path, films deposited by physical means

    are commonly directional, rather than conformal.

    A) Thermal evaporator - uses an electric resistance heater to melt the material and

    eventually evaporate, and the vapor will reach the substrate to be deposited as

    a solid. Only materials with a much higher vapor pressure than the heating

    element can be deposited without contamination of the film.

    B) Electron beam evaporator - fires a high-energy beam from an electron gun toboil a small spot of material; since the heating is not uniform, lower vapor

    pressure materials can be deposited.C) Sputtering - relies on a plasma (usually a noble gas, such as Argon) to knock

    material from a "target" a few atoms at a time. The sputtered atoms are ejectedinto the gas phase and are not in their thermodynamic equilibrium state.

    Therefore, they tend to condense back into the solid phase upon colliding with

    any surface in the sputtering chamber.

    Sputter chamber

    D) Pulsed laser deposition uses pulses of focused laser light to transform the

    target material directly from solid to plasma; this plasma usually reverts to a

    gas before it reaches the substrate but sufficiently high vacuum will allow

    momentum to carry this gas to the substrate, where it condenses to a solidstate.

    10.Molecular beam epitaxy (MBE) - the deposition of one or more pure materialsonto a single crystal wafer, one layer of atoms at a time, under ultra-high vacuum,

    forming a perfect crystal. In solid-source MBE, ultra-pure elements are heated in

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    separate furnaces until they each slowly begin to evaporate. The evaporated

    elements condense on the wafer, where they react with each other to form acrystal. The term "beam" simply means that evaporated atoms do not meet each

    other or any other gases until they reach the wafer.11.Electroplating - the coating of an electrically conductive item with a layer of

    metal using electrical current. The result is a thin, smooth, even coat of metal on

    the object.

    12.Chemical mechanical polish / planarization (CMP) used to planarizing the topsurface of the substrate. The process is used to polish the surface, removing

    excess material and even out any irregular topography.

    13.Wafer testing - performed before a wafer is sent to die preparation, all individualintegrated circuits that are present on the wafer are tested for functional defects by

    applying special test patterns to them. The wafer testing is performed by a pieceof test equipment called a prober, and the process is sometimes referred to as a

    probe test or wafer sort.14.Wafer backgrinding - a polishing technique applied on the bottom of the wafer

    used to reduce the thickness of the wafer so the resulting chip can be put into athin device like a smart card or PCMCIA card.

    II. Die preparation

    1. Wafer mounting - during this step, the wafer is mounted on a plastic tape that isattached to a ring. Wafer mounting is performed right before the wafer is cut intoseparate dies. The adhesive tape on which the wafer is mounted ensures that the

    individual dies remain firmly in place during 'dicing'.

    Wafer glued on blue tape and cut into pieces

    2. Die cutting - the individual dies contained in the wafer are cut into separatepieces. In between the functional parts of the circuits, a thin non-functional

    spacing is foreseen where a saw can safely cut the wafer without damaging thecircuit. This spacing is called the scribe. The width of the scribe is very small,

    typically around 100 Jm. A very thin and accurate saw is therefore needed to cut

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    the wafer into pieces. Usually the dicing is performed with a water-cooled circular

    saw with diamond-tipped teeth.III. IC packaging

    1. Die attachment - process upon which a die is mounted and fixed to the package orsupport structure. For high-powered applications, the die is usually soldered ontothe package (for good heat conduction). For low-cost, low-powered applications,

    the die is often glued directly onto a substrate (such as a printed wiring board)

    using an epoxy adhesive.

    Die attachment

    2. IC Bonding - process of making interconnections between a microchip and theoutside world.

    A) Wire bonding makes use of wires for the interconnections. The wire is

    generally made up of one of the following: gold, aluminum and copper. Wire

    diameters start at 15Jm and can be up to several hundred micrometers for

    high-powered applications, and are attached at both ends using some

    combination of heat, pressure, and ultrasonic energy to make a weld. Wire

    bonding is generally considered the most cost-effective and flexibleinterconnect technology, and is used to assemble the vast majority of

    semiconductor packages.B) Flip chip a processing step that deposits solder beads on the chip pads. After

    cutting the wafer into individual dice, the "flip chip" is then mounted upside

    down in/on the package and the solder reflowed. Flip chips then normally will

    undergo an underfill process that will cover the sides of the die, similar to the

    encapsulation process. Also known as the Controlled Collapse Chip

    Connection, or C4.

    Ceramic Land Grid Array and Ceramic Ball Grid Array Flip Chips

    C) Tape automated bonding (TAB) - the process of mounting a die on a flexibletape made of polymer material, such as polyimide. The mounting is done such

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    that the bonding sites of the die, usually in the form of bumps or balls made of

    gold or solder, are connected to fine conductors on the tape, which provide themeans of connecting the die to the package or directly to external circuits.

    Sometimes the tape on which the die is bonded already contains the actualapplication circuit of the die.

    Tape automated bonding

    3. IC encapsulation - the design and manufacturing of protective packages for thecompleted IC.

    IV. IC testing - the finished product undergoes a final testing procedure to check forfunctionality before shipping.