Materials Science in Electronics devices - …denko/lecture/lecture/denshi...・ Material issue of...

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Materials Science in Electronics devices - Semiconductor devices - 2015 Yutaka Oyama [email protected] http://www.material.tohoku.ac.jp/~denko/lab.html Contents Material issue of semiconductor devices and fabrication process Schematics of thin film growth (Molecular Layer Epitaxy, etc.) Ultra fast and high frequency semiconductor electronic and photonic devices -1 Ultra fast and high frequency semiconductor electronic and photonic devices -2 Crystal growth and semiconductor device epitaxy Device grade evaluation of semiconductor crystals

Transcript of Materials Science in Electronics devices - …denko/lecture/lecture/denshi...・ Material issue of...

Page 1: Materials Science in Electronics devices - …denko/lecture/lecture/denshi...・ Material issue of semiconductor devices and fabrication process • Schematics of thin film growth

Materials Science in Electronics devices

- Semiconductor devices -

2015 Yutaka Oyama

[email protected]

http://www.material.tohoku.ac.jp/~denko/lab.html

Contents

・ Material issue of semiconductor devices and fabrication process

• Schematics of thin film growth (Molecular Layer Epitaxy, etc.)

・ Ultra fast and high frequency semiconductor electronic and photonic devices -1

• Ultra fast and high frequency semiconductor electronic and photonic devices -2

・ Crystal growth and semiconductor device epitaxy

・ Device grade evaluation of semiconductor crystals

Page 2: Materials Science in Electronics devices - …denko/lecture/lecture/denshi...・ Material issue of semiconductor devices and fabrication process • Schematics of thin film growth

半導体デバイスは、「金属・半導体・セラミックス」を総合して形成。理想型静電誘導トランジスタのプロセス例

METAL

35A

HEAVY DOPING

DOPING EPITAXY 1019-1020cm-3

(SURFACE STOICHIOMETRY CONTROL)

LOW-T& SELECTIVE

MOLECULAR LAYER EPITAXY (MLE)

WITH ATOMIC ACCURACY (AA)

HIGH QUALITY

REGROWN INTERFACE(SURFACE STOICHIOMETRY CONTROL)

LOW c CONTACT(METAL/SEMI CONTACT)NON-ALLOYED

VERY THIN MIXED LAYER

SELECTIVE EPITAXY

(SELF-ALIGN PROCESS)

ULTRA SHALLOW GROVE

LOW-T&DAMAGE ETCHING(PHOTO-STIMULATED GAS FLOW ETCHING)

LOW-T&DAMAGE SiN CVD

(REMOTE PLASMA CVD)

MISゲート{

DETAILED CRITICAL PROCESSES FOR ISITMETAL/CERAMICS/SEMICONDUCTOR BREAKTHROUGH PROCESSES

Page 3: Materials Science in Electronics devices - …denko/lecture/lecture/denshi...・ Material issue of semiconductor devices and fabrication process • Schematics of thin film growth

S/D=3.5nm

Page 4: Materials Science in Electronics devices - …denko/lecture/lecture/denshi...・ Material issue of semiconductor devices and fabrication process • Schematics of thin film growth

薄膜エピタキシャル成長

・液相エピタキシ

・気相エピタキシ

・超高真空エピタキシ

希薄環境相の結晶成長徐冷法ネルソン法温度差法

LED,LDなど発光デバイスの大量生産一般的にはミクロン・サブミクロンデバイスに適用高純度(偏析効果)・高品質低コスト

塩化物気相エピタキシ有機金属気相エピタキシ(MOVPE)

など

発光デバイス~トランジスタ・量子効果デバイスまでミクロン~サブミクロン~ナノ構造まで広範囲原料の高純度化気相反応+表面反応

分子線エピタキシ(MBE)

分子層エピタキシ(MLE,ALE)

ケミカルビームエピタキシ(CBE)

など

発光デバイス~トランジスタ・量子効果デバイスまでミクロン~サブミクロン~ナノ構造まで広範囲原料の高純度化表面反応

LPE

Liquid phase epitaxy

VPE

Vapor phase epitaxy

UHV

Ultra high vacuum

epitaxy

Thin film epitaxial growth

Page 5: Materials Science in Electronics devices - …denko/lecture/lecture/denshi...・ Material issue of semiconductor devices and fabrication process • Schematics of thin film growth

Detailed reaction processes of Epitaxial growth

・Si_react

Vapor phase or solution reaction

Diffusion to the surface

Surface adsorption

Surface reaction

Surface diffusion

(migration)nucleation

desorption

Real surface reaction

process in MLE Si

Page 6: Materials Science in Electronics devices - …denko/lecture/lecture/denshi...・ Material issue of semiconductor devices and fabrication process • Schematics of thin film growth

Spiral growth necleus centers on facets

LPE GaAs (screw dislocation)

Page 7: Materials Science in Electronics devices - …denko/lecture/lecture/denshi...・ Material issue of semiconductor devices and fabrication process • Schematics of thin film growth

Principle of MLE :GaAs case

Molecular Layer Epitaxy in brief

ALE(Atomic Layer Epitaxy) of poly-ZnS on glass substrate for EL application

T. Suntola, U.S. Patent 4058430, 1977.

M. Ahonen, M. Pessa, T. Suntola, Thin Solid Films 65 (1980) 301.

MLE(Molecular Layer Epitaxy) of GaAs single crystal on GaAs

J. Nishizawa et. al. Extended Abstracts of the 16th Conference on Solid State Device and Materials

(The Japan Society of Applied Physics, Kobe, Japan, 1984), p. 1.

J. Nishizawa, et. al. J. Electrochem. Soc., 132 (1985) 1197.

Page 8: Materials Science in Electronics devices - …denko/lecture/lecture/denshi...・ Material issue of semiconductor devices and fabrication process • Schematics of thin film growth

Molecular layer epitaxy of GaAs

Thin Solid Films, 225 (1993), 1-6.

Jun-ichi Nishizawa, Hiroshi Sakuraba Yutaka Oyama など

Principle of MLE

Mono-molecular layer epitaxy

Self-limiting epitaxy with atomic accuracy (AA)

Area selective epitaxy

Page 9: Materials Science in Electronics devices - …denko/lecture/lecture/denshi...・ Material issue of semiconductor devices and fabrication process • Schematics of thin film growth

表面反応Surface reaction process

Page 10: Materials Science in Electronics devices - …denko/lecture/lecture/denshi...・ Material issue of semiconductor devices and fabrication process • Schematics of thin film growth

Impurity doping: control of surface stoichiometry

Electrical activation of Te and Se in GaAs at extremely heavy doping up to 5×1020cm-3 prepared by

intermittent injection of TEG/AsH3 in ultra-high vacuum,

Journal of Crystal Growth, Volume 212, Issues 3-4, May 2000, Pages 402-410

Yutaka Oyama, Jun-ichi Nishizawa, Kohichi Seo and Ken Suto など Ohno T et. al.

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0

0.5

1

1.5

2

2.5

DEZn Pressure (Torr)

Car

rier

Co

nce

ntr

atio

n (

cm-3

)

Gro

wth

Rat

e (A

/C

ycl

e)

AA Mode(C.C.)

AA'Mode(C.C.)

IG Mode(C.C.)

10

10

10

10

20

19

19

18

1x

5x

1x

5x

10 10 10 10-6 -5 -5 -4

3x 1x 3x 1x

Hole concentration vs. DEZn pressure for Zn doping for temperature synchronized MLE.

Zinc doping of GaAs grown with temperature synchronized molecular layer epitaxy

AsH3 AsH3DEZn TEG

evacuation evacuation evacuation evacuation

time

Tem

per

ature

temperature synchronized molecular layer epitaxy

AA' - after arsine doping mode

precursor injection phases

360 380 400 420 440 4600

1

2

4

AA Mode

AA'Mode

IG Mode

undoped

10

10

10

17

18

19

2x

1x

1x

3

Substrate temperature during AsH3 injection [・C]

Ho

le c

on

centr

atio

n

[cm

-3]

Gro

wth

rat

e per

cycl

e [

・]

Growth rate and hole concentration vs. temperature during arsine injectionfor Zn doped GaAs grown with temperature synchronized MLE.

file: d:\0q\fig_s56s.cdr ZnTS.cdr

DOPING CHARACTERISTICS OF p-GaAs:Zn MLE

Page 12: Materials Science in Electronics devices - …denko/lecture/lecture/denshi...・ Material issue of semiconductor devices and fabrication process • Schematics of thin film growth

Doping mode dependences of impurity concentration evaluated by one-epitaxial run: base DETe doping.

Extremely high and steep impurity profile

Page 13: Materials Science in Electronics devices - …denko/lecture/lecture/denshi...・ Material issue of semiconductor devices and fabrication process • Schematics of thin film growth

▲Te DOPING

○Se DOPING

UP TO 1021cm-3 IMPURITY CONCENTRATION

5x1019cm-3 ELECTRON CONCENTRATION

Required for nm-channel Tr.

DOPING CHARACTERISTICS OF n-GaAs MLE

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DOPING CHARACTERISTICS OF p-GaAs:Be MLE

0 10 20 30 40 50 601018

1019

1020

1021

Be

co

nce

ntr

atio

n (c

m-3

)

Be(MeCp)2 injection time (sec)

●AA ■AG

UP TO 4x1020cm-3 IMPURITY CONCENTRATION

8x1019cm-3 HOLE CONCENTRATION

Required for nm-channel Tr.

Ohno T et. al.

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Ultra low c metal/semiconductor contact:

non-alloyed and selective CVD by W(CO)6

XTEM of MS interface with atomically

flat interface

Low-resistance Contacts with Chemical Vapor Deposited Tungsten on GaAs Grown by

Molecular Layer Epitaxy

[J. Electrochem. Soc., 146 (1), (1999), 131 - 136]

Yutaka Oyama, Piotr Plotka, Fumio Matsumoto, Toru Kurabayashi, H.hamano,

Hideyuki Kikuchi and Jun-ichi Nishizawa など

Page 16: Materials Science in Electronics devices - …denko/lecture/lecture/denshi...・ Material issue of semiconductor devices and fabrication process • Schematics of thin film growth

Contact resistivity for n-GaAs (MLE grown)

Also for p-GaAs (down to 10-8Wcm2 order)

Almost the limit of TLM method

Page 17: Materials Science in Electronics devices - …denko/lecture/lecture/denshi...・ Material issue of semiconductor devices and fabrication process • Schematics of thin film growth

High quality regrown interface

"Optimization of low temperature surface treatment of GaAs crystal",

J.Nishizawa, Y.Oyama, P.Plotka and H.Sakuraba,

Surface Science, 348, 105-114 (1996). など

Good interface

Page 18: Materials Science in Electronics devices - …denko/lecture/lecture/denshi...・ Material issue of semiconductor devices and fabrication process • Schematics of thin film growth

No trace of oxides and carbide after optimized

surface treatment

QMS desorption analysis

Also by XPS analysis

High quality regrown interface: chemical analysis

Page 19: Materials Science in Electronics devices - …denko/lecture/lecture/denshi...・ Material issue of semiconductor devices and fabrication process • Schematics of thin film growth

[110]

[11

0]

{001}

R

F

R

R

R

F

F

F

F

FF

F

R

R

R

R

F

F

F

F

F

F

F

F

TOP VIEW

Regrown p+-GaAs:Be 1st n+-GaAs:Te&S

epitaxy (49nm)

1st n+-GaAs:Te&S

epitaxy (49nm)

S.I.GaAs

Ti/Au non-alloyed

contact

Sidewall tunnel junctions

(regrowth interface)

Sidewall tunnel junction

(regrowth interface)

CROSS SECTIONAL VIEW

RF F

Figure 1. Schematic drawings of the cross sectional and top view of the fabricated sidewall

tunnel diodes. “F” and “R” mean the first epitaxial layers and the regrowth layers. The

arrows indicate the positions of sidewall regrown tunnel junctions. Large pad has 100mm

in length, and small one has 50mm.

Application of MLE GaAs to high quality

ultra-small tunnel junctions

Side-wall regrowth process

Application of low-temperature area-selective regrowth for ultrashallow sidewall GaAs tunnel junctions

Yutaka Oyama, Takeo Ohno, Kenji Tezuka, Ken Suto and Jun-ichi Nishizawa

Applied Physics Letters, 81, 2563-2565 (2002). など

Page 20: Materials Science in Electronics devices - …denko/lecture/lecture/denshi...・ Material issue of semiconductor devices and fabrication process • Schematics of thin film growth

Ti/Au

non-alloyed

contact

n+-GaAs:Te&S layer

(50nm)regrown p+-GaAs:Be layer

SI GaAs substrate

sidewall

tunnel junction (SJ~10-8cm2)

100 nm

1 mm

n+-GaAs:Te&S

p+-GaAs:Be

Application of MLE GaAs

to high quality ultra-small

tunnel junctions

Side-wall regrowth process

Page 21: Materials Science in Electronics devices - …denko/lecture/lecture/denshi...・ Material issue of semiconductor devices and fabrication process • Schematics of thin film growth

Figure 2. J-V

characteristics of GaAs

sidewall tunnel junctions at

290 and 77K on (a) normal

mesa, (b) 45° inclined

configuration and (c)

reverse mesa sidewall

orientations.

0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.70.0

5.0x103

1.0x104

1.5x104

2.0x104

2.5x104

3.0x104

3.5x104

290K

77K

NORMAL MESA ORIENTATION

Curr

ent

Den

sity

[A

cm-2]

Voltage Bias [volts]

0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.70.0

5.0x103

1.0x104

290K

77K

45° INCLINED

CONFIGURATION

Curr

ent

Den

sity

[A

cm-2]

Voltage bias [volts]

0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.70

1x103

2x103

3x103

4x103

5x103

290K

77KREVERSE MESA

ORIENTATION

Curr

ent

Den

sity

[A

cm-2]

Voltage Bias [volts]

Record high peak current density

Current-voltage characteristics of sidewall TUNNEL junctions

Sidewall mesa orientation dependences

Ohno T et. al.

Page 22: Materials Science in Electronics devices - …denko/lecture/lecture/denshi...・ Material issue of semiconductor devices and fabrication process • Schematics of thin film growth

(Jin, 2003)

● Our results:2002

GaAs tunnel diode (PVCR=28)

(Ahmed, 1997)

Figure of merits of fabricated TUNNEL junctions

RITD:

Resonant Interband Tunnel diode Ohno T et. al.

Page 23: Materials Science in Electronics devices - …denko/lecture/lecture/denshi...・ Material issue of semiconductor devices and fabrication process • Schematics of thin film growth

0 200 400 600 800 1000 1200 1400

1018

1019

1020

tunnel junction

(regrown p+-GaAs:Be/n

+-GaAs:Te&S interface)

epitaxial/substrate

interface

Be

S

Te

Impuri

ty c

oncentr

ati

on [

cm-3]

Depth from the surface [A]

Very high & steep impurity profile at tunnel junction interface

up to 2x1018cm-3 impurities /A Ohno T et. al.

Page 24: Materials Science in Electronics devices - …denko/lecture/lecture/denshi...・ Material issue of semiconductor devices and fabrication process • Schematics of thin film growth

Ultra fast and high frequency semiconductor electronic

and photonic devices

To be continued to next week