SAR Cyclic and Integrating ADCs

8/12/2019 SAR Cyclic and Integrating ADCs

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Department of Electrical and Computer Engineering

Vishal Saxena -1-

SAR, Algorithmic and IntegratingADCs

Vishal Saxena, Boise State University([email protected])


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Successive Approximation ADC


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Successive Approximation ADC

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Binary search algorithm N*Tclk to complete N bits

Conversion speed is limited by comparator, DAC, and digital logic

(successive approximation register or SAR)


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Binary Search Algorithm

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DAC output gradually approaches the input voltage

Comparator differential input gradually approaches zero


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Charge Redistribution SA ADC

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4-bit binary-weighted capacitor array DAC (aka charge scaling DAC)

Capacitor array samples input when 1 is asserted (bottom-plate)

Comparator acts as a zero crossing detector


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Charge Redistribution (MSB)

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R i Ri R X 4 X 3 2 1 0 X iV 8C- V 16C V

V 16C = V - V C - V C +C +C +C V - V16C 2

Start with C4 connected to VR and others to 0 (i.e. SAR=1000)


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Comparison (MSB)

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If VX < 0, then Vi > VR/2, and MSB = 1, C4 remains connected to VR

If VX > 0, then Vi < VR/2, and MSB = 0, C4 is switched to ground

X

iR

X V2

V V:TESTMSB


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Charge Redistribution (MSB1)

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R ii R X X X R iV 12C V 16C 3

V 16C V V 12C V 4C V V V16C 4

SAR=1100


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Comparison (MSB1)

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If VX < 0, then Vi > 3VR/4, and MSB-1 = 1, C3 remains connected to VR

If VX > 0, then Vi < 3VR/4, and MSB-1 = 0, C3 is switched to ground

X R i3

MSB -1 TEST : V V V4

X


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Charge Redistribution (Other Bits)

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Test completes when all four bits are determined w/ four charge

redistributions and comparisons

SAR=1010, and so on


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After Four Clock Cycles

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Usually, half Tclk is allocated for charge redistribution and half forcomparison + digital logic

VX always converges to 0 (Vos if comparator has nonzero offset)

X


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Summing-Node Parasitics

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If Vos = 0, CP has no effect eventually; otherwise, CP attenuates VX

Auto-zeroing can be applied to the comparator to reduce offset


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SAR ADC Summary

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High accuracy achievable (12+ Bits)

Low power and linear as no Opamp is required

Relies on highly accurate comparator

Moderate speed (10 MHz) Regaining interest in scaled CMOS processes


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SAR ADC Limitations

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Conversion rate typically limited by finite bandwidth of RC network

during sampling and bit-tests

For high resolution, the binary weighted capacitor array can becomequite largeE.g. 16-bit resolution, Ctotal~100pF for reasonable kT/C noise contribution

If matching is an issue, an even larger value may be needed

E.g. if matching dictates Cmin=10fF, then 216Cmin=655pF

Commonly used techniquesImplement "two-stage" or "multi-stage" capacitor network to reduce array

size [Yee, JSSC 8/79]

Split DAC or C-2C network

Calibrate capacitor array to obtain precision beyond raw technology

matching [Lee, JSSC 12/84]


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Algorithmic (Cyclic) ADC


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Essentially same as pipeline

But a single MDAC stage is used in a cyclic fashion for all operationsNeed many clock cycles per conversion


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Input is sampled first, then circulates in the loop for N clock cycles

Conversion takes N cycles with one bit resolved in each Tclk

Sample

mode


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Modified Binary Search

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If VX < VFS/2, then bj = 0, and Vo = 2*VX

If VX > VFS/2, then bj = 1, and Vo = 2*(VX-VFS/2)

Vo is called conversion residue

RA = residue amplifier

Conversionmode


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Modified Binary Search

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Constant threshold (VFS/2) is used for each comparison

Residue experiences 2X gain each time it circulates the loop

X

iFS

clk

FS


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Loop Transfer Function

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Comparison if VX < VFS/2, then bj = 0; otherwise, bj = 1

Residue generation Vo = 2*(VX - bj*VFS/2)

VX

Vo

VFS/20 VFS

VFSbj=0 bj=1


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Algorithmic ADC

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Hardware-efficient, but relatively low conversion speed (bit-per-step)

Modified binary search algorithm

Loop-gain (2X) requires the use of a residue amplifier, but greatly simplifies

theDAC 1-bit, inherently linear (why?)

Residue gets amplified in each circulation; the gain accumulated makes the

later conversion steps insensitive to circuit noise and distortion

Conversion errors (residue error due to comparator offset and/or loop-gain

non-idealities) made in earlier conversion cycles also get amplified againand again overall accuracy is usually limited by the MSB conversion step

Redundancy is often employed to tolerate comparator/loop offsets

Trimming/calibration/ratio-independent techniques are often used to treat

loop-gain error, nonlinearity, etc.


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Offset Errors

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Ideal RA offset CMP offset

Vo = 2*(Vi - bj*VFS/2) Vi = bj*VFS/2 + Vo/2

Vi

Vo

VFS/20 VFS

VFSb=0 b=1

Vi

Vo

VFS/20 VFS

VFSb=0 b=1

Vi

Vo

VFS/20 VFS

VFSb=0 b=1Vos

Vos

Vi

Do

VFS/20 VFS Vi

Do

VFS/20 VFS Vi

Do

VFS/20 VFS


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Redundancy (DEC, RSD)

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Vi

Vo

VFS/20 VFS

VFSbj=0 bj=1

VFS/2

Bj+1=0

Bj+1=1

Vi

Do

VFS/20 VFS00

01

10

11

Vi

Vo

VFS/20 VFS

VFSbj=0 bj=1

VFS/2

Bj+1=0

Bj+1=1

Bj+1=-1

Bj+1=2

Vi

Do

VFS/20 VFS00

01

10

11

1 CMP 3 CMPs

RSD= Redundant Signed Digit


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Loop Transfer Function

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Original w/ Redundancy

Subtraction/addition both required to compute final sum

4-level (2-bit) DAC required instead of 2-level (1-bit) DAC

Vi

Vo

VFS/20 VFS

VFSb=0 b=1

Vi

Vo

VFS/20 VFS

b=0 b=1b=-1 b=2


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Comparator Offset

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Max tolerance of

comparator offset isVFS/4 simple

comparators

Similar tolerance also

applies to RA offset

Key to understand

digital redundancy:

jo

o

i

j

FSVV = +

2b

2

V

V

b


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Modified 1-Bit Architecture

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1-b/s RA transfer curve

w/ no redundancy

One extra CMP

added at VR/2

0

VR/2

-VR/2

Vi

Vo

-VR/2 VR/2-VR

VR

VR

0

VR/2

-VR/2

Vi

-VR/2 VR/2-VR

VR

VR

b=0 b=1 b=0 b=1b=0.5


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From 1-Bit to 1.5-Bit Architecture

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-VR/4 VR/4

0

VR/2

-VR/2

Vi

-VR

VR

VR

b=0 b=1b=0.5

-VR/4 VR/4

0

VR/2

-VR/2

Vi

-VR

VR

VR

b=0 b=2b=1

Vo

A systematic offset VR/4

introduced to both CMPs

A 2X scaling is performed

on all output bits


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The 1.5-Bit Architecture

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3 decision levels

ENOB = log23 = 1.58

Max tolerance of comparator

offset is VR/4

An implementation of the

Sweeny-Robertson-Tocher

(SRT) division principle The conversion accuracy

solely relies on the loop-gain

error, i.e., the gain error and

nonlinearity

A 3-level DAC is required o i RV = 2 V - b -1 V


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The Multiplier DAC (MDAC)

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2X gain + 3-level DAC + subtraction all integrated A 3-level DAC is perfectly linear in fully-differential form

Can be generalized to n.5-b/stage architectures

Vo

Vi

0-VR

VR

Decoder

1 C1

1 C2

2

1e

A

2

-VR/4

VR/4

R1

2i

1

21o V

C

C1bV

C

CCV

o i RV = 2 V - b -1 V


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A Linear 3-Level DAC

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b = 0 b = 1 b = 2

Ri

TB

1

2i

1

21

ooo

VV2

VVC

CV

C

CCVVV

i

CMCM

1

2i

1

21

ooo

V2

VVC

CV

C

CCVVV

Ri

BT

1

2i

1

21

ooo

VV2

VVC

CV

C

CCVVV

Vo-

C1

C2

Vo+

C1

C2

AVT

VBVo-

C1

C2

Vo+

C1

C2

AVCM

VCM Vo-

C1

C2

Vo+

C1

C2

AVT

VB


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Alternative 1.5-Bit Architecture

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Ref: E. G. Soenen and R. L. Geiger, An architecture and an algorithm for fully digital

correction of monolithic pipelined ADCs, IEEE Trans. on Circuits and Systems II, vol.

42, issue 3, pp. 143-153, 1995.

-VR/2 VR/2

0Vi

-VR

VR

VR

b=0 b=2b=1

Vo

How does

this work?


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Error Mechanisms of RA

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Capacitor mismatch

Op-amp finite-gain error and

nonlinearity

Charge injection and clock

feedthrough (S/H)

Finite circuit bandwidth

o i RV = 2 V - b -1 V

1 2 2o S/H i R

1 2 1 21 1

o o

C C CV t f V b 1 V

C C C CC C

A V A V

Vo

Vi

0-VR

VR

Decoder

1 C1

1 C2

2

1e

A

2

-VR/4

VR/4


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RA Gain Error and Nonlinearity

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Raw accuracy is usually limited to 10-12 bits w/o error correction

R R

R

R

i

R

R

R

o

iR R

o


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Static Gain-Error Correction

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1 2 2o i R i R

1 2 1 21 1

1 2

C C CV V b V V -b V

C Cka ka

C CC C

A A

1 2

1 21

oi 2i o

R 1 2 R 1 2

C CC

VV CA b D = D + bV C C V C C

kd kd

Analog-domain method:

Digital-domain method:

Do we need to correct for kd2 error?


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RA Gain Trimming

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Precise gain-of-two is achieved by adjustment of the trim array

Finite-gain error of op-amp is also compensated (not nonlinearity)

C1/C2 = 1 nominally

1 2

o i1 2

1

2R

1 21

C CV V

C CC

A

C b 1 VC CC

A

Vo-

Vo+

i+

i-

X+

X-

12

12


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Split-Array Trimming DAC

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Successive approximation utilized to find the correct gain setting

Coupling cap is slightly increased to ensure segmental overlap

2C1.2C

8C4C2CC8C4C2CC

2C1.2C

8C4C2CC8C4C2CC

VX+

VX-

Vi+

Vi-

8-bit gain

1-bit sign


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Digital Radix Correction

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2 1

2 1 2 1

2 1

j j j+1

j j+1 j+2

2

j j+1 j+2

2 3

j j+1 j+2 j+3

2 3

j j+1 j+2

2 1

2 1 2 1 2 1

2 1 j+32 1 2 1 2

kd kdkd kd kd kd

kd kd kd kd

kd kd kd kd kd kd

kd kd kd kd

D = b + D= b + b + D

= b + b + D

= b + b + b + D

= b + b + bkd kd kd+ b +...

1 2

1 21

oi 2

i oR 1 2 R 1 2

C CC

VV CA b D = D + bV C C V C C

kd kd

Unroll this:


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Integrating ADC


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Si l Sl I i ADC


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Single-Slope Integration ADC

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INL depends on the linearity of the ramp signal

Precision capacitor (C), current source (I), and clock (Tclk) required

Comparator must handle wide input range of [0, VFS]

1i 1 o

clk

io

clk

clk

tIV = t , D =

C T

VD = ,

I T

CI T

LSB =C

D l Sl I t ti ADC


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Dual-Slope Integration ADC

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RC integrator replaces the I-C integrator

Input and reference voltages undergo the same signal path

Comparator only detects zero crossing

i

fclk

o

X

R

D l Sl I t ti ADC


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Dual-Slope Integration ADC

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Exact values of R, C, and Tclk are not required

Comparator offset doesnt matter (what about its delay?) Op-amp offset introduces gain error and offset (why?)

Op-amp nonlinearity introduces INL error

i Rm 1 2

i 2 2o

R 1 1

o 2 1

V VV = t = tRC RC

V t ND = = =

V t N

or D =N for fixed N

X 1 2

m

os

O A Off t


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Op-Amp Offset

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Vi = 0 Vi = VR

N2 0 Offset Longer integration time!

Vi

Do

0 VR

Actual

IdealDos

S b i D l Sl ADC


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Subranging Dual-Slope ADC

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MSB discharging stops at the immediate next integer count past Vt Much faster conversion speed compared to dual-slope

Two current sources (matched) and two comparators required

Vi

Control

Logic

SHA

Cnt 1

(8 bits) MSBs

VX

Cmp2

I

CS

I

256

Cmp1Vt

Cnt 2

(8 bits)LSBs

fclk Carry

Subranging Dual Slope ADC


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Precise Vt is not required if carry is propagated

Matching between the current sources is critical

if I1 = I, I2 = (1+)I/256, then || 0.5/256

Itd be nice if CMP 1 can be eliminated ZX detector!

X

X

dV 1 I,

dt CdV 2 I

dt 256C

21o NWND

X

1 2

t

Subranging Dual Slope ADC


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CMP 1 response time is not critical

Delay from CNT 1 to MSB current shut-off is not critical

constant delay results in an offset (why?)

CMP 2 response time is critical, but relaxed due to subranging


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Subranging Multi Slope ADC


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Subranging Multi-Slope ADC

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Single comparator detects zero-crossing

Comparator response time greatly relaxed

Matching between the current sources still critical

X

X

X

dV 1 I,

dt C

dV 2 I,

dt 16C

dV 3 I

dt 256C

32211o NWNWND

Subranging Multi Slope ADC


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Subranging Multi-Slope ADC

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Comparator response time is not critical except the last one

Delays from CNTs to current sources shut-off are not critical

constant delays only result in offsets

Last comparator response time is critical, but relaxed due to multi-

step subranging

References


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References

1. Rudy van de Plassche, CMOS Integrated Analog-to-Digital and Digital-to-AnalogConverters, 2nd Ed., Springer, 2005..

2. Y. Chiu, Data Converters Lecture Slides, UT Dallas 2012.

3. B. Boser,Analog-Digital Interface Circuits Lecture Slides, UC Berkeley 2011.

SAR Cyclic and Integrating ADCs

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