Reliability of LTPS TFTs TFTs... · 1 Reliability of LTPS TFTs Han-Wen Liu. Department of...

1

Reliability of LTPS TFTs

Han-Wen Liu

Department of Electrical Engineering &Graduate Institute of Optoelectric Engineering

National Chung Hsing University2010/05/27

2

Contents

Introduction of LTPS TFTs

Key processes of LTPS TFTs

Electrical characteristics of LTPS TFTs


3

Contents





4

Driver LSI& Control LSI

Driver LSI& Control LSI

Driver Circuit

RAM CPU ROM

Interface Pen Input

Conventional a-Si TFT-LCD

μ= 0.5~1

Poly-Si TFT-LCDwith Integrated Drivers

μ=50～200 cm2/Vs

System On Panel

μ= ~500 cm2/Vs

Flexible tapeControl LSI

Progress of Display

5

Advantages of LTPS TFTs

TFT LCD technology α-Si TFTs LTPS TFTs

Mobility (μ) ≦1 cm2/V-sec ≧100 cm2/V-sec

Integration of driving IC Gate driver

Gate & data driver

Aperture ratio(Open ratio) Low High

Main applications LCD TV, Monitor

Cell phone, Digital camera

6

Why we need LTPS TFTs ?

1. High Aperture Ratio2. High-speed operation3. Low power consumption4. Higher Ion /Ioff (>106)

From device view

7

Why we need LTPS TFTs ?

1. Reducing numbers of TAB package (Cost of Driver Circuit and Package)!

2. Reducing EMI (cross talk)!

From system view

8

Why we need LTPS TFTs?

3. Most important, integrating the driver onto glass!4. As mobility higher than 500 cm2/V-s, CPU can be

also integrated onto glass (System on panel)!

From system view (SOP)

9

Mechanism of Poor Properties in LTPS

10

Polycrystalline Si Structure

Small crystals (“crystallites” or “grains”) of Si atoms

Average lateral grain size can range from several nm to mm

depends on deposition, annealing conditions

Different crystalline orientations

discontinuity from one grain to another

The border between crystallites is called a “grain boundary”

contains disoriented bonds and dangling bonds

locally allowed energy stateswithin the Si bandgap

TEM of a Poly-Si Film

11

Poly-Si Density of States Distribution

Shallow “tail states” are associated with strained bonds

Deep states near mid-gap are associated with broken bonds

Deep state Tail state

Energy distribution

Gaussian distribution

exponential distribution

Origin Dangling bonds Strained bonds

Influences Vth, S.S.

12

Contents





13

LTPS TFTs Process Flow (I)1. Buffer-layer/ α-Si precursor2. Dehydrogenation

B-- B-- B-- B--

1. B11 doping of p-TFT channel doping

1. ELA crystallization

1. Poly-Si island pattern (Mask 1)

1. 31P+ for n-TFT channel doping (Mask 2)

P-- P-- P-- P--

1. Gate oxide dep., gate metal dep. & pattern (Mask 3)2. Densification / Hydrogenation

1. 31P+ for n-TFT LDD doping (blanket by gate self-aligned)P- P- P-P-

1. 31P+ for n-TFT S/D doping (Mask 4)P+ P+ P+P+

14

1. 11B- for p-TFT S/D doping (Mask 5)2. Activation

B+ B+ B+B+

1. Interlayer deposition 2. via hole (Mask 6 )

1. S/D deposition & pattern ( Mask 7)

1. Passivation (SiOx / SiNx/) deposition & pattern (Mask 8 )

1. ITO deposition & pattern (Mask 9)

LTPS TFTs Process Flow (II)

15

31 stage ring oscillator

10s 102s 103s 104s 105s 106s0

0.05

0.1Fr

eque

ncy

Var

iati

on, f

/fo

Operating Time

Data: Toshiba, Japan

Why LDD in LTPS TFTs ?

16

Crystallization of α-silicon

Solid Phase Crystallization: SPC

Metal Induced Crystallization: MICor Metal Induced Lateral Crystallization: MILC

Excimer Laser Annealing: ELA

17

Solid Phase Crystallization: SPC

Furnace annealing

Should be < 600 oC

Over several tens of hours (> 20 hrs.)

18

Metal Induced Crystallization: MIC

Ni, Pd, Au, Al

Silicide mediated, or Eutectic alloy

Lower the annealing temperature: < 550 oC

Few hours to ten of hours

Ex: Nickel Ni+2SiNiSi2 NiSi2 clusters migration throughout the α- Si region resulted in the crystallization of the α-Si

19

Metal-Induced Unilaterally Crystallized Poly-Si TFTs

Data: IEEE ED, Vol. 47, no. 2, Feb. 2000

20

Schematic Diagram of Scanning Mode ELA Process

21

I. Partial-melting regime (Low energy density)

Melt depth < film thickness

Explosive crystallization, vertical regrowth

Fine-grained and small-grained poly-SiExcimer laser irradiation

Oxide substrate

a-Si

Partially-melted Si RegrowthPolysilicon

Mechanism of Excimer Laser Crystallization (I)

22

II. Complete-melting regime (High energy density)

No unmelted Si remains

Deep supercooling followed by nucleation and

growth of solids

Excimer laser irradiation

Oxide substrate

Completely-melted Si

Homogeneousnucleation

Fine-grainpolysilicon

Mechanism of Excimer Laser Crystallization (II)

23

III. Near-complete-melting regime (Super-lateral growth)

Unmelted Si islands survive

Significant lateral growth proceeds before impingement

Excimer laser irradiation

Nearlycompletely-melted Si

Oxide substrate

Super lateral growth

Unmelted residual Siislands

Large-grainpolysilicon

Mechanism of Excimer Laser Crystallization (III)

24

Laser Crystallization of -Si Films

25

Defect Passivation in LTPS TFTs

26

Contents





27

LTPS TFTs Transfer Characteristics

28

Regions of LTPS TFTs Operation

Cut-off:

Current is due to reverse-bias drain junction leakage

trap-assisted mechanisms

Subthreshold:

Current is due to carrier diffusion

limited by source junction potential barrier

Pseudo-subthreshold:

Current is due to carrier drift

Inversion-charge density Qinv increases ~linearly with VG -Vt

meff increases ~exponentially with VG

ID increases ~exponentially with VG

Above threshold:

Current is due to carrier drift

Qinv

VG -Vt ; Under high Vg, meff ~constant or decrease with Vg due to surface scattering ID increases linearly with VG

29

Regions of LTPS TFTs Operation

30

Ioff at Various Applied Voltages

31

At low VG and VD (low field), IOFF is low and varies

almost linearly with the VD .

At higher field, IOFF varies almost exponentially

with VG and exhibits a dependency only on the

channel width. This suggesting that carriers are

being emitted from the drain space charge region.

Ioff at Various Applied Voltages

32

Model of Leakage Current

33

Kink Effect of LTPS TFTs

High drain electric field causes avalanche multiplication effect

34

Device Physics of Kink Effect

Step1: Electrons are accelerateddue to high electric field

Step2: Electrons and holes aregenerated due to impact-ionization

Step3: Holes move toward sourceStep4: Holes lower the source barrier

Some solutions:1. Using lightly doped drain (LDD) can reduce electric filed to have

lower impact ionization rate.2. Adding a body contact (double gate) can remove the accumulated

holes.

35

High Field Dimensional Effects

Drain Voltage VD ( V )0 1 2 3 4 5 6 7 8 9 10

I D x

L /

W ( A

)

05

1015202530354045505560

L = 1.5 mL = 20 m

N-channelW = 1.5 mTch = 100 nm

Severe kink effect for short channel devices

36

Trap-enhanced Kink Effect

Drain Voltage VD ( V )0 2 4 6 8 10 12 14

Unp

assi

vate

d D

evic

e D

rain

Cur

rent

I D (

A)

0

5

10

15

20

Pas

siva

ted

Dev

ice

Dra

in C

urre

nt I D

(A)

0

50

100

150

200

Before passivationAfter passivation

N-channelW / L = 10 m / 3 mTch = 100 nm

37

High Field Dimensional Effects

1. Impact ionization effects

Isub = ID x

x L

Impact ionization rate

:

]1exp[]exp[DsatD VVqE

qE

GateVDVS

VG

VDsat

DrainSource

e- e-h+

38

High Field Effects

2. Floating body effectselectron current (black line) and hole current (grey line)

S D

G

IiIC

Ich ID

BOX

VD

39

Effect of Parasitic BJT

40

Contents





41

Extremely serious in SOI and TFT.

Caused by high Joule heat and low power dissipation.

Power dissipation is related to:

substrate material

poly-Si thickness

design rule

Self Heating Effect

Data: S. Inoue et al. 2002 JJAP

42

-15 -10 -5 0 5 10 15 2010-1610-1510-1410-1310-1210-1110-1010-910-810-710-610-510-410-310-2

DC stress Vg=+18V Vd=+15VMeasured@ Vd=0.1V

initial 20s 200s 2000s

Id (A

)Vg (V)


Self Heating Effect

Under self heating stress, generally Ion and Gm,max decreasing, Ioff , Vth and S.S. increasing.

43

Self Heating Effect


Under self heating stress,

the severe degradation occurs at both high Vg and high Vd .

44

10 100 1000

-0.5

-0.4

-0.3

-0.2

-0.1

0.0

Measured@ Vd=0.1V DC Vg=+18V,Vd=+3V DC Vg=+18V,Vd=+6V DC Vg=+18V,Vd=+9V DC Vg=+18V,Vd=+12V DC Vg=+18V,Vd=+15V

Io

n/Io

n,0

Stress time (s)10 100 1000

0.0

0.5

1.0

1.5

2.0

2.5 Measured@ Vd=0.1V DC Vg=+18V,Vd=+3V DC Vg=+18V,Vd=+6V DC Vg=+18V,Vd=+9V DC Vg=+18V,Vd=+12V DC Vg=+18V,Vd=+15V

Vt

h

Stress time (s)

Self Heating Effect

Under Vg=+18V self heating stress, obvious Ion degradation as Vd over 9V and turn-around at Vd =9V.

Under Vg=+18V self heating stress, obvious Vth -shift as Vdover 9V.

45

Hot Carrier Effect


-15 -10 -5 0 5 10 15 2010-1610-1510-1410-1310-1210-1110-1010-910-810-710-610-510-410-310-2

DC stress Vg=+3V Vd=+18VMeasured@ Vd=0.1V

initial 20s 200s 2000s

Id (A

)Vg (V)

Under hot carrier stress, generally Ion and Gm,max decreasing, Ioff increasingVth and S.S. almost unchanged.

46

10 100 1000-0.75-0.70-0.65-0.60-0.55-0.50-0.45-0.40-0.35-0.30-0.25-0.20-0.15-0.10-0.050.00

Measured@ Vd=0.1V DC Vg=+3V,Vd=+3V DC Vg=+3V,Vd=+6V DC Vg=+3V,Vd=+9V DC Vg=+3V,Vd=+12V DC Vg=+3V,Vd=+15V

Io

n/Io

n,0

Stress time (s)10 100 1000

0.00

0.02

0.04

0.06

0.08

0.10

0.12 Measured@ Vd=0.1V DC Vg=+3V,Vd=+3V DC Vg=+3V,Vd=+6V DC Vg=+3V,Vd=+9V DC Vg=+3V,Vd=+12V DC Vg=+3V,Vd=+15V

Vt

hStress time (s)

Hot Carrier Effect

Under Vg=+3V hot carrier stress, obvious Ion degradation as Vd over 9V.

Under Vg=+3V hot carrier stress, the shift of Vth is small.

47

Self Heating vs Hot Carrier Effect


Region A: self heating effect, both high Vg and high Vd .

Region B: hot carrier effect, high Vd but low Vg .

48Data: S. Inoue et al. 2003 JJAP

(a) Self heating stressUnder Vg=25V, Vd=15V

(b) Hot carrier stressUnder Vg=5V, Vd=15V

(c) Stress at boundaryUnder Vg=12V, Vd=15V

Self Heating vs Hot Carrier Effect

49

Turn-around degradationN-type LTPS TFTs

Ion degradation Sampling current Id

10 100 1000 10000-0.18

-0.16

-0.14

-0.12

-0.10

-0.08

-0.06

-0.04

-0.02

DC stress Vg=+18V, Vs=0V Vd=+6V Vd=+7.5V Vd=+9V Vd=+10.5V

Io

n / I

on,0

Stress time(s)1 10 100 1000 10000 100000

0.000888

0.000890

0.000892

0.000894

0.000896

0.000898

0.000900

Dra

in c

urre

nt (A

)

Stress time (s)

Vg=+18V, Vd=+9VVs=0V

Data: H. W. Liu et al. accepted by JJAP

50

Turn-around degradationN-type LTPS TFTs

Gm,max degradation Vth degradation

10 100 1000 100000.0

0.1

0.2

0.3

0.4

0.5

0.6

0.7

0.8DC stress Vg=+18V, Vs=0V

Vd=+6V Vd=+7.5V Vd=+9V Vd=+10.5V

Vt

h

Stress time(s)10 100 1000 10000

-0.15

-0.10

-0.05

0.00

0.05

0.10

DC stress Vg=+18V, Vs=0V Vd=+6V Vd=+7.5V Vd=+9V Vd=+10.5V

G

m,m

ax/G

m,m

ax,0

Stress time(s)


51

Turn-around degradationDegradation mechanism

+18V+9V

Glass substrate

n+ n+e-

n- n-e-e-e-e-


52

Purpose of Dynamic Stress

Purpose of this workPurpose of this workPurpose of this workFor CMOS circuits, reliability of n-ch TFTs, p-ch TFTsis important. Degradation of n-ch TFTs, p-ch TFTs was evaluated using Dynamic stress.

In peripheral circuits, TFTs are driven by dynamic pulse of high voltage. In peripheral circuits, In peripheral circuits, TFTsTFTs are driven are driven by dynamic pulse of high voltage.by dynamic pulse of high voltage.

poly-Si panel

CMOS

53

TFT

Dynamic StressDynamic Stress

T r T fT＝1/f

High

Low

Conditions of Dynamic Stress

Vg=Vg=--1515~+~+1515 VV

FFreq.req.== 0.5Hz~5000.5Hz~500 kHzkHz

DutyDuty ratioratio== 50%50%

TTrr，，TTff == 10~20010~200 nsecnsec

Gate

Stress

Ｓ D

54

Degradation of n-ch TFTs

Mobility、ON current decreased.OFF current increased.

Data: Y.Uraoka et al, ICMTS 2000

Log ScaleLinear Scale

-10 0 10 20

0

5

10

15

[x10-5 ]

Dra

in C

urre

nt (A

)

Gate Voltage (V)

initial1sec10sec100sec1000sec

-10 0 10 20

10-10

10-5

0

20

40

60

Dra

in C

urre

nt (A

)

Gate Voltage (V)

Mob

ility

(cm

2 /V

s)

initial1sec10sec100sec1000sec

55

Frequency Dependence

10-1 100 101 102 103

0.4

0.6

0.8

1

500kHz50kHz5kHz0.5kHz

Stress Time (sec)

u　/u

0

Frequency:0.5kHz～ Repetition Time Dependence

Less mobility degradation with decreasing frequency

Mobility degradationdepended on repetition time .Mobility Mobility degradationdegradationdepended on repetition time .depended on repetition time .

Universal curveUUniversal curveniversal curve

0.3

0.4

0.5

0.6

0.7

0.8

0.9

1

1.1

102

104

106

108

0.5kHz5kHZ50kHz500kHz

u　/u　 0

Number of Repetition


56

Rising ＆ Falling Time

10-1 100 101 102 103

0.7

0.8

0.9

1

10nesc20nsec50nsec100nsec200nsec

Stress Time (sec)u　/u　 0

10-1 100 101 102 1030.6

0.7

0.8

0.9

1

u　/u　 0

Stress Time (sec)

20nsec50nsec100nsec200nsec

Pulse Rising Time (Tr ) Pulse Fall Time (Tf )

Tr Tｆ

Mobility decrease was accelerated by pulse falling time.


57

DC stressVg=5V,Vd=15V

Dynamic StressVg= -15~+15V, freq.= 500KHz

Gate Metal

Source

Drain

Gate Metal

Drain

Source

Photon Emission of Stressed TFTs

Photon emission was also observed in n-ch TFTs during dynamic operation.


58

Degradation Model of Dynamic Stress

Falling time of pulse stress

+15→-15V

0V 0V

-15V

0V 0V

+15V

0V0VChannelChannel

n-ch TFT →

n-ch TFT →

ON →

LowLow

HighHigh

HighHigh→→LowLowHot carriers aregenerated.

Electron trapswere generated.

Electron are accumulated.


59

＋15→-15V

0V 0V

+ 15→-15V

0V 0V

More DAHC are generated.

+15V

Vth

Low electric field

High electric field

Tf

-15V

Tf+15V

Vth

Low electric field

High electric field-15V

Degradation Model of Dynamic Stress

60

Hot Carrier by Emission Microscope

Falling Time Dependence

TTff == 100nsec100nsec

TTff == 200nsec200nsec

Source

Source

Drain

Drain

Gate Metal

Gate Metal 0 100 200 300 400 500 6000.15

0.2

0.25

0.3

0.35

0.4

0.45

0

1

2

3

[10+4]

μ/μ

0

Falling Time (nsec)

Tr=100nsec

Inte

nsity

(a.u

)


61

Reliability of AC Stress

Ion degradation:(-18V~+18V) > (-18V~0V) >> (0V~+18V)

(OFF ~ON) > (OFF state) >> (ON state)

10 100 1000-0.8

-0.7

-0.6

-0.5

-0.4

-0.3

-0.2

-0.1

0.0

AC 500kHz, Tr=Tf=100nsVd=Vs=0V

Vg=-18~+18V Vg=0~+18V Vg=-18~0V

Ion

/ Ion

,0

Stress time (s)

Data: H. W. Liu et al. accepted by 217th ECS Meeting

62

Reliability of AC Stress

Gm,max degradation:(-18V~+18V) > (-18V~0V) >> (0V~+18V)

(OFF ~ON) > (OFF state) >> (ON state)

10 100 1000-0.8

-0.7

-0.6

-0.5

-0.4

-0.3

-0.2

-0.1

0.0

AC 500kHz, Tr=Tf=100nsVd=Vs=0V

Vg=-18~+18V Vg=0~+18V Vg=-18~0V

G

m,m

ax/G

m,m

ax,0

Stress time (s)


63

Degradation of OFF State AC Stress

10 100 1000-0.8

-0.7

-0.6

-0.5

-0.4

-0.3

-0.2

-0.1

0.0

0.1

G

m,m

ax/G

m,m

ax,0

Stress time (s)

Vg=-18~0V, Tr=Tf=5nsVd=0V, Vs=ground

10kHz 100kHz 500kHz 1MHz

105 106 107 108 109 1010 1011-0.8

-0.7

-0.6

-0.5

-0.4

-0.3

-0.2

-0.1

0.0


10kHz 100kHz 1MHz 10MHz

G

m,m

ax/G

m,m

ax,0

Number of Repetitions

Frequency dependence & universal curve

Gm,max degradation


64


10 100 1000-0.7

-0.6

-0.5

-0.4

-0.3

-0.2

-0.1

0.0

Io

n / I

on,0

Stress time (s)


10kHz 100kHz 500kHz 1MHz

105 106 107 108 109 1010 1011-0.8

-0.7

-0.6

-0.5

-0.4

-0.3

-0.2

-0.1

0.0


10kHz 100kHz 1MHz 10MHz

Io

n / I

on,0

Number of Repetitions

Frequency dependence & universal curve

Ion degradation


65


0 200 400 600 800 10000.0

2.0x10-104.0x10-106.0x10-108.0x10-101.0x10-91.2x10-91.4x10-91.6x10-91.8x10-92.0x10-9


10kHz 100kHz 500kHz

Sam

plin

g C

urre

nt I d

(A)

Stress time (s)

0 200 400 600 800 1000-2.0x10-9-1.8x10-9-1.6x10-9-1.4x10-9-1.2x10-9-1.0x10-9

-8.0x10-10-6.0x10-10-4.0x10-10-2.0x10-10

0.0


10kHz 100kHz 500kHz

Sam

plin

g C

urre

nt I s

(A)

Stress time (s)

Sampling current Id & Is under AC stress


66


Degradation of Cgd & Cgs

0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0

0.0

0.2

0.4

0.6

0.8

1.0

N

orm

aliz

ed C

gd o

r Cgs

Vg (V)

Stressed @ 500kHz, Tr=Tf=5ns Vg=-18~0V, Vd=Vs=0V

Measured @ 1MHz

Solid mark: CgdOpen mark: Cgs

initial

stress 1000s

stress 4000s


67


Degradation of forward & reverse Id -Vg

0 3 6 9 12 150.0000

0.0001

0.0002

0.0003

0.0004

0.0005

0.0006

0.0007

0.0008

I d

(A)

Vg (V)

Stress @ 500 kHz, Tr=Tf=5nsVg=-18~0V, Vd=0V, Vs=ground

Measured @ Vd=10V, saturation initial_forward initial_reverse 2000s stress_forward 2000 stress_reverse


68

DrainSource

Vg=-18~0V (OFF State)Gate

Id > 0

e- e-

n p nReverse bias

Forward bias

Degradation region

Vs=0V Vd=0V

Proposed Degradation Model


69

Gm,max degradation


Dependent on Tr rather than Tf

10 100 1000

-0.40

-0.35

-0.30

-0.25

-0.20

-0.15

-0.10

-0.05

0.00

0.05

G

m,m

ax/G

m,m

ax,0

Stress time (s)

100kHz, Vg=-18~0V, Vd=0V, Vs=ground

Tr=Tf=5ns Tr=Tf=50ns Tr=Tf=300ns Tr=5ns,Tf=300ns Tr=300ns,Tf=5ns


70

Ion degradation


Dependent on Tr rather than Tf

10 100 1000-0.35

-0.30

-0.25

-0.20

-0.15

-0.10

-0.05

0.00

0.05

100kHz, Vg=-18~0V, Vd=0V, Vs=ground

Tr=Tf=5ns Tr=Tf=50ns Tr=Tf=300ns Tr=5ns,Tf=300ns Tr=300ns,Tf=5ns

Io

n / I

on,0

Stress time (s)


71

AC Vg

-18V

S

G

D

n+ n+

0V

h+ h+ h+ h+ h+ h+ h+

h+ h+ h+ h+ h+ h+ h+h+ h+ h+ h+ h+ h+ h+h+

h+h+h+

h+h+n+ n+

Degradation Model of OFF State AC Stress

72

Thanks for your attention!Thanks for your attention!

Reliability of LTPS TFTsContentsContents投影片編號 4Advantages of LTPS TFTsWhy we need LTPS TFTs ?Why we need LTPS TFTs ?Why we need LTPS TFTs?Mechanism of Poor Properties in LTPSPolycrystalline Si StructurePoly-Si Density of States DistributionContents投影片編號 13投影片編號 14投影片編號 15Crystallization of α-siliconSolid Phase Crystallization: SPCMetal Induced Crystallization: MIC投影片編號 19投影片編號 20投影片編號 21投影片編號 22投影片編號 23投影片編號 24投影片編號 25Contents投影片編號 27投影片編號 28投影片編號 29投影片編號 30投影片編號 31投影片編號 32投影片編號 33Device Physics of Kink Effect High Field Dimensional Effects投影片編號 36High Field Dimensional EffectsHigh Field EffectsEffect of Parasitic BJTContents投影片編號 41投影片編號 42投影片編號 43投影片編號 44投影片編號 45投影片編號 46投影片編號 47投影片編號 48Turn-around degradationTurn-around degradationTurn-around degradation投影片編號 52投影片編號 53投影片編號 54投影片編號 55投影片編號 56投影片編號 57投影片編號 58投影片編號 59投影片編號 60Reliability of AC StressReliability of AC Stress投影片編號 63投影片編號 64投影片編號 65投影片編號 66投影片編號 67Proposed Degradation Model投影片編號 69投影片編號 70投影片編號 71投影片編號 72

Reliability of LTPS TFTs TFTs... · 1 Reliability of LTPS TFTs Han-Wen Liu. Department of...

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