Presented By: Rodney FluhartyDec. 07, 2000

Who is ARM?Who is ARM?

• Advanced Risc Microprocessor is the industry's leading provider of 16/32-bit embedded RISC microprocessor solutions.

• Licenses their high-performance, power-efficient RISC processors, peripherals, and system-chip designs to leading international electronics companies.

Who uses ARM technology?

Atmel, Cirrus Logic (www.cirrus.com), Fujitsu, Mitel (www.mitel.com), IBM, LG Semicon (www.lgsemicon.co.kr/), LSI Logic, Lucent Technologies (www.lucent.com), National Semiconductor, NEC, Oki, Samsung, Seiko Epson (www.epson.co.jp/), Sharp, Texas Instruments, Toshiba, and VLSI.

Why Don’t I see “ARM” chips?

• They are sold as VC (virtual components) and IP (intellectual property).

• Their designs are embedded and only the technology is ARM’s.

• Much cheaper to use existing technology.

Brief Overview of ARM 940T• Member of ARM 9 family.

• Complete CPU subsystem (Bus, Cache, Core)

• Harvard Architecture: Separate Data and Instruction Memory.

• 31 general-purpose registers with 16 simultaneously visible.

• Core is a 32-bit RISC processor.

• Do not support Virtual Addressing.

Core Block DiagramCore Block Diagram

Microprocessor Block DiagramMicroprocessor Block Diagram

Number CrunchingNumber Crunching

• Single-cycle 16X32-bit multiply-accumulate (MAC) unit

• Integer based only.

• Floating point would require a co-processor.

• Lack Integer divides (must synthesize division)

Bus Architecture/Clocking Bus Architecture/Clocking MethodologiesMethodologies

• Separate data/instruction busses.

• Two clock inputs (BCLK, FCLK).

3 Modes of clocking:

• FastBus: Used with high speed memory;• BCLK controls ARM91TDMI, cache ops, AMBA

Bus.

• FCLK ignored.

• Synchronous - Used for low-speed memory; both clock inputs used.

• BCLK controls bus

• FCLK controls core, cache.– Rules for Synchronous

» FCLK > BCLK

» BCLK transition must occur when FCLK high.

• Asynchronous - Used for low-speed memory; both clock inputs used.

• BCLK controls bus

• FCLK controls core, cache.– Rules for Synchronous

» FCLK > BCLK

Cache DescriptionCache Description

• Instruction/Data Cache = 4Kb

• 8 word write buffer

• Each cache comprises four, fully-associative 1kb segments.

• Single-cycle reads, one/two cycle writes (depending on sequence of instructions).

Cache Description ContinuedCache Description Continued

•Implements “Read-on-miss replacement” policy.

•Selection by randomly clocked rows (unless locked).

•Can use “Write-back” or “Write-through”

•Implement both “Valid” and “Dirty” bits.

Cache ArchitectureCache Architecture

PipeliningPipelining• 5 Stage pipeline (fetch, decode, execute,

memory, write-back).

• Implements bubble insertion.

Introduction to ThumbIntroduction to Thumb

• Why waste memory on instructions if not necessary?

• 16 bit subset of the 32 bit instruction set.

• Thumb module located in pipeline.

• Decompresses 16 bit instruction to 32 bit equivalent with no delays.

• Up to 30% code density improvement.

A Closer LookA Closer Look

How much does this affect?How much does this affect?

• 36 of the ARM’s native instructions have been adapted to Thumb technology.

• These did not benefit from the full 32 bit instruction.

Jazelle TechnologyJazelle Technology• Java was developed for embedded systems, so it

makes sense to optomize an embedded processor for Java!

• Historically:– Java source code is converted to a Java byte code.– Machine had to convert byte code to instructions at

execution time.– This can be very slow on low-power embedded

hardware (cell phones, set-top boxes, handhelds).

Wake me up when it’s loaded...Wake me up when it’s loaded...

• Original hardware solutions involved costly external co-processors.

• ARM’s solution: Add one more instruction and about 12,000 gates to the decode.

• Enter ‘BXJ Rm’ and the ARM goes into Java mode eliminating the slower JVM

• Certain registers are re-assigned to Java.• Still ARM and Thumb compatible.

Let the numbers speakLet the numbers speak

ConclusionConclusion

• ARM continues to produce high quality, embedded processors.

• ARM has developed new technologies to optomize hardware.

• Newer products such as the ARM10 or StrongARM (@600MHz) will likely appear in everyday life.