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CPU

Main

Memory

Five Components of a Computer

Output

Devices

Input

Devices

Secondary

Memory

display screen,

printer

keyboard,

mouse

harddisks, floppy disks,

tapes, CD-ROMs

CPU - Central Processing Unit fetches and follows a set of simple

instructions

Main Memory stores the executing program and its data in RAM

( random access memory )

Secondary Memory stores permanent records ( files )



Two Principal Microcomputer System Components

•Hardware

• Software

Microprocessor

(CPU)I/O System

Memory

System

BUS BUS

Random Access Memory (RAM)

Dynamic, Static

Cache, Flash Memory

Read Only Memory (ROM)

8088/8086

80286, 80386

80486, Pentium

Printer, Mouse, DVD

Floppy/Hard Disk

CD, USB, keyboard

Monitor, Tape Backup

Hardware: Architecture of a computer - general layout of majorComponents



System Block Diagram

System bus (data, address & control signals)

Memory

Interrupt circuitrySerial I/OParallel I/O

Timing CPU

µ P +

associated

logiccircuitry:

•Bus controller

•Bus drivers

•Coprocessor

•ROM (Read Only Memory) (start-up

program)

•RAM (Random Access Memory)

•DRAM (Dynamic RAM) - high capacity,refresh needed

•SRAM (Static RAM) - low power, fast,

easy to interface

•Crystal oscillator

•Timing circuitry

(counters dividing tolower frequencies)

At external unexpected events, µ P

has to interrupt the main program

execution, service the interrupt

request (obviously a short

subroutine) and retake the main

program from the point where itwas interrupt.

Simple (only two wires

+ ground) but slow.•Printer (low resolution)

•Modem

•Operator’s console

•Mainframe•Personal computer

Many wires, fast.

•Printer (high resolution)

•External memory

•Floppy Disk

•Hard Disk

•Compact Disk •Other high speed devices



The Personal Computer

Processor(8086 / 8088

trough

Pentium)

System bus (data, address & control signals)

System

ROM

Interrupt

logic (8259)

Keyboard

logic (8253)

DMA

Controller

(8237)

Timer

logic

(8253)

Coprocessor(8087

trough

80387)

640KB

DRAM

Expansion

logic

Keyboard

Speaker

Extension slots

Video cardDisk controller

Serial port

...



CPU performs the fetch/decode/execute cycle

Fetch: Control Unit fetches next instruction

Decode: Control Unit decodes instruction

Execute: instruction is executed by appropriate component

ALU

Control

Unit

Parts of the Central Processing Unit

Instruction

(Input)

ALU – Arithmetic and Logic Unit performs mathematical operations

Control Unit coordinates all of the computer’s operations

Result

(Output)

CPU



High-level languages: designed to be easy for

humans to read and to write programs in, but too

complicated for the computer to understand

Z = X + Y

Low-level languages: consist of simple instructions

which can be understood by the computer after aminor translation

ADD X Y Z

Machine Language: written in the form of zeros and

ones, can be understood directly by the computer

0110 1001 1010 1011



Evolution of Microprocessors

Computers “generations”• First generation ENIAC (vacuum tubes)• Second generation (transistors)• Third generation (IC - SSI, MSI)• Fourth generation (LSI)

• Fifth generation can think?

Microprocessors

MSI Intel® 4004™, 8008™

LSI Intel® 8080™, Zilog® Z80™, Motorola® 6800™

• 8 bit data bus, 16 bit address bus (64kbyte=65536 byte of • addressable memory), no multiply and divide instructions

•

VLSI 32…64 bit data bus, 2-300MHz clock, RISC concept



Hardware Terms & Functionality

• CPU: Performs all arithmetic & logical operations

• Memory: Used to store programs & data. Is divided into

individual components called addresses

• Input/Output (I/O) devices: allow communication with the

“real” world• Mass storage: means of permanently storing programs

and/or data

• System bus: Means by which other components

communicate. Busses are grouped into three categories:

– Data lines: for transmitting data – Address lines: indicate where information is sent to/from

– Control lines: regulate activity on the bus



In more detail, the architecture may look like the following:

CPUBus

Control

Timing

Memory

Module

MemoryModule

I/O

Module

I/O

Module

Mass

Storage

Keyboard



Interfaces frequently implemented in a microcomputer system.

Data

Communication

Control

Mass

Storage

Control

Bus

SupportROM

Static

RAM

Memory

Control

Display

Control

Keyboard

Control

Hard Copy

Control

Other

Device

Dynamic

RAM

PrinterKeyboardDisplay

To

Processor

ToM

assStorage



The 8086: the first 80x86 Machine8086 8088 80286 80386 80486 Pentium

Gen. p. Reg. 8/16bit 8/16bit 8/16bit 8/16/32bit 8/16/32bit 8/16/32bit

Data BUS 16 8 16 32 32 64

Address BUS 20 20 24 32 32 32Mem. Space 1MB 1MB 16MB 4GB 4GB 4GB

Modes

Coprocessor 8087 8087 80287 80387 Internal Internal (80-bit)

Multitasking

Virtual mem. 1GB 64TB 64TB

Virtual address.

Internal cache 8KB 8KB data / 8KB instruction

Arhitecture CISC/RISC

ALU Pipeline2 (two integer opp. or onefloating point at a time)

BUS Pipeline two BUS cycles at a time

Burst R/W 32 bytes

Prefetch Buffer

32 bytes read at once from

cache

Branch prediction (i.e.

CALL)

Real/Protected

Memory Menagement & Protection /

Integrated Memory Menagement

adrress unit, segment descriptors, gate descriptors

Machine Status Word

Page Fault Liniar Address

Controll Reg. Page Directory Base Add.

CISC=Complex Instruction Set Computer

Real



Evolution of the Intel Processors

8080 8051 80186 80386ex

8086/88 80286 80386 80486 Pentium

Embedded Microprocessors/Microcontrollers

General Purpose Microprocessors

8086/88

8028680386

80486Pentium Code and System

Level Compatability

Pentium II



The 8086: the first 80x86 Machine8088 and 8086 pin assignments

GND

A14A13

A12

A11

A10

A9

A8AD7

AD6

AD5

AD4

AD3

AD2

AD1

AD0

NMI

INTR

CLK

GND

Vcc

A15A16/S3

A17/S4

A18/S5

A19/S6

SS0 (HIGH)

MN/MXRD

HOLD (RQ/GT0)

HLDA (RQ/GT1)

WR (LOCK)

IO/M (S2)

DT/R (SI)

DEN (S0)

ALE (QS0)

INTA (QS1)

TEST

READY

RESET

1 40

8088

20 21

GND

AD14AD13

AD12

AD11

AD10

AD9

AD8AD7

AD6

AD5

AD4

AD3

AD2

AD1

AD0

NMI

INTR

CLK

GND

Vcc

AD15A16/S3

A17/S4

A18/S5

A19/S6

BHE/S7

MN/MXRD

HOLD (RQ/GT0)

HLDA (RQ/GT1)

WR (LOCK)

IO/M (S2)

DT/R (SI)

DEN (S0)

ALE (QS0)

INTA (QS1)

TEST

READY

RESET

1 40

8086

20 21



Typical Microprocessor Memory System

CPU Memory

Control

Address

Data



8086 / 8088 Memory Interface

• Address Bus

– 20 address lines so a 220 byte address space

– Pins A0-A19 provide the address

– For 8086, A0-A15 appear multiplexed with D0-D15 to form AD0-

AD15

– For 8088, A0-A7 appear multiplexed with D0-D7 to form AD0-AD7

• Data Bus

– For 8086, 16 bit data bus D0-D15 (multiplexed as AD0-AD15)

– For 8088, 8 bit data bus D0-D7 (multiplexed as AD0-AD7)

– 8086 may use only D0-D7 or D8-D15 if appropriate

• Control Bus – For memory access, the following pins are used:

– RD’, WR’, M/IO’, DT/R’, DEN’, ALE, BHE’



General Architecture of the

8088/8086 Processors

Segment

Registers

Instruction

Pointer

Address

Generation and

Bus Control

Instruction

Queue

BUS

General

Registers

Operands

ALU

Flags



Real mode and Protected mode

operation

Addressable memory:

8086 20 address lines => 1MB (Mega Byte)

•

•

•Pentium 32 address lines => 4096MB

For compatibility, all the 80x86 family members start running in “Real

Mode”, emulating the 8086 features (i.e. 1MB RAM)

Beginning with 80286, the “Protected Mode” is also available, allowing direct

control of all address lines (all addressable memory), multitasking support,

virtual memory addressing, memory management and protection (against

violation from other task), control over internal data and instruction cache.



Addresses

• Memory locations are comprised of groups of bits.

– 8 bits: 1 byte

– 16 bits: 1 word

– 32 bits: 1 double word

– 64 bits: 1 quad word

• Each byte has an associated address. Addresses are

comprised of groups of bits.

• The set of all possible address bit combinations is called the

ADDRESS SPACE.



IP

SP

FLAGS

The Software Model of 80x86 Family

AH AL

BH BL

CH CL

DH DL

A X

B X

C X

D X

B P

S I

D I

EAX

EBX

ECX

EDX

EBP

ESI

ED I

15 . . . 8,7 . . . 0 15 . . . 8,7 . . . 0 31 . . . . . . 16,15 . . . 8,7 . . . 0

32 bit registers,

80386 or higher only

A X

B X

C X

D X

B P

S I

D I

A H A L

B H B L

C H C L

D H D L

Accumulator

Base

CountData

Base Pointer

Source Index

Destination Index

8 bit registers 16 bit registers

CS

DS

SS

ES

IP

S P

F L A G S

EIP

ESP

EFLAGS

Code Segment

Data Segment

Stack Segment

Extra Segment

Instruction Pointer

Stack Pointer

Flags

Extended registers, only on

80386 and higher CPUs

FS

GS



A X

B X

C X

D X

B P

S I

D I

Processor Registers

A000 +

5F00

A5F00

Shift

to left

4 bits

Add

Effective

Address

(20bits)

16 bit

16 bit

Segment = a 64kbyte memory block

beginning at a multiple by 10Haddress.

An effective address is generated as

combination between a segment

register and another register as in

the example.Each segment register has a default usage

(class of instructions where apply).

Multiply, divide, accessing I/O...

Counter in loop operations

Multiply, divide, pointer to I/O...

Source index in string operations...

Destination index in string operatio

Pointer in program flow

Pointer in Stack

Control and status flags

A prefix (66H) allows

using 32 bit registers in

the real mode:

db 66h

;EAX instead AX

mov ax,1140h

;less significant 16 bits

db 058bh

;most significant 16 bits

15 . . . 8,7 . . . 0

16 bit registers

CS

DS

SS

ES

IP

SP

FLAGS

FS

GS

Accumulator

Base

Count

Data

Base Pointer

Source Index

Destination Index

Code Segment

Data Segment

Stack Segment

Extra Segment

Instruction Pointer

Stack Pointer

Flags



Flag register

1 5 1 4 1 3 1 2 1 1 1 0 9 8 7 6 5 4 3 2 1 0

- N T O F D F IF T F S F Z F - A F - P F - C FI O P L

CF

PF

AF

ZF

SF

TF

IF

DF

OF

IOPL

NT

Carry Flag

Parity Flag

Auxiliary carry Flag

Zero Flag

Sign Flag

Trace Flag

Interrupt enable Flag

Direction Flag

Overflow Flag

I/O Priority Level

Nested Task

Contains Carry out of MSB of result

Indicates if result has even parity

Contains Carry out of bit 3 in AL

Indicates if result equals zero

Indicates if result is negative

Provides a single step capability for debugging

Enables/disables interrupts

Controls pointer updating during string operations

Indicates that an overflow occurred in result

Priority level of current task (two bits)

Indicates if current task is nested



I t ti t



Instruction typesData transfer instructions

8086 instruction setIN Input byte or word from port

LAHF Load AH from flagsLDS Load pointer using data segment

LEA Load effective address

LES Load pointer using extra segment

MOV Move to/from register/memory

OUT Output byte or word to port

POP Pop word off stack

POPF Pop flags off stack

PUSH Push word onto stack

PUSHF Push flags onto stack

SAHF Store AH into flags

XCHG Exchange byte or word

XLAT Translate byte

Additional 80286 instructionsINS Input string from port

OUTS Output string to port

POPA Pop all registers

PUSHA Push all registers

Additional 80386 instructionsLFS Load pointer using FS

LGS Load pointer using GS

LSS Load pointer using SS

MOVSX Move with sign extended

MOVZX Move with zero extended

POPAD Pop all double (32 bit) registers

POPD Pop double register

POPFD Pop double flag register

PUSHAD Push all double registers

PUSHD Push double register

PUSHFD Push double flag register

Additional 80486 instructionBSWAP Byte swap

Additional Pentium instruction

MOV Move to/from control register

Instruction types



Instruction typesArithmetic instructions

8086 instruction setAAA ASCII adjust for addition

AAD ASCII adjust for divisionAAM ASCII adjust for multiply

AAS ASCII adjust for subtraction

ADC Add byte or word plus carry

ADD Add byte or word

CBW Convert byte or word

CMP Compare byte or wordCWD Convert word to double-word

DAA Decimal adjust for addition

DAS Decimal adjust for subtraction

DEC Decrement byte or word by one

DIV Divide byte or word

IDIV Integer divide byte or wordIMUL Integer multiply byte or word

INC Increment byte or word by one

MUL Multiply byte or word (unsigned)

NEG Negate byte or word

SBB Subtract byte or word and carry (borrow)

SUB Subtract byte or word

Additional 80386 instructionsCDQ Convert double-word to

quad-wordCWDE Convert word to double-word

Additional 80486 instructionsCMPXCHG Compare and exchange

XADD Exchange and add

Additional Pentium instructionCMPXCHG8B Compare and

exchange 8 bytes

Instruction types



Instruction typesBit manipulation instructions

8086 instruction set

AND Logical AND of byte or wordNOT Logical NOT of byte or word

OR Logical OR of byte or word

RCL Rotate left trough carry byte or word

RCR Rotate right trough carry byte or word

ROL Rotate left byte or word

ROR Rotate right byte or wordSAL Arithmetic shift left byte or word

SAR Arithmetic shift right byte or word

SHL Logical shift left byte or word

SHR Logical shift right byte or word

TEST Test byte or word

XOR Logical exclusive-OR of byte or word

Additional 80386 instructions

BSF Bit scan forwardBSR Bit scan reverse

BT Bit test

BTC Bit test and complement

BTR Bit test and reset

BTS Bit test and set

SETcc Set byte on conditionSHLD Shift left double precision

SHRD Shift right double precision



Instruction typesString instructions

8086 instruction set

CMPS Compare byte or word stringLODS Load byte or word string

MOVS Move byte or word string

MOVSB(MOVSW) Move byte string (word string)

REP Repeat

REPE (REPZ) Repeat while equal (zero)

REPNE (REPNZ) Repeat while not equal (not zero)SCAS Scan byte or word string

STOS Store byte or word string

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