PLO-2000.pdf - Microwave...
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PLO-2000 Series Phase Locked Dielectric Resonator Oscillator (PLDRO) utilizes state of the art MIC to provide highly stable, reliable and efficient signal source at microwave frequencies up to 50 GHz. The low profile and rugged construction provide excellent durability against harsh environmental conditions. PLO-2000 oscillator is designed using FET or BJT amplifier with series feed back at source and Dielectric Resonator at the gate. High gain, low-noise FETs/BJTs are biased positively or negatively at the gate to ensure minimum phase-noise. The devise is carefully matched for maximam power, minimum phase-noise and Voltage Standing Wave Ratio (VSWR). The oscillator is matched for maximum temperature stability and optimum negative resistance. PLO-2000 oscillator is buffered by cascaded low-noise driver and power amplifiers for minimum load pulling, maximum isolation and power. FET/BJT devices are directly attached to gold plated Kovar carriers to minimize shear effect and maximize heat sinking. Kovar carriers are mounted to the chassis to provide an efficient thermal junction and a stable structure for reduction of microphonics. To ensure oscillator stability over the full temperature range, the tuning elements are precisely designed and positioned to compensate for temperature drift by a factor of three. PLO-2000 series proprietary phase lock loop circuitry is surface mounted on thick film Alumina substrate. The reference frequency is multiplied and sampled to output frequency. Produced error voltage due to frequency drift is sensed by a Wein-Bridge Oscillator to provide the necessary sweep voltage to an ultra H-Q tuning varactor diode for the purpose of compensation and phase locking. The unique cosntruction of phase lock loop sub- assembly provides excellent temperature stability and minimum solder joints for maximum reliability. PLO-2000 series is internally voltage regulated to avoid reverse bias. frequency pushing, bias modulation and voltage transients. A phase lock indicator alarm of open TTL type is provided as a feature. The PLO-2000 series are externally reference locked and factory tuned to specified frequency. Mechanical frequency adjustment is provided for optimum phase voltage setting. DESCRIPTION FEATURES * LOW MICROPHONICS * LOW POWER CONSUMPTION * UP TO +25 dBm OUTPUT POWER * AVAILABLE FROM 1-50 GHz * OPERATING RANGE: -55°C TO +105°C * DIELECTRIC RESONATOR * INTERNAL VOLTAGE REGULATOR * PHASE LOCK INDICATOR ALARM * LOW PHASE NOISE * MIC AND SMT FABRICATION External Ref 100 MHz PLDRO (PLO-2000) APPLICATION * SATELLITE COMMUNICATIONS * CABLE TV LINKS (CATV) * LOCAL AREA NETWORKS (LAN) * GLOBAL POSITIONING SYSTEMS (GPS) * TEST EQUIPMENT * POINT TO POINT * UP/DOWN CONVERTERS * TRANSMITTER & RECEIVERS * DIGITAL RADIOS * MISSILE GUIDANCE * SPACE, MILITARY, COMMERCIAL MICROWAVE DYNAMICS, IRVINE, CA PLO-2000
Transcript of PLO-2000.pdf - Microwave...
PLO-2000 Series Phase Locked Dielectric Resonator Oscillator (PLDRO) utilizes state of the art MIC to provide highly stable, reliable and efficient signal source at microwave frequencies up to 50 GHz. The low profile and rugged construction provide excellent durability against harsh environmental conditions.
PLO-2000 oscillator is designed using FET or BJT amplifier with series feed back at source and DielectricResonator at the gate. High gain, low-noise FETs/BJTs are biased positively or negatively at the gate to ensureminimum phase-noise. The devise is carefully matched for maximam power, minimum phase-noise and VoltageStanding Wave Ratio (VSWR). The oscillator is matched for maximum temperature stability and optimum negative resistance.
PLO-2000 oscillator is buffered by cascaded low-noise driver and power amplifiers for minimum load pulling,maximum isolation and power. FET/BJT devices are directly attached to gold plated Kovar carriers to minimize shear effect and maximize heat sinking. Kovar carriers are mounted to the chassis to provide an efficient thermal junction and a stable structure for reduction of microphonics. To ensure oscillator stability over the fulltemperature range, the tuning elements are precisely designed and positioned to compensate for temperature drift by a factor of three.
PLO-2000 series proprietary phase lock loop circuitry is surface mounted on thick film Alumina substrate. The reference frequency is multiplied and sampled to output frequency. Produced error voltage due to frequency driftis sensed by a Wein-Bridge Oscillator to provide the necessary sweep voltage to an ultra H-Q tuning varactordiode for the purpose of compensation and phase locking. The unique cosntruction of phase lock loop sub-assembly provides excellent temperature stability and minimum solder joints for maximum reliability.
PLO-2000 series is internally voltage regulated to avoid reverse bias. frequency pushing, bias modulationand voltage transients. A phase lock indicator alarm of open TTL type is provided as a feature. The PLO-2000 series are externally reference locked and factory tuned to specified frequency. Mechanical frequency adjustment is provided for optimum phase voltage setting.
DESCRIPTION
FEATURES * LOW MICROPHONICS * LOW POWER CONSUMPTION* UP TO +25 dBm OUTPUT POWER* AVAILABLE FROM 1-50 GHz* OPERATING RANGE: -55°C TO +105°C
* DIELECTRIC RESONATOR* INTERNAL VOLTAGE REGULATOR* PHASE LOCK INDICATOR ALARM* LOW PHASE NOISE* MIC AND SMT FABRICATION
External Ref 100 MHz PLDRO(PLO-2000)
APPLICATION * SATELLITE COMMUNICATIONS* CABLE TV LINKS (CATV)* LOCAL AREA NETWORKS (LAN)* GLOBAL POSITIONING SYSTEMS (GPS)* TEST EQUIPMENT* POINT TO POINT
* UP/DOWN CONVERTERS* TRANSMITTER & RECEIVERS* DIGITAL RADIOS* MISSILE GUIDANCE* SPACE, MILITARY, COMMERCIAL
MICROWAVE DYNAMICS, IRVINE, CA
PLO-2000
2.070
2.25
.09.67
.25.280
OUTLINE DRAWING
SPECIFICATIONS
2.07
0
2.07
0
1.10
0
1.44
.50
Model NumberSingle FrequencyMechanical Tuning RangePower OutputLoad VSWR, MaximumPower RequirementsReference Input FrequencyReference Power InputReference Power Input RangeFrequency StabilityPhase NoiseSpuriousHarmonicsAlarmOperating TemperatureStorage TemperatureConnectorsSizeFinish
FIGURE A
PHASE NOISE ENVELOPE
SS
B P
HA
SE
NO
ISE
-d
Bc/
Hz
22 GHz
4GHz
-60
-70
-80
-90
-100
-110
-120
-130
-1401KHz 10KHz 50KHz 100KHz 400KHz 1MHz
OFFSET FREQUENCY FROM THE CARRIER
NOTE: Drawing not to scale
ØV
ALARM
+15V
REF IN
GND
RF OUT
PLO-2000-XX.XXSERIAL NO. XXXXDATE CODE XXXX
FREQ. ADJ
MNTG HOLES.101 DIA. THRU3 PLCS
2.25
MNTG HOLES2-56UNC-2B X .23 DP.4 PLCS
COPYRIGHT © 2006 MICROWAVE DYNAMICS, IRVINE CA • ORDERS ACCEPTED BY MICROWAVE DYNAMICS ARE SUBJECT TO OUR TERMS AND CONDITIONS OF SALESPECIFICATIONS ARE SUBJECT TO CHANGE WITHOUT NOTICE
BLOCK DIAGRAM
Ø Voltage Alarm
RFOUT
RFIN
AMPOSC
Regulator
AMP
Error AMP/Alarm
AM
P
AMPDET
Ø
+15VDC
External Crystal Ref.
MICROWAVE DYNAMICS, 16542 Scientific Way, Irvine, CA PHONE:949-679-7788 FAX: 949-679-7748Web Page :http://www.microwave-dynamics.com • Email: [email protected]
PLO-2000-XX.XX (Where XX.XX is freq. in GHz 1.00 to 50.00 GHz100 MHz+13 dBm,up to +25 dBm Optional2.0 :1.0+12, +15 VDC, 220 mA50 to 200 MHz0 dBm-6 to +10 dBmSame as ReferenceReference Noise + 20 Log (N) +3dB-80 dBc-25 dBcTTL-50º to +105ºC Optional; 0º to 50º Standard-55º to +125ºCSMA-Female or 2.9 mm-Female2.25" x2.25" x.67"Nickel
Model NumberSingle Frequency
Power Output Load VSWR, Maximum Power Requirements
Reference Power Input (Range) Frequency Stability Phase Noise Spurious Harmonics Operating Temperature Storage Temperature Connectors Size Finish
PLO-2000-XX.XX (Where XX.XX is freq in GHz) 1.00 to 50.00 GHz
+13 dBm, up to + 25 dBm Optional2.0: 1.0+12, +15 VDC, 220 mA
10 dBm (-6 to +10 dBm)Same as Reference Reference Noise + 20 Log (N) +3dB
-25 dBc
-55°C to 125°CSMA-Female or 2.92 mm-Female2.25” x 2.25” .67”Nickel
-80 dBc
0°C to 50°C Standard; -55°C to 105°C Optional
Mechanical Tuning Range 100 MHz
Reference Input Frequency 50 to 200 MHz
![2013-2014 ANNUAL ASSESSMENT REPORT TEMPLATE...Chart 3 a. PLO 1: j Y b. PLO 1: v Y c. PLO 1: n Y d. PLO 1: te P Y g. LO 3: j Y h. LO 3: l]Y i. PLO 4: al Y) 1 0 0.51 0.51 0 0.51 0.51](https://static.fdocuments.in/doc/165x107/5f2cb7f173abf20ea42d8e53/2013-2014-annual-assessment-report-template-chart-3-a-plo-1-j-y-b-plo-1.jpg)