Phase Locked Loop Design

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Phase Locked Loop Design KyoungTae Kang, Kyusun Choi Electrical Engineering Computer Science and Enginee ring CSE598A/EE597G Spring 2006

description

CSE598A/EE597G Spring 2006. Phase Locked Loop Design. KyoungTae Kang, Kyusun Choi Electrical Engineering Computer Science and Engineering. Frequency Synthesizer. General Synthesizer Issues. Frequency Spectrum. Settling Time (Lock Time). PLL Components Circuits. PLL Components Circuits. - PowerPoint PPT Presentation

Transcript of Phase Locked Loop Design

Page 1: Phase Locked Loop Design

Phase Locked LoopDesign

KyoungTae Kang, Kyusun Choi

Electrical Engineering

Computer Science and Engineering

CSE598A/EE597G Spring 2006

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Frequency Synthesizer

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General Synthesizer Issues

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Frequency Spectrum

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Settling Time (Lock Time)

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PLL Components Circuits

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PLL Components Circuits

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Reference Circuit

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PLL Components Circuits

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PFD and Charge Pump

Spur!!

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Phase Frequency Detector(1)

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Phase Frequency Detector(2)

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PFD and modified flip-flop

B.park, “A 1GHz, Low-Phase-Noise CMOS Frequency Synthesizer with Integrate LC VCO for Wireless Communications“, CICC 1998

Park, Byungha? GIT PhD. Samsung LSI, RF/Analog IC Group

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New Modified flip-flop by KT

•Reduce signal path

•High speed

•10 Transistors

•Negative reset

•No oscillation

•Customized

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D Flip-Flop

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DFF Simulation Comparison

•Modifed FF by KT

•DFF

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PFD Simulation(1)

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PFD Simulation(2)

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PFD Simulation(3)

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PFD Output Stage-Charge Pump

Programmable

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Charge Pump (Drain–s/w)

•My first Charge pump.

•Easy to design and understand how to work

•Spike Noise from net76 when U2 turn on

•High noise contribution!

•If you designed CP like this, you got fired!

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Charge Pump (Source-s/w)

•Low charge sharing

•Low noise

•Suppression the Spur

Level?

Why? Cascode?

>High impedence

>Pole!!!

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Charge Pump Simulation

CP_Drain

CP_Source

V(U/D)

I(U)

I(D)

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Charge Pumps

Rhee, W., "Design of high performance CMOS charge pumps in phase locked loop", In Proc. ISCAS, 1999, Vol. 1, pp. 545-548

J. S. Lee, M. S. Keel, S. I. Lim, and S. Kim, “Charge pump with perfect current matching characteristics in phase-locked loops,” Electronics Letters, Vol. 36, No. 23, pp. 1907-1908, November 2000.

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Loop Filter(1)

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Loop Filter(2)

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PLL Components Circuits

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Differential Delay Cell-Single pass

Chan-Hong Park, Solid-State Circuits, 1999.

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Differential Delay Cell-Multiple pass

Yalcin Alper Eken, Solid-State Circuits, 2004

Negative Skewed Delay Scheme:

Seog-Jun, Lee, ISSC, 1997

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Single pass Ring OSC.

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Multiple pass Ring OSC.

Which one is faster?

1. 3 stage single pass Ring OSC.

2. 5 stage multiple pass Ring OSC.

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3 Stage-Single pass Ring OSC.

•220MHz~825MHz @ V(Ctrl)=1.65V~3.3V

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3 Stage-Single pass Ring OSC.

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5 Stage-Multiple pass Ring OSC.

•1.65GHz~2.5GHz @ V(Ctrl) 1.65V~3.3V

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How to simulate Oscillator in Hspice?

.Option

Transient Step

Start-up time

Triggered Signal

Frequency Measure Tool: Cscope

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PLL Components Circuits

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Frequency Divider

•Input stage-high speed, low power, Following stages-High speed

•Differential type-Suppression Noise

•Input buffer is required

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N=64 Divider Simulation

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Input buffer

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PLL Simulation

V(VCO)

V(Ref)

V(DiV)

V(Up)

V(Dn)

V(Ctrl)


A Phase Locked Loop for Molecular Communications and ... Phase Locked Loop for Molecular Communications and...electronics, phase locked loop (PLL) is known to align timing or phase

A Phase Locked Loop for Molecular Communications and ... Phase Locked Loop for Molecular Communications and...electronics, phase locked loop (PLL) is known to align timing or phase

Analysis and Comparison of Phase Locked Loop

Analysis and Comparison of Phase Locked Loop

Digital Phase Locked Loop

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Discrete Phase-Locked Loop Systems and Spreadsheets

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Phase-Locked Loop Basics (PLL)

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Phase locked loop frequency synthesizers · Phase locked loop frequency synthesizers SMDP Instructional Enhancement Program Nagendra Krishnapura Department of Electrical Engineering

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Practical Phase-Locked Loop Design

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A MULTI-BAND PHASE-LOCKED LOOP FREQUENCY

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Phase Locked Loop Design Fundamentals

Phase Locked Loop Design Fundamentals

An Efficient Phase-Locked Loop for Distorted Three-Phase ...

An Efficient Phase-Locked Loop for Distorted Three-Phase ...

DESIGN AND ANALYSIS OF EFFICIENT PHASE LOCKED LOOP … · Phase Locked Loop (PLL) mainly for synchronization, clock synthesis, skew and jitter reduction [5]. Phase locked loops find

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CD4046B Phase-Locked Loop (Rev. A)

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Practical Phase-Locked Loop Design - A Tutorial

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Phase-locked loop based on nanoelectromechanical … loop... · Phase-locked loop based on nanoelectromechanical resonant-body ... on nanoelectromechanical resonant-body field ...

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