July 14 - 18, 2014

Peter Williams Lecture Theatre

University of Leicester, Leicester, UK

http://www2.le.ac.uk/conference/ahs2014

2014 NASA/ESA Conference on

Adaptive Hardware and Systems

July 14 - 18, 2014

Peter Williams Lecture Theatre, University of Leicester, Leicester, UK

Organized by National Aeronautics and Space Administration – Jet Propulsion Laboratory (NASA-JPL)

European Space Agency, Netherlands (ESA)

Fraunhofer Institute for Integrated Circuits IIS, Germany (Fraunhofer IIS)

University of Leicester, UK (UoL)

Sponsored by Society for Adaptive and Evolvable Hardware and Systems (ADEVO)

National Aeronautics and Space Administration (NASA)

Bio-Inspired Technologies and Systems (BITS), Jet Propulsion Laboratory (JPL)

European Space Agency, Netherlands (ESA)

IEEE Circuits and Systems Society (IEEE-CAS)

ACM Special Interest Group on Design Automation (ACM-SIGDA)

Fraunhofer Institute for Integrated Circuits IIS, Germany (Fraunhofer IIS)

University of Leicester, UK (UoL)

General Chair Tanya Vladimirova, University of Leicester, UK

General Co-Chairs Richard Katz, NASA Goddard Space Flight Center, USA

Rainer Wansch, Fraunhofer Institute for Integrated Circuits IIS, Germany

Zhengxu Zhao, Shijiazhuang Tiedao University, P R China

Preface

These proceedings contain the papers presented at the 2014 NASA/ESA Conference on

Adaptive Hardware and Systems (AHS-2014), held at University of Leicester, Leicester,

United Kingdom, on 14-18 July 2014. The purpose of the AHS 2014 conference is to bring

together leading researchers from the adaptive hardware and systems community to exchange

experiences and share new ideas in the field.

Adaptation reflects the capability of a system to maintain or improve its performance in

the context of internal or external changes, such as uncertainties and variations during

fabrication, faults and degradations, modifications in the operational environment, incidental

or intentional interference, different users and preferences, modifications of standards and

requirements, trade-offs between performance and resources, etc.

Adaptation at hardware levels increases the system capabilities beyond what is possible

with software-only solutions, and a large number of adaptation features employing both

analogue and digital adjustments are becoming increasingly present in the most elementary

system components. Algorithms, techniques, and their implementation in hardware from

spacecraft and rovers to instruments and avionics are developed over a diverse variety of

applications, such as adaptive communications (adapting to changing environment and

interference), reconfigurable systems on a chip and embedded wireless devices (adapting to

power limitations) or survivable spacecraft (adapting to extreme environments and mission

unknowns).

The papers presented during the conference spanned many topics: state-of-the-art adaptive

technology, reconfigurable systems, multi-core and heterogeneous computing and

architectures, fault-tolerant and self­repair systems, embryonic hardware, adaptive image and

signal processing, wireless sensor networks, space systems.

A number of tutorials, an invited special session and a workshop were organized. Invited

and regular papers on challenging topics such as “Fault Detection Isolation and Recovery”

and “Adaptive Systems” were presented. Keynote addresses on the state-of-the-art in on-

board data systems, small satellites and multi-core processors for space applications were

given.

Finally, we would like to acknowledge the support and hard work of the many individuals

who made AHS-2014 a reality. First, we thank the authors and the invited speakers for their

high-quality contributions. We express our gratitude to the Programme Committee for their

gracious assistance in the refereeing process. We thank our organisers and host: the NASA

Jet Propulsion Laboratory, the European Space Agency, the Fraunhofer Institute for

Integrated Circuits IIS, the University of Leicester.

1

Conference Organisers

General Chair

Tanya Vladimirova, University of Leicester, UK

General Co-Chairs

Richard Katz, NASA Goddard Space Flight Center, USA

Rainer Wansch, Fraunhofer Institute for Integrated Circuits IIS, Germany

Zhengxu Zhao, Shijiazhuang Tiedao University, P R China

Program Chair

Michael Newell, Athens Consulting, LLC, USA

Program Co-Chairs

David Merodio, European Space Agency (ESA), Netherlands

Omar Emam, EADS Astrium, UK

Michael Huebner, Ruhr-Universitaet Bochum, Germany

Publicity Chair

Ahmet Erdogan, University of Edinburgh, UK

Local Organising Chairs

Muhammad Fayyaz, University of Leicester, UK

Xiaojun Zhai, University of Leicester, UK

Steering Committee

Adrian Stoica, Jet Propulsion Laboratory, USA (Chair)

Tughrul Arslan, University of Edinburgh, UK

Didier Keymeulen, Jet Propulsion Laboratory, USA

David Merodio, European Space Agency (ESA), Netherlands

Khaled Benkrid, ARM Ltd., UK

Umeshkumar Patel, NASA Goddard Space Flight Center, USA

Ahmet Erdogan, University of Edinburgh, UK

2

Program Committee

Ali Ahmadinia, Glasgow Caledonian University,

UK

Ali Akoglu, University of Arizona, USA

Abbes Amira, University of the West of Scotland,

UK

Nazeeh Aranki, Jet Propulsion Laboratory, USA

Nizamettin Aydin, Yildiz Technical University,

Turkey

Larry Bergman, Jet Propulsion Laboratory, USA

Neil Bergmann, University of Queensland,

Australia

Ahmed Bouridane, Northumbria University, UK

Alex Doboli, State University of New York, USA

Rolf Drechsler, University of Bremen, Germany

Manfred Glesner, Darmstadt University of

Technology, Germany

Sezer Goren, Yeditepe University, Turkey

Steven Guccione, Cmpware, Inc., Austin, USA

Pauline Haddow, Norwegian University of Science

and Technology, Norway

Niels Hadaschik, Fraunhofer Institute for

Integrated Circuits IIS, Germany

Alister Hamilton, University of Edinburgh, UK

Gareth J. Howells, University of Kent, UK

Richard Jansen, European Space Agency (ESA),

Netherlands

H.J. Kadim, Liverpool JM University, UK

Markus Koester, University of Paderborn,

Germany

Dimitrios Kritharidis, Intracom S.A. Telecom

Solutions, Greece

Martin Margala, University of Massachusetts

Lowell, USA

Konstantinos Masselos, University of

Peloponnese, Greece

Klaus D. McDonald-Maier, University of Essex,

UK

J. Manuel Moreno, Technical University of

Catalunya, Spain

Masahiro Murakawa, National Institute of

Advanced Industrial Science and Technology,

Japan

Christos Papachristou, Case Western Reserve

University, USA

Jelle Poupaert, European Space Agency (ESA),

Netherlands

Gang Qu, University of Maryland, USA

Radu Secareanu, Freescale Semiconductor, USA

Marco Santambrogio, Politecnico di Milano, Italy

Tiberiu Seceleanu, ABB Corporate Research,

Sweden

Lukas Sekanina, Brno University of Technology,

Czech Republic

Hajime Shibata, Analog Devices, Canada

Luca Sterpone, Politecnico di Torino, Italy

Gianluca Tempesti, University of York, UK

Jim Torresen, University of Oslo, Norway

Andrew M. Tyrrel, University of York, UK

Fatih Ugurdag, Ozyegin University, Turkey

Ranga Vemuri, University of Cincinnati, USA

Massimo Violante, Politecnico di Torino, Italy

Erfu Yang, University of Stirling, UK

Ken Zick, USC Information Sciences Institute,

USA

3

Invited Keynote Address

10am-11am, 15th July, 2014

Abstract:

On-board data systems and data handling electronics are in constant evolution, due to the

obsolescence of components and indeed to the need of increasing their performances. They follow

ground technology trends, often at a slower pace, such as the ones allowing easier and faster

integration by reusing building blocks. This is well reflected by on-board platform and payload

computers that become not only more compact and more powerful but also more versatile. In parallel,

high speed links and on-board networks (e.g. SpaceWire, SpaceFibre, and Ethernet) are now widely

used. They complement or even replace more conventional command and control busses (e.g.

Mil1553).

On the same line, sensor links and busses (e.g. SPI, I2C, CAN) are being adapted to space use.

Another interesting evolution is related to file based mass-memories (e.g. non-volatile) allowing data

to be easily stored on-board and retrieved by applications through standardised services and protocols.

These facilities are extended to new concepts including file based operations.

On the basis of future missions for which adaptively are an enabling requirement, the presentation

addresses ESA's approach for streamlining the development of Data Systems. Starting from reference

architectures, the concept of Space Avionics Open Interface Architecture (SAVOIR) is then detailed.

Then the definition of generic specifications for key units such as On-Board Computers and Remote

Terminal Units are addressed together with some implementation options.

Finally, functions and features supporting an adaptive behaviour of the sub-system during definition,

development and operations are presented.

Biography:

Philippe Armbruster received an Engineering degree in Physics and Electronics in 1983 and then a

PhD in Signal and Image Processing from the Louis Pasteur University of Strasbourg in 1987, France.

After having completed the development of a very high resolution image digitising and processing

system for a German company, he started working in 1989 at the technical centre of the European

Space Agency, ESTEC, located in The Netherlands. He was first in charge of developing signal

processing devices and electronic units for on-board satellite payload data processing applications.

Being nominated head of the Data Systems division in 2003, he is responsible presently for the

development of radiation hardened microprocessors, computers, mass memories and on-board

electronics in general. He contributed significantly to the development of the SpaceWire standard

used worldwide today to implement on-board networks. Philippe Armbruster is now focusing on

space avionics based on open interfaces (SAVOIR initiative) and adaptive on-board data systems.

ESA Developments for On-board Data Systems

Philippe Armbruster

Head of Data Systems Division, ESA

4

Invited Keynote Address

9am-10am, 16th July, 2014

Abstract:

Modern small satellites, taking advantage of the dramatic advances in commercial ‘off-the-shelf’

(COTS) technologies developed for the industrial and consumer markets, have developed capabilities

that are rivalling their conventional large satellite counterparts but at considerably lower cost and

shorter timescales to launch – fundamentally changing the approach to space, enabling wider

participation in space activities and applications, and stimulating new business models.

Biography:

Andy Bradford started his career in the space industry as a young graduate trainee (YGT) at ESA

ESTEC; during this time he played a major role in the 'TeamSat' mission, which was a small satellite

designed and built mainly by students and young graduates. Following this Andy worked for Bradford

Engineering in the Netherlands (the name is a pure coincidence!), working mainly on small satellite

studies and also propulsion systems and components for small satellites. Andy returned to the UK in

1998 to join Space Innovations Ltd (SIL) in Newbury, as a Mechanical Systems engineer, primarily

working as the mechanical and AIT lead on the Australian 'FedSat' satellite. Andy joined SSTL in

2000, following the demise of SIL. Andy's first role in SSTL was as a project manager, initially on

the FedSat project, which SSTL took on from SIL. Andy went on to manage the BILSAT project from

2001 to 2003, and then the GIOVE-A project from 2003 to early 2006. After this Andy managed the

Mechanical Systems Group, until August 2007 when he joined the SSTL leadership team, initially as

Director of Projects. Shortly afterwards he transferred to the role of Director of Engineering, which

he held until October 2013, at which point he took up his current role of Director of Special

Programmes.

Andy has an MSc in Astronautics and Space Engineering from Cranfield University and a BSc in

Design Engineering.

Small Satellites - the Disruptive Use of COTS Technologies

Andy Bradford

Director of Special Programmes

Surrey Satellite Technology Ltd (SSTL), Guildford, UK

5

Invited Keynote Address

9am-10am, 17th July, 2014

Abstract:

Multi-core processors (MCPs) are now proposed for use in critical applications for their increased

performance and to mitigate product obsolescence. MCPs offer adaptive systems powerful features to

dynamically change behaviour at run-time in response to changes in the operational environment,

system configuration, resource availability or other factors, but are still looked at warily in critical

domains. Fault-tolerant architectures targeted at high-reliability can be, in principle, implemented in

multi-core devices making full use of redundant hardware and software. In that case, the fault

tolerance or at least fail safe mechanism must be provided by an external fault detection function.

However MCPs contain built-in components that are not present in single-core processors which can

provoke nondeterministic interference between the software applications executing on the separate

cores. In addition, some MCPs can dynamically change the behaviour of the processors in the absence

of external input upon fulfilment of certain criteria.

This presentation will discuss the reasons why we are compelled to use multi-core processors, the

issues these devices pose in critical applications and possible solutions to them.

Biography:

Avelino Martin is Head of the Hardware Design Assurance Department at Airbus Defence and Space

Military Aircraft. He has over 25 years of electronic engineering experience including expertise in

Space Hardware and Microelectronics Design. Before Airbus Defence, Avelino held a SoCCER

group position at EADS ASTRIUM (SoC/IP) involving work on complex hardware certification

compliance issues.

Avelino is the co-author of the CEPA 2 Micro-Electronics White Book (Military Aerospace

Roadmaps, for Western European Union Ministries of Defence) on ASIC – FPGA – IP – SoC and

participates in a number of Airborne Electronic Hardware certification transnational (European /

American) working groups. He holds a Telecommunications Engineering Degree from the Technical

University of Madrid.

Multi-Core Processors in Critical Applications

Avelino Martin

Head of Hardware Design Assurance at Airbus Defence and Space

Military Aircraft

6

Tutorial 1

Radiation Effects in Space, an Introduction

Stefan K. Hoeffgen, Fraunhofer INT

10am-11am, 14th July, 2014

Abstract:

This tutorial will give a general introduction to radiation effects in space from the environment to

testing. It will be structured into four parts:

Part 1 gives an overview of the radiation environment in space and its sources: terrestrial, solar and

galactic-cosmic.

Part 2 describes the effects of the radiation at transistor level. It will concentrate on the effects

relevant to CMOS technology namely Total Ionizing Dose (TID) as well as Single Event Upsets (SEU)

Single Event Functional Interrupts (SEFI) and Single Event Latchup (SEL).

Part 3 gives a short overview of some radiation hardening techniques at process level.

Part 4 is concerned with the testing of the devices for TID and SEE at different facilities (Co-60,

protons, and heavy ions).

7

Tutorial 2

Error-Resilient Circuits and Micro-Architecture Techniques for

Energy-Efficient Computing

Karthik Shivashankar, ARM University Programme, R&D

11am-12am, 14th July, 2014

Abstract:

Integrated circuits in modern SoCs and microprocessors are typically operated with sufficient margins

to mitigate the impact of rising uncertainties at advanced process nodes. The widening safety-margins

required to ensure robust computation in the face of such uncertainties inevitably lead to conservative

designs with unacceptable power and performance overheads. Recently, error-tolerant circuit

techniques have received increased research focus both in academia and in industry as an effective

means of achieving energy-efficient computation through the elimination of these design margins.

Typically, these techniques incorporate specialized circuitry to detect occasional critical-path failure

due to worst-case variations. Suitable recovery mechanisms restore correct pipeline state while

ensuring forward progress.

This tutorial discusses a wide spectrum of error-tolerant approaches from industry and academia,

specifically highlighting ARM research in this area. In particular, a technique called “Razor" that

introduced timing-speculation in microprocessor pipelines in order to eliminate voltage and

frequency guard bands is reviewed. Several academic and industrial prototypes that incorporate Razor

and similar techniques are reviewed. The tutorial also describes recent work that extends timing-

speculation to hardware accelerators in communications and digital signal-processing applications.

8

Tutorial 3

The LEON Processor

Part I: Overview of Past, Current and Next-Generation LEON

SoC Architectures

Part II: Introduction to the Open Source LEON/GRLIB IP

Library

Jan Andersson, Aeroflex Gaisler

12:15am-13:15am and 14:00am-15:00am, 14th July, 2014

Abstract:

The LEON project was started by the European Space Agency in late 1997 to study and develop a

high-performance processor to be used in European space projects. The objectives for the project were

to provide an open, portable and non-proprietary processor design, capable to meet future

requirements for performance, software compatibility and low system cost. Another objective was to

be able to manufacture in a Single Event Upset (SEU) sensitive semiconductor process. In order to

maintain correct operation in the presence of SEUs, extensive error detection and error handling

functions were needed.

Traditionally, a LEON SoC design has consisted of one single processor connected to a bus with a

memory controller and various peripherals and communication controllers. In recent years, a shift has

been made where multi-core architectures have become available for use in the harsh space

environment.

The tutorial will give an overview of the VHDL design methods developed and used for the LEON

project and of how the LEON processors have evolved from single CPU systems to multi-core

devices, via the GR712RC processor, and currently to the ESA quad-processor Next Generation

Microprocessor (NGMP) architecture.

In parallel with the architectural advancements, the environment around the LEON processor has also

changed. The tutorial will describe the current state of Aeroflex Gaisler’s GRLIB IP library that

includes the latest LEON processors together with over 100 peripheral IP cores. Focus will be on the

free open source version of GRLIB that is currently being used for research and education by

universities around the globe.

9

Tutorial 4

SpaceWire: Fundamentals, Applications and Future

Developments

Prof. Steve Parkes, Star Dundee Ltd

14:45am-15:45am, 14th

July, 2014

Jorgen Ilstad, European Space Agency

16:00am-17:00am, 14th

July, 2014

Abstract:

The SpaceWire tutorial will be presented by Professor Steve Parkes from the University of Dundee,

who wrote the SpaceWire standard with inputs from international engineers, and Jorgen Ilstad, an

experienced SpaceWire engineer from ESA who has worked supporting several ESA missions using

SpaceWire and has developed several important SpaceWire technologies.

SpaceWire is a computer network for use onboard spacecraft that connects together instruments,

mass-memory, on-board processors, and the downlink telemetry system. SpaceWire is simple to

implement and has some specific characteristics that help it support data-handling applications in

space: high-speed, low-power, simplicity, relatively low implementation cost, and architectural

flexibility making it ideal for many space missions. SpaceWire provides high-speed (2 Mbits/s to 200

Mbits/s), bi-directional, full-duplex data-links, which connect together SpaceWire enabled equipment.

Data-handling networks can be built to suit particular applications using point-to-point data-links and

routing switches.Since the SpaceWire standard was published in January 2003, it has been adopted by

ESA, NASA, JAXA and RosCosmos and is being widely used on scientific, Earth observation,

commercial and other spacecraft. High-profile missions using SpaceWire include: Gaia, ExoMars

rover, Bepi-Colombo, James Webb Space Telescope, GOES-R, Lunar Reconnaissance Orbiter and

Astro-H.

The SpaceWire tutorial comprises two parts: SpaceWire Fundamentals and SpaceWire Applications

and Future Developments.

The SpaceWire Fundamentals tutorial provides an introduction to the way in which SpaceWire

works. First the various levels of the SpaceWire standard are described including the physical, signal,

character, exchange, and packet levels. SpaceWire routers and networks are then introduced and the

way in which a SpaceWire network operates is explained. The operation of SpaceWire time-codes,

which broadcast synchronisation signals across a SpaceWire network, is explained. The Remote

Memory Access Protocol (RMAP) will also be introduced. At the end of this part of the tutorial the

participant will have a good understanding of how SpaceWire works.

SpaceWire Applications and Future Developments tutorial explores how SpaceWire is being used

in practice. Several space missions are taken as examples and the data-handling architecture is

described. The use of point-to-point links to transfer data from a high-data rate instrument to a mass-

memory system is illustrated by GAIA and Sentinel 1. The use of router technology to form

SpaceWire networks is illustrated with missions like BepiColombo and MTG. A brief overview of

current and future developments of SpaceWire will be presented.

10

Tutorial 5

Overview of the FP7 Project FlexTiles

Philippe Millet, Thales, France

14:45am-15:45am, 14th

July, 2014

Abstract:

A major challenge in computing is to leverage multi-core technology to develop energy-efficient high

performance systems. This is critical for embedded systems with a very limited energy budget as well

as for supercomputers in terms of sustainability. Moreover the efficient programming of multi-core

architectures, as we move towards many-core solutions with more than a thousand processor cores

predicted by 2020, remains an unresolved issue. The FlexTiles project defines and develops an

energy-efficient yet programmable heterogeneous many-core platform with self-adaptive capabilities.

The many-core is associated with an innovative virtualisation layer and a dedicated tool-flow to

improve programming efficiency, reduce the impact on time to market and reduce the development

cost by 20 to 50%. FlexTiles raises the accessibility of the many-core technology to industry – from

small SMEs to large companies – thanks to its programming efficiency and its ability to adapt to the

targeted domain using embedded reconfigurable technologies.

FlexTiles is a 3D stacked chip with a many-core layer and a reconfigurable layer. This heterogeneity

brings a high level of flexibility in adapting the architecture to the targeted application domain for

performance and energy efficiency.

A virtualisation layer on top of a kernel hides the heterogeneity and the complexity of the many-core

platform from its programmer and fine-tunes the mapping of an application at runtime. The

virtualisation layer provides self-adaptation capabilities by dynamic relocation of application tasks to

software on the many-core or to hardware on the reconfigurable layer. This self-adaptation is used to

optimise load balancing, power consumption, hot spots and resilience to faulty modules.

The reconfigurable technology is based on a virtual bitstream that allows dynamic relocation of

accelerators just as software based on virtual binary code allows task relocation. This flexibility

allows the use of fault mitigation schemes, a crucial issue for future many-cores. During the execution

of the application, the runtime binding is done to match the configuration defined by the virtualisation

layer. It adapts the location of the code, the storage and the communication paths on the fly.

11

Conference Programme

TUTORIALS DAY - MONDAY, 14th

JULY, 2014

Chair: Didier Keymeulen

9:30 - 10:00 REFRESHMENTS

10:00 - 11:00 Tutorial 1: Radiation Effects

Stefan K. Hoeffgen, Fraunhofer INT, Germany

11:00 - 12:00

Tutorial 2: Title: Error-Resilient Circuits and Micro-Architecture Techniques

for Energy-Efficient Computing

Karthik Shivashankar, ARM University Programme, R&D

12:00 – 12:15 COFFEE BREAK

12:15 – 13:15

Tutorial 3: The LEON Processor

Part I: Overview of Past, Current and Next-Generation LEON SoC

Architectures

Jan Andersson, Aeroflex Gaisler

13:15 – 14:00 LUNCH

14:00 – 15:00

Tutorial 3: The LEON Processor

Part II: Introduction to the Open Source LEON/GRLIB IP Library

Jan Andersson, Aeroflex Gaisler

14:45 – 15:45

Tutorial 4: SpaceWire

Part I: SpaceWire Fundamentals

Prof. Steve Parkes, Star Dundee Ltd

15:45 – 16:00 COFFEE BREAK

16:00 – 17:00

Tutorial 4: SpaceWire

Part II: SpaceWire Applications and Future Developments

Jorgen Ilstad, European Space Agency

17:00 – 18:00 Tutorial 5: FP7 Project FlexTiles - Overview

Philippe Millet, Thales, France

18:30 Welcome Party: BBQ at the Old Horse

12

DAY 1 - TUESDAY, 15th

JULY, 2014

Day Chair: Prof. Tanya Vladimirova, University of Leicester, UK

08:00 – 09:00 Registration

09:00 – 09:10

Opening Address and Organisational Remarks

Prof. Tanya Vladimirova

University of Leicester, UK

09:10 – 09:20

Welcome Address by Prof. Helen Atkinson, CBI, FREng

Head of Department of Engineering

University of Leicester

Vice-President, Royal Academy of Engineering

09:20 – 10:00

Welcome Address by Prof. Martin Barstow

Pro-Vice–Chancellor, Head of College of Science and Engineering,

University of Leicester

President-elect, Royal Astronomical Society

10:00 – 11:00

Invited Keynote Address: ESA Development for On-board Systems

Philippe Armbruster

Head of Data Systems Division, European Space Agency (ESA), Netherlands

11:00 – 11:30 COFFEE BREAK

Session A. Reconfigurable Systems

Chair: David Merodio Codinachs, European Space Agency (ESA), Netherlands

11:30 – 11:55

Considering reconfiguration overhead in scheduling of dependent tasks on 2D

Reconfigurable FPGA

Quang-Hai Khuat1, Daniel Chillet

1 and Michael Hübner

2

1University of Rennes 1 - IRISA/INRIA

2Ruhr-University Bochum, ESIT

11:55 – 12:20

A Novel Dynamic Partial Reconfiguration Design for Automatic White

Balance

Jalal Khalifat and Tughrul Arslan

University of Edinburgh

12:20 – 14:00 LUNCH

14:00 – 14:25

Efficient Reconfiguration of Processing Modules on FPGAs for Space

Instruments

Sándor Fekete, Björn Fiethe, Stephan Friedrichs, Harald Michalik and Christos

Orlis

Braunschweig University of Technology

13

Session B. Special Session: FDIR

Chair: Jorgen Ilstad, European Space Agency (ESA), Netherlands

14:25– 14:50

New Voter Design Enabling Hot Redundancy for Asynchronous Network

Nodes

Felix Siegle1, Tanya Vladimirova

1, Omar Emam

2 and Jørgen Ilstad

3

1University of Leicester

2Astrium Defence and Space

3European Space Agency, ESTEC, Netherlands

14:50 – 15:15

Online Fault Detection for Networks-on-Chip Interconnect

Junxiu Liu, Jim Harkin, Yuhua Li and Liam Maguire

University of Ulster

15:15 – 15:40

Improved Fault-tolerance through Dynamic Modular Redundancy (DMR) on

the RISA FPGA Platform

Martin Trefzer and Andy Tyrrell

University of York

15:40 – 16:05

Decentralized Run-Time Recovery Mechanism for Transient and Permanent

Hardware Faults for Space-borne FPGA-based Computing Systems

Victor Dumitriu1, Lev Kirischian

1 and Valeri Kirischian

2

1Ryerson University

2MDA Space Missions

16:05 – 16:35 COFFEE BREAK

Session C. Adaptive Systems - I

Chair: Prof. Martin Margala, University of Massachusetts Lowell

16:35 – 17:00

Run-time power and performance scaling with CPU-FPGA hybrids

Jose Nunez-Yanez and Arash Beldachi

University of Bristol

17:00 – 17:25

Power-Aware Multi-Objective Evolvable Hardware System on an FPGA

Blanca Lopez, Juan Valverde, Eduardo de La Torre and Teresa Riesgo

CEI-UPM

17:25 – 17:50

A Hierarchical Fault Tolerant System on the PAnDA Device with Low

Disruption

David Michael Renwick Lawson, James Alfred Walker, Martin A. Trefzer, Simon J.

Bale and Andy M. Tyrrell

University of York

18:30 – 20:00 City Tour: Guided walk “The Story of Leicester”

Start at the junction of New Walk and King Street

14

DAY 2 - WEDNESDAY, 16th

JULY, 2014

Day Chair: Michael Newell, Athens Consulting, LLC, USA

08:30 – 09:00 Registration

9:00 – 10:00

Invited Keynote Address: Small Satellites - The Disruptive Use of COTS

Technologies

Andy Bradford

Director of Special Programmes

Surrey Satellite Technology Ltd (SSTL)

Session D. Fault Tolerant Systems

Chair: Michael Newell, Athens Consulting

10:00 – 10:25

Soft Error Mitigation Through Selection of Non-invert Implication Paths

Bin Zhou1, Srikanthan Thambipillai

1 and Wei Zhang

2

1Nanyang Technological University

2Hong Kong University of Science and Technology

10:25 – 10:55 COFFEE BREAK

10:55 – 11:20

On Enhancing the Reliability of Internal Configuration Controllers in FPGAs

Ali Ebrahim1, Tughrul Arslan Arslan

1 and Xabier Iturbe

2

1University of Edinburgh

2Ikerlan-IK4

11:20 – 11:45

The Upset-Fault-Observer: A Concept for Self-Healing Adaptive Fault

Tolerance

Byron Navas, Johnny Öberg and Ingo Sander

Royal Institute of Technology (KTH)

Session E. Adaptive Image Processing

Chair: Didier Keymeulen

11:45– 12:10

Automated Thresholding for Low-Complexity Corner Detection

Nirmala Ramakrishnan, Meiqing Wu, Siew-Kei Lam and Thambipillai Srikanthan

Nanyang Technological University

12:10 – 12:35

ABLUR: an FPGA-based adaptive deblurring core for real-time applications

Giuseppe Airò Farulla, Marco Indaco, Paolo Prinetto, Daniele Rolfo and Pascal

Trotta

Politecnico di Torino

12:35 – 14:00 LUNCH

14:00 – 14:25

Adaptive Hyperspectral Image Compression using the KLT and Integer KLT

algorithm

Chafik Egho1 and Tanya Vladimirova

2

1Surrey Space Centre, University of Surrey

2University of Leicester

15

Session F: Adaptive Signal Processing

Chair: Prof. Giovanni Beltrame, Ecole Polytechnique de Montreal

14:25 – 14:50

Fault Diagnosis for MEMS INS using Unscented Kalman Filter Enhanced

by Gaussian Process Adaptation

Ivan Vitanov and Nabil Aouf

Defence and Security, Cranfield University

14:50 – 15:15

A Modular FPGA-based Implementation of the Unscented Kalman Filter

Jeremy Soh and Xiaofeng Wu

University of Sidney

15:15 – 15:40

Novel PCA based Pixel Level Multi-Focus Image Fusion Algorithm

Hongyuan Jing and Tanya Vladimirova

University of Leicester

15:40 – 16:10 COFFEE BREAK

16:10 – 18:00 Poster Session

Chair: Muhammad Fayyaz, University of Leicester

Poster 1

Learning Engine for Cognitive Radio Based on the Immune Principle

Rui Yao, Kun He, Yanmei Sun and Youren Wang

Nanjing University of Aeronautics and Astronautics

Poster 2

Dynamic parallel reconfiguration for self-adaptive hardware architectures

Laurent Fiack1, Benoit Miramond

1, Andres Upegui

2 and Fabien Vannel

2

1ETIS Lab UMR 8051 CNRS / ENSEA / UCP

2University of Applied Sciences Western Switzerland, hepia, HES-SO

Poster 3

Method to Self-repairing Reconfiguration Strategy Selection of Embryonic

Cellular Array on Reliability Analysis

Zhai Zhang

Nanjing University of Aeronautics and Astronautics, College of Automation

Engineering

Poster 4

Increasing multiprocessor lifetime by Youngest-First Round-Robin core

gating patterns

Aleksandar Simevski1,2

, Rolf Kraemer1,2

and Milos Krstic1

1IHP GmbH

2BTU Cottbus-Senftenberg

Poster 5

Balancing System Availability and Lifetime with Dynamic Hidden Markov

Models

Jacopo Panerati1, Samar Abdi

2 and Giovanni Beltrame

1

1Ecole Polytechnique de Montreal

2Concordia University

Poster 6

Airborne Demonstration of FPGA implementation of Fast Lossless

Hyperspectral Data Compression System Didier Keymeulen

Poster 7

Dynamically Adaptive and Reliable Approximate Computing Using Light-

Weight Error Analysis

Beayna Grigorian and Glenn Reinman

University of California, Los Angeles

16

Poster 8

Hardware Suport Vector Machine (SVM) for Satellite On-Board Applications

Abdul-Halim Jallad1 and Lubna Mohammed

2

1American University of Ras Al-Khaimah

2Al-Zaytoonah University of Jordan

Poster 9

Energy balancing in multi-hop Wireless Sensor Networks: an approach based

on reinforcement learning

Guido Oddi, Antonio Pietrabissa and Francesco Liberati

University of Rome "La Sapienza"

Poster 10

A Compact Realization of an n-Bit Quantum Carry Skip Adder Circuit with

Optimal Delay

Nusrat Jahan Lisa1 and Hafiz Md Hasan Babu

2

1Ahsanullah University of Science & Technology

2University of Dhaka

Poster 11

Design and Integration of an Intelligent Controller for a Fourier Transform

Spectrometer

Didier Keymeulen

19:30 – 23:30

Conference Dinner and Prize Awards

National Space Centre

Exploration Drive, Leicester

17

DAY 3 - THURSDAY, 17th

JULY, 2014

Day Chair: Rainer Wansch, Fraunhofer Institute for Integrated Circuits IIS

08:30 – 09:00 Registration

09:00 – 10:00

Invited Keynote Address: Multi-core Processors in Critical Applications

Avelino Martin

Head of Hardware Design Assurance

Airbus Defence and Space - Military Aircraft

Session G: Space Systems - I

Chair: Rainer Wansch, Fraunhofer Institute for Integrated Circuits IIS

10:00 – 10:25

A Run Time Adaptive Architecture to trade-off Performance for Fault

Tolerance applied to a DVB On-Board Processor

Filip Veljković1, Teresa Riesgo

1, Eduardo de La Torre

1, Raúl Regada

2 and Luis

Berrojo2

1Center of Industrial Electronics - Universidad Politecnica de Madrid

2Thales Alenia Space Spain

10:25 – 10:55 COFFEE BREAK

10:55 – 11:20

Broadband FPGA Payload Processing in a Harsh Radiation Environment

Florian Rittner1, Robért Glein

2, Thomas Kolb

1 and Benjamin Bernard

1

1Fraunhofer IIS

2University of Erlangen-Nuremberg

11:20 – 11:45

Towards an Adaptive Network Centric Distributed Time and Space

Partitioned Platform Architecture

Christian Fidi1 and Hans-Jürgen Herpel

2

1TTTech computer technik AG

2Airbus Defense and Space

11:45– 12:10

SpaceFibre: Adaptive High-Speed Data-Link for Future Spacecraft Onboard

Data Handling

Steve Parkes1, Albert Ferrer Florit

2, Alberto Gonzalez Villafranca

2, Chris

McClements1, David McLaren

1 and Angel Monera Martinez

1

1University of Dundee

2STAR-Dundee Ltd

12:10 – 12:35

Software Defined Radios for Small Satellites

Mamatha Maheshwarappa and Christopher Bridges

Surrey Space Centre, University of Surrey

12:35 – 14:00 LUNCH

18

Session I. Space Systems - II

Chair: Christopher Bridges, Surrey Space Centre, University of Surrey

14:00 – 14:25

Space Wireless Sensor Networks for Planetary Exploration: Node and

Network Architectures

Pedro Rodrigues1, André Oliveira

1, Guido Oddi

2, Francesco Liberati

2, Francisco

Alvarez3, Ramiro Cabás

3, Tanya Vladimirova

4, Xiaojun Zhai

4, Hongyuan Jing

4 and

Michael Crosnier5

1Tekever

2University of Rome "La Sapienza"-CRAT

3Arquimea Ingeniería S.L.U.

4University of Leicester

5Airbus Defence and Space

14:25 – 14:50

Multi-Sensor Data Fusion in Wireless Sensor Networks for Planetary

Exploration

Xiaojun Zhai, Hongyuan Jing and Tanya Vladimirova

University of Leicester

Session J. Adaptive Systems - II

Chair: Abdul-Halim Jallad, American University of Ras Al-Khaimah

14:50 – 15:15

Region Adaptive Digital Image Watermarking System using DWT-SVD

algorithm

Chunlin Song1, Sud Sudirman

2, Madjid Merabti

2 and Peng Xiao

1

1Jiangnan University

2Liverpool John Moores University

15:15 – 15:40

Detection of Silent Data Corruption in Fault-Tolerant Distributed Systems on

Board Spacecraft

Muhammad Fayyaz and Tanya Vladimirova

University of Leicester

15:40 – 16:10 COFFEE BREAK

16:10 – 16:25 Concluding Remarks

Tanya Vladimirova, General Chair AHS-2014

17:00 – 20:00 Leaving Party at The Parcel Yard

19

FRIDAY, 18th

JULY, 2014

Venue: Lecture Theatre 1, Engineering Building Day Chair: Philippe Millet, Thales, France

08:30 – 09:00 Refreshments

FlexTiles: Self-Adaptive Heterogeneous Many-Core Technology Based on

Flexible Tiles

Workshop Associated with AHS 2014

9:00 – 10:45 Session 1

10:45 – 11:00 COFFEE BREAK

11:00 – 13:00 Session 2

20

FlexTiles Workshop at AHS-2014

½ day Workshop Associated with AHS 2014, Leicester

9am – 1pm, 18 July 2014

FlexTiles: Self-Adaptive Heterogeneous Many-Core Technology Based on Flexible

Tiles

Abstract

This workshop will present to AHS-2014 attendees, state-of-the-art technology related to many-core

platforms and will demonstrate a design methodology for the use of heterogeneous many-core

processors with self-adaptation capabilities, its virtualisation layer and its tool chain, ensuring

programming efficiency and low power consumption. Demonstrations of an Open Virtual Platform

simulator and an FPGA emulator will illustrate the capabilities of the FlexTiles heterogeneous many-

core platform.

The presentations will be given by FlexTiles partners, as follows:

First session (9:00 AM)

1. FlexTiles Project Overview: A Heterogeneous Many-Core Platform Based on 3D Stacked Chip

Technology and Programming Solutions

Philippe MILLET, Coordinator (Thales), 30'

2. 3-D Stacked Chip Technology and Strategies for Optimal Usage of Through Silicon Vias (TSV)

Romain LEMAIRE, (CEA Leti), 25’

3. FlexTiles Simulating Environment Based on Open Virtual Platform (OVP)

Stephan WERNER, (KIT) 25’

4. Low-Power DSP Accelerator Embedded in a Heterogeneous Many-Core Architecture.

Marc MORGAN,(CSEM) 25’

Coffee Break (10:45 AM)

Second Session (11:00 AM)

5. Dynamically Reconfigurable Embedded FPGA System

Antoine COURTAY, (UR1), 25’

6. Sample Application: Optical Flow Processing:

Invited Speaker, 30’

7. FPGA-Based Emulation of FlexTiles Platform

Fynn SCHWIEGELSHOHN, (RUB), 25’

8. Demonstration: OVP Simulation of the FlexTiles Platform

Stephan WERNER (KIT), 25’

21

1

3

1 2

Welcome Party: BBQ at the “Old Horse” at 18:30 on 14th

July, 2014

3

1

2 City Tour: Guided walk “The Story of Leicester” at 18:30 on 15

th July, 2014,

Start at the junction of New Walk and King Street

Start at the junction of New Walk and King Street Leaving Party at “The Parcel Yard” at 17:00 on 17th

July, 2014

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