PCI Express: The Evolution to 8.0 GT/s

Navraj Nandra, Director of MarketingMixed-Signal and Analog IP, Synopsys

PCIe Enterprise Computing MarketPCIe Enterprise Computing MarketTransition From Gen2 to Gen3

Gen3 transition will depend on the spec release but

Total PCIe instances. 2009 and beyond are

Gen 2 shipped with systems deployed in

2007 and 2008

The majority of Gen2 customers will move to Gen3 for more bandwidth in 2009

on the spec release, but major processor providers are expected to launch in 2010 with PDKs in 2009

estimates

Growth will continue for the Gen 1 connectivity

market

2003 2004 2005 2006 2007 2008 2009 2010 20112003 2004 2005 2006 2007 2008 2009 2010 2011

PCI Express 3 0 Key Dates (CY)Key Industry Q4 Q2 Q3 Q1Q4 Q2

PCI Express 3.0 Key Dates (CY)Q3 Q1 Q3 Q4 Q1 Q2y y

MilestonesQ

2007Q

2008Q3

2008Q

2009Q

2008Q

2009Q3

2007Q

2008Q3

2009Q

2009Q1

2010Q

2010

G 3

PCI Express 3.0 Speed Announced

Gen 3

PCI Express 3.0 Specification (0.7)

PCI Express 3.0 Specification (0.5)

PCI Express 3.0 Specification (0.9)

PCI Express 3.0 Specification () PIPE 3.0 Specification (0.5) p p f ()

PIPE 3.0 Specification (0.7)

ote: All future dates are estimates

PCI Express 3 0 (preliminary v0 5)PCIe Architecture Raw

Bit RateInterconnect Bandwidth

Bandwidth Lane Direction

Total Bandwidth for x16 link

PCI Express 3.0 (preliminary v0.5)

PCIe 1.1 2.5 GT/s 2 Gb/s ~250 MB/s ~8 GB/s

PCIe 2.0 5.0 GT/s 4 Gb/s ~500 MB/s ~16 GB/s

PCIe 3.0 8.0 GT/s 8 Gb/s ~1 GB/s ~32 GB/s

• PCIe 3 0 (Gen3) is 2x the bandwidth of Gen2• PCIe 3.0 (Gen3) is 2x the bandwidth of Gen2• @8 GT/s, the data Rate only provides 60% boost in Bandwidth

Uses a combination of Protocol and Encoding Changes for the additional 40%• Uses a combination of Protocol and Encoding Changes for the additional 40%• Use 128b/130b encoding on individual lanes

Use PHY la er packeti ation to identif packet bo ndaries• Use PHY layer packetization to identify packet boundaries• Removes the “K” codes

S bli l ( 8b/10b) t id d d it• Scrambling only (no 8b/10b) to provide edge density• Backwards compatible with previous PCIe generations

PCI Express 3 0 Areas of ChangePCI Express 3.0 Areas of Change

A li ti

Application

Transaction

Application

Link

TransactionDigital Controller

Link

PhysicalPhysical Interface

Physical

ElectricalElectrical

LogicalLogicalPIPE

Physical CodingS b l

Physical Interface(PIPE)

PCS Layer New Electrical Requirements

Mechanical

ElectricalElectrical Sub-layer

Electrical Sub-bl k

y New Electrical Requirements-Jitter-Sensitivity-Power

Rx TxLane

block

Lane

PCI Express 3.0PCI Express 3.0High Speed Transceiver

Key Features PCIe 3.0Data Rate 8.0 ± 300 ppm GbpsUnit Interval 124.9625 ps (min)

125.0375 ps (max)Encoding Scrambling only with 128/130 bit encodingEncoding Scrambling only with 128/130 bit encoding

Transmit Signaling:Diff ti l t t lt 1200 V ( )• Differential p-p output voltage

• DC common-mode voltage limits• Transition times (20% - 80%)

1200 mV (max)0 – 3.6 V18 ps

• Max total output jitter (p-p) 0.24 UI (TBD)

PCI Express 3 0PCI Express 3.0High Speed Transceiver

CKey Features PCIe 3.0Receive Signaling:• Receiver coupling AC (220 nF max)• Receiver coupling • Differential p-p input voltage (max)• Input transition times (20% - 80%)• Min jitter tolerance (p p)

AC (220 nF max)1200 mV (max)18 psTBD• Min jitter tolerance (p-p)

• Target BERTBD10-12

Equalization:TX 3-tap programmable equalization (pre, main and post)

Continuous Time Linear Equalizer (CTLE) RX recommended

PCI Express 3 0 Areas of ChangePCI Express 3.0 Areas of Change

A li ti

Application

Transaction

Application

Link

TransactionDigital Controller

Link

PhysicalPhysical Interface

Physical

New Requirements32 bit support

ElectricalElectrical

LogicalLogicalPIPE

Physical CodingS b l

Physical Interface(PIPE)

PCS Layer

- 32-bit support- Equalization

Mechanical

ElectricalElectrical Sub-layer

Electrical S b bl k

y

Rx TxLane

Sub-block

Lane

New PIPE 3 0 (v0 5) InterfaceNew PIPE 3.0 (v0.5) InterfacePCI Express Mode PCLK Data Width

2.5 GT/s 250 MHz 8 bits2.5 GT/s 125 MHz 16 bits5.0 GT/s 500 MHz 8 bits5.0 GT/s 250 MHz 16 bits5.0 GT/s 125 MHz 32 bits8.0 GT/s 1000 MHz 8 bits8 0 GT/s 500 MHz 16 bits

E t d d f G 3 b t till t

8.0 GT/s 500 MHz 16 bits8.0 GT/s 250 MHz 32 bits

• Extended for Gen3, but still supports:– Variable clock – Variable data

• New 32-bit data width supported for Gen2/Gen3

PCI Express 3 0 Areas of ChangePCI Express 3.0 Areas of Change

A li ti

Application

Digital Controller will have

Transaction

Application

Link

TransactionDigital Controller

Digital Controller will have to handle 2x data: - Change LTSSM - Double the data path

Double the clockLink

PhysicalPhysical Interface

Physical- Double the clock- Removal of “K” codes

ElectricalElectrical

LogicalLogicalPIPE

Physical CodingS b l

Physical Interface(PIPE)

PCS Layer

Mechanical

ElectricalElectrical Sub-layer

Electrical S b bl k

y

Rx TxLane

Sub-block

Lane

SSummary

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Complete DesignWare IP SolutionComplete DesignWare IP Solutionfor PCI Express 3.0

• Complete solution: controllers, PHY, VIP• Doubles data transfer speed to 8.0 GT/s• Backwards compatible with PCIe 1 1 and 2 0

Complete PCI Express 3.0IP Solution

• Backwards compatible with PCIe 1.1 and 2.0• Comprehensive suite of digital controllers

– Endpoint, Root Complex, Dual Mode

• Endpoint• Root port• Dual Mode

S it h/B id

• Endpoint• Root port• Dual Mode

S it h/B id

DigitalDigitalControllersControllers

(RC/EP), Switch and Bridge, SR-IOV– Internal data path options of 32, 64 &128– Support for x1 x2 x4 x8 and x16

• Switch/Bridge• Switch/Bridge

• 3.0* (8.0 Gb/s)• 3.0* (8.0 Gb/s) Support for x1, x2, x4, x8 and x16– AMBA® 3 AXI™ Bridge and AMBA 2 AHB™

BridgeR b t PHY IP i D l t

• 2.0 (5.0 Gb/s)• 1.1 (2.5 Gb/s)• 2.0 (5.0 Gb/s)• 1.1 (2.5 Gb/s)

PHYPHY

• Robust PHY IP in Development– Will meet final PCIe 3.0 specs in areas such

as jitter, margin, receive sensitivity• Master• Slave• Monitor

• Master• Slave• Monitor

Verification IPVerification IP– Advanced built-in diagnostics and ATE

capabilities

• Monitor • Monitor

Note: PCI Express 3.0 specification is currently at 3.0. All DesignWare IP is currently under development

Thank youy

• Explore more about Synopsys DesignWare IP at ChipEstimate.comExplore more about Synopsys DesignWare IP at ChipEstimate.com

Use IP specific to Synopsys to plan your next chip!• Use IP specific to Synopsys to plan your next chip!

• Please stay and talk with Navraj Nandra

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