PCI Express Base Specification Revision 2djm202/pdf/... · pci express base specification, rev. 2.0 9
PCI Express Switch
description
Transcript of PCI Express Switch
HS/DSL ProjectHS/DSL Project
Yael Grossman Arik Krantz
Implementation and Synthesis of a 3-Port PCI-
Express Switch
Supervisor: Mony Orbach
Project SpecificationsProject Specifications
We will implement:
3 - port switch for PCI-Express 1 upstream, 2 downstream full-duplex ports Up to 2.5 Gbit/sec transfer rate CRC support at the DLL layer Independent packet handling per port Packet routing between ports through
lookup tables
Send Queue 1 and 2 (SQ1, SQ2)
Contain packets routed to current port from the other twoswitch ports. We have one buffer for each queue in orderto prevent simultaneous memory write.
ACK/NACK Queue (ACKQ)Used to store DLLPs for each received TLP while they await sending.
Replay Buffer (RB)Contains all the packets that have been sent on the outgoing queue
and have not yet received an ACK.
Send/Receive PipelinesIncludes logic for incoming and outgoing packets.
Routing MechanismIncludes an independent copy of the routing table.
Local/Global MechanismsLocal/Global Mechanisms
Packet Storage in Common Memory SpaceEnables fast packet forwarding between ports
Global Initialization at Boot TimeInitialize routing tables with system layout.
Local
Global
Receive FlowReceive Flow
This mechanism is applied per port.
It displays the sequence of actions that the switch executes on a received packet.
Packet is received on incoming lane
Packet type is determined and CRC check is performed
According to packet type (DLLP or TLP), we take appropriate action.
CRC Logic Block
CLK
Address Addr
Route Packet and
enqueue
ACK/NACK Send Logic
Valid
Addr
CLK
RB Logic
Chosen_Buffer
Addr-TLP
IsTLP
Valid
IsTLP
NTS4
Addr4
Addr3
NTS3
CRC Logic Block
Route packet
and Enqueue
(TLPs)
Continue
ACK/NACK Send Logic(TLPs)
ReplayBuffer Logic
(DLLPs)
Return
TLP_CRC
DLLP_CRC
IsTLPCheck if
TLP/DLLP
Valid
Valid
Valid IsTLP Description 1 1 Packet is valid TLP 1 0 Packet is valid DLLP 0 1 Packet is invalid TLP 0 0 Packet is invalid DLLP / unrecognized
Valid
IsTLP
Addr
* Valid and IsTlp default to 0.
EN
EN
CRC Logic Block
Return
Decide Outgoing Port
Addr
Valid
IsTLP
Write to SQ_1
Write to SQ_2
EN_1
EN_2
Routing Logic BlockLogic block executed by global routing mechanism
Return
Construct DLLP Packet
IsTLP
Valid
Addr
Replace type-bit in packet with
Valid’
Write to ACKQ
ENEN
ACK/NACK Block
Addr
NTS3
Return
Addr
Replay Buffer Logic Block
\2
Addr-TLP
Enable
Control
Chosen_Buffer
Resend Buffer
Remove Addresses from RB
Add Address
to RB
ACK/NACK
Addr
IsTLP
Valid
ACK/NACK
\2
Addr
Addr
Addr
Addr4
NTS4
Decide on action
according to DLLP type, validity and
chosen buffer
En A/N Ch_Buf Control 0 X 10,11 00 – Do Nothing 0 X 00,01 11 – Add Address to RB 1 1 10,11 01 – Remove Address from RB 1 1 00,01 Split CLK: rising – address removal, falling – address addition 1 0 10,11 10 – Resend Buffer 1 0 00,01 Split CLK: rising – address sending, falling – address addition
Enable1 if the signal is a correct DLLP.
Chosen_Buffer00,01 – Add Addr_TLP to RB.Else – ignore.
Control00 – Do Nothing01 – Remove Address from RB10 – Resend Buffer11 – Add Address to RB
Send FlowSend Flow
This mechanism is applied per port.
It displays the sequence of actions that the switch executes in order to send a packet on the outgoing lane.
The switch contains 4 buffers with packets to be sent: SQ1, SQ2, ACKQ and the Replay Buffer.
It will decide from which buffer to select the packet to be sent (if they aren’t empty), and send it on the outgoing lane.
SQ_1
SQ_2
ACKQ
RB Logic
Addr1
NTS1
Addr2
NTS2
Addr3
NTS3
Addr4
NTS4
Arbitration Logic
NTS – Need To Send
\2Chosen_Buffer
\2Chosen_Buffer
\2Chosen_Buffer
Address_to_Store
Addr-TLP
Valid+TLP \2
Addr
Valid+TLP \2Addr
Valid+TLP \2Addr_2
Valid+TLP \2Addr_1
Completed TasksCompleted Tasks
Detailed design Data flow diagram (transmitter/ receiver) for ports Queue and buffer structure for ports Packet handling algorithms
System block design Completed most of higher-level block design Work in progress on lower-level blocks
Preparation for VHDL coding Learned to work with HDL designer Learned VHDL (basic level)
Semester PlanSemester Plan
Complete design for all sub-blocks 3 weeks Routing/lookup table mechanism Arbitration logic Send Queue implementation Concurrency issues in queue access Deal with unresolved issues such as:
- Interaction with Physical Layer
- Understand memory segmentation
VHDL design 1 week Division of the system into interconnected entities Definition of appropriate architecture per entity Preparation for VHDL implementation
Exam period break… 4 weeks
VHDL design 1 week …continue design (and start coding).