PCI Express Toolsmaterias.fi.uba.ar/6644/info/varios/PCI Express Tools.pdfperformance is certainly...

PCI Express Tools

From the Physical Layer to a Fully Operating System

2 For more information on PCI Express tools visit www.agilent.com/find/pci_express

The increase in required system performance is certainly not over. The expected 1000-fold improvementin the Internet’s performance alonewill require systems with capabilitiesbeyond what existing buses (ex. PCI or PCI-X) can provide. When CPUspeeds exceed 10 GHz, gigabitnetworking becomes commonplace,and consumers finally demand high-performance graphics andvideo, existing bus options will be inadequate.

Many high-speed interconnecttechnologies are being proposed for use in computer server anddesktop systems, but PCI Express is perhaps the most attractive. With an application interface that is consistent with previous PCIimplementations, PCI Express allowsyou to move existing applicationsand drivers to the next generation ofperformance without rewriting code.

However, it is not possible to achievethe required performance usingexisting parallel-bus approaches

without overcoming a signal integritynightmare. Therefore, an entirelynew physical layer is required. PCIExpress is based on a 2.5-Gbps serial channel in contrast to the33/133-MHz multidrop parallelPCI/PCI-X buses. PCI Express canemploy up to 32 lanes to pushperformance up to 80 Gbps.Therefore, you must learn newphysical, data link, and transactionlayers to implement a system basedon PCI Express.

The serial approach makes signalintegrity challenges manageablewhile providing a scalable level ofperformance by allowing multiplelane deployment. But the serial PCIExpress point-to-point architecturealso creates complications. A switchmust be used to implement multipleboards to emulate a parallel bus.

Agilent Technologies has beendeeply involved in the PCI bus sinceit was first proposed. As a memberof the PCI-SIG, Agilent is continuingits involvement in the developmentof PCI Express and provides thesolutions you need as PCI Expressmoves into reality.

Physical Layer

With PCI Express, interoperabilitystarts at the physical layer.Development of a PCI Express-basedsystem includes modeling andsimulations, but you eventually needto create hardware. You need tovalidate the integrity of the physicallayer and ensure that reflections,crosstalk, emissions, and othereffects are within allowable limits.Time-domain reflectometry (TDR)oscilloscopes and multiport vectornetwork analyzers (VNAs) are ideal

tools for evaluating the signalintegrity of transmission lines formedwithin printed circuit boards, andwith cables and connectors. Eachsignal path must be measured toidentify impedance discontinuitiesand losses that might render a signal path useless. Beyond testingsignal paths, you must also checklane-to-lane skew, analyze jitter, andmeasure drive strength and receivertolerance. The logical sub-block of the physical layer includes linkinitialization and training that mustbe validated prior to moving data.

The Agilent Infiniium DSO80000Series 13 GHz real-time oscilloscopeoffers up to 40 GSa/s with 2M ofmemory. The 12 GHz 1169AInfiniiMax active differential andsingle-ended probes offerunsurpassed performance, accuracyand connectivity for real-time signalintegrity measurement of the PCIExpress physical layer. The flexiblearchitecture of the InfiniiMax activeprobes allow you to makemeasurements with a hand heldbrowser, solder in, socketed or SMAconnection for both differential, aswell as single-ended measurements.

The Agilent 86100B digital communi-cations analyzer has the bandwidthand TDR functions you need to perform these measurements.The Agilent physical-layer testsystems, based on a VNA, are verypowerful tools for characterizingsignal paths and creatingtime-domain waveforms of highaccuracy and resolution. TheAgilent 81133/34A 3.35-GHzpulse/pattern generator is ideal for PCI Express driver and receiver validation.

CONFIG/OS

SOFTWARE & DRIVERS

PCI Express is new from here on down

No changes here.

No impact on existing

PCI software or drivers.

Future performance

gains will impact

this layer only.

TRANSACTION

DATA LINK

PHYSICAL

Figure 1. PCI Express layeredarchitecture enables modularity,scalability and re-use.

We’re There for Your Evolving PCI Express Needs

Data Link Layer

The data link layer ensures that datais reliably delivered to its destinationvia the PCI Express link. The majorgoal of the data link layer is dataintegrity. Once the physical layer isvalidated, the data link layer must bevalidated. Because PCI Express addsa sequence number and CRC to thetransaction-layer packet, validatingthe data link layer is not trivial. It isnecessary to use capable test toolsthat will allow you to monitor datamovement and provide consistentstress to fully test the data link.

PCI Express includes a flow-controlprotocol to ensure that packets areonly transmitted when there isbuffer space to receive them. This isintended to reduce the number ofpacket resends due to bufferoverruns. It is important to measurethe implementation of the optimizedbuffer depth (and performance),virtual lane correctness, CRCoperation, link training, and properflow control. An Agilent 16900Series logic analysis system with a

packet analysis probe will ease theprocess by allowing you to trace linktraffic at the protocol level with afully decoded packet display andpacket triggering.

PCI Express exerciser and protocolanalyzer solutions from Agilent assistyour development of silicon, add-incards, servers, and workstations.Their modular and flexiblearchitectures allow for continuousfeature upgrades. These tools can beused for functional validation,exercising protocol variations, errorinsertion, automated compliancetests, device emulation, stress testing,generating and receiving maximum-bandwidth traffic, protocolobservation, and emulating multiplestreams and virtual lanes. Theyprovide comprehensive test coveragewith repeatable and deterministictest scenarios.

Transaction Layer

The transaction layer receives readand write requests from the

application software in the sameway as PCI and PCI-X. All of theserequests are implemented as splittransactions, and some of therequest packets require acorresponding response packet.Also, the transaction layer receives response packets and hasto match these with the appropriaterequest packets (each packet has aunique identifier that enablesresponse packets to be directed tothe correct originator). Packets haveattributes that may be used tooptimally route these packetsthrough the I/O subsystem.

Such a complex transaction layercan be debugged and validated withthe Agilent 16900 Series logicanalysis system with a packetanalysis probe. The E2960 Seriesprovides the industry’s first full-speed x1, x2, x4 and x8 combinedexerciser-analyzer platform, whichprovides R&D and QA engineerswith bring-up, debug and validationcapabilities to test and validatehardware and software designs.

The traffic flowing over PCI Expresslinks almost always comes from andgoes to other buses, such as the CPUfront side bus, memory, InfiniBand,PCI and PCI-X, Serial ATA, AGP 3.0,and other I/O buses. The ability tosimultaneously trace activity onthese buses as well as PCI Expressis crucial when validating thecomplete system. The Agilent 16900Series logic analysis systems providesupport for virtually every bus inthe system, making it easy to followtransactions, data and packets asthey flow through the system. Thesystem performance analysis (SPA)tool set identifies elusive bottlenecksso you can optimize systemparameters and architecture.

For more information on PCI Express tools visit www.agilent.com/find/pci_express 3

PhysicalLayer

Data LinkLayer

TransactionLayer

LOGIC ANALYZER

EXERCISER

ParBERTPULSE

PATTERNGENERATOR

PROTOCOL ANALYZER

TDR

VNA

OSCILLOSCOPES

Figure 2. Agilent offers test tools for PCI Express physical, data link,and transaction layers.


High-speed system design startswith the physical structure. PCI Express data rates areequivalent to sending microwavesignals through copper structures.First-pass success demands asystematic approach to design andvalidation. Microwave engineershave addressed similar designchallenges by breaking down the system to model eachcomponent separately, then together as a complete channel.

Accurate simulations requireaccurate component models. Youcan modify existing models or relyon supplied libraries but the mostaccurate method is to measureactual components. Measurement-based models increase yourconfidence by providing real-worlddata to your time domain orfrequency domain simulator.

Each channel must handle datarates in excess of 2.5 Gbit/sec toensure sufficient margins to coverfor manufacturing and processvariations, connector wear andsilicon aging. A good rule of thumbis 10-25% margins.

Characterize your design andextract models with either a TDR (time domain reflectometer) or a 4-port VNA (vector networkanalyzer). Both offer advantages and produce similar results. TDRs are more affordable and oftenfamiliar while VNAs are capable ofmore accurate and traceable results.

Physical Layer Design, Validation and Modeling

Physical Layer

Figure 3. Both the TDR and VNA provide accurate results of the PCI Expressphysical layer.

Application Typical Recommended Measurements Solution(s)

PCI Express Component Build, validate and PLTS w/VNADevelopment de-embed test fixture

Complete characterizationData export to model extraction & analysis products

Incoming Inspection Validate vendor-supplied PLTS w/TDRof PCI Express component samples PLTS w/PNA or ENA aloneComponents Model extraction for system

simulation

System Validation Complete validation of your PLTS w/TDR or VNAPCI Express channel; including SDD21 and SDD11 measurements

One Time Measurement Extract channel or Model Extraction ServicesNeed device models from Agilent Technologies

Validate PCI Express (see pages 12 and 13)conformance

Table 1. PCI Express Physical Layer Test Solutions.


The Agilent TDR/TDT

A TDR combines a samplingoscilloscope with a step generatorcapable of launching a fast edge intothe device under test (DUT). Thereflected wave (TDR) displaysimpedance discontinuities throughthe structure of the device. Thetransmitted wave (TDT) enables you to measure system loss andpropagation delay.

To obtain greater accuracy, useTDR/TDT Normalization.Normalization goes beyondtraditional vertical and time basecalibrations to remove electricaldelay and loss of your cable frommeasurement results.

The Agilent 86100B Infiniium digitalcommunications analyzer (DCA),and 54754A differential time domainreflectometer module are intuitive

tools for debug, analysis and model extraction. Oscilloscopemeasurements and eye diagrams are available when the TDR isturned off. Excess inductance and capacitance measurementsdetermine the location andmagnitude of discontinuities.

The Agilent 4-Port Vector NetworkAnalyzer (VNA)

A VNA uses stimulus/response tocharacterize the DUT. A sine wave is transmitted into the DUT whiletuned receivers are swept inlockstep, providing both reflectionand transmission properties. VNAs offer greater measurementresolution and accuracy than a TDR through calibration and fixtureremoval techniques that have beenrefined through years of demandingmicrowave applications. VNA results

are calibrated using frequencydomain artifacts — eachmeasurement is accurate, repeatableand traceable to industry standards.

VNA measurements are usuallyexpressed as Scattering Parameters(or S-Parameters) which can betranslated into time-domain views.S-Parameters are well established asthe best technique to characterizethe manner in which a PCIcomponent modifies a digital signal.

The Agilent Physical Layer Test System

The physical layer test system(PLTS) provides confidence throughcomplete characterization andmodel extraction of your DUT. PLTS supports both the TDR andVNA measurement platforms,providing instrument controlincluding setup, error correction,acquisition, analysis and datatransfer – thus reducing the difficultand time-consuming process ofmeasuring differential structures toa few keystrokes and reducing thechance of error.

PCI Express requires characterizationof input differential insertion andloss and near/far end crosstalk.PLTS provides direct measurementof insertion and return loss, as wellas mode conversion analysis, whichis used to determine cross-talk.

Guided setup and calibrationmethodologies ensure that the datayou capture accurately reflects yourDUT. Export VNA or TDR data tosimulators that accept S-Parametersor to TDA Systems IConnect modelextraction and analysis software.

DEVICE UNDER

TEST

DEVICE UNDER

TEST

AGILENT TECHNOLOGIES N1900-SERIES

PHYSICAL LAYER TEST SYSTEM

AGILENT TECHNOLOGIES PNA SERIES

VECTOR NETWORK ANALYZERS

AGILENT TECHNOLOGIES 86100-SERIES

TIME DOMAIN REFLECTOMETERS

S-PARAMETERS TIME DOMAIN DATA

Figure 4. The Agilent PLTS enables you to control, measure andcompare data from both TDR and VNAs.


Oscilloscopes and Probes

The jitter budget for TJ for PCIExpress signals is small – on theorder of 87 ps (BER 10–6) maximumunder the 1.1 specification. Anoscilloscope with low trigger jitterand jitter noise floor is essential tocharacterize the true jitter margin.The trigger jitter of the DSO80000Series is < 0.5 ps rms and the jittermeasurement noise floor for timeinterval error measurements is aslow as < 0.65 ps rms.

With PCI Express, you often onlywant to use as much bandwidth asnecessary and with the AgilentDSO80000 Series you have theoptional capability to utilize the full40 GSa/s sample rate in a proprietarynoise reduction mode that allowsthe scope to have a lower overallbandwidth coupled with an evenlower DSP reduced noise floor. Thiscan provide you with a much moreaccurate measurement in systemswhere vertical noise is an issue.

Figure 5. The Agilent DSO80000 Seriesoscilloscopes and InfiniiMax Seriesprobes deliver a high-performance,13 GHz, end-to-end measurement system.

Data Link Layer

Physical Layer

The Agilent Infiniium DSO80000Series oscilloscope system providesunmatched accuracy, performanceand connectivity for signal integritymeasurements on PCI Expresssignals. It offers up to 13-GHzbandwidth with two channels, eachsampling at 40 GSa/s with 2 M of memory. The award-winningInfiniiMax 13 GHz active differentialand single-ended probe systemoffers connection flexibility, withhand held browsers, solder in,socketed and SMA connections. PCI Express signals haveapproximate rise and fall times of125 ps, which requires a minimum6 GHz bandwidth and 20 GSa/ssampling rate essential for accuratemeasurements of rise times and eye opening.


Probing PCI Express signals on aprinted circuit board or IC packageis extremely challenging, becausethe PCI Express signals are highspeed and are differential. TheAgilent 1169A 13-GHz InfiniiMaxdifferential probe system ensuresaccurate differential measurementswith a 12 GHz system bandwidthand flat response at the probe tip.The DSO801304A scope and 1169Aactive differential probe can be usedto measure the following parametersspecified in the PCI ExpressPhysical Layer Specification:

Unit interval

Differential peak-to-peak output voltage

Minimum TX (transmitted) eye width

Maximum time between the jittermedian and maximum deviationfrom the median

D+/D- (differential plus/differentialminus) TX output rise/fall time

ac peak common mode output voltage

Absolute delta between dc commonmode during LO and electrical idle

Absolute delta between dc commonmode between D+ and D-

Electrical idle differential peakoutput voltage

Amount of common mode voltagechange allowed during receiverdetection

Minimum time spent in electrical idle.

The Agilent Technologies N5393APCI Express electrical performancevalidation and compliance softwareprovides you with a fast and easyway to verify and debug your PCIExpress designs. The N5393A PCIExpress electrical test softwareutilizes the clock recovery methodused in the official PCI-SIG SignalQuality Test Methodology (“SigTest”)application, ensuring that your testresults are consistent with resultsfrom the SigTest application. TheN5393A requires the E2688A serialdata analysis software and one ofthe PCI-SIG approved compliancetest fixtures (CBB or CLB).

Features:Test setup wizard guides youthrough test selection, configuration,connection, execution, and resultsreporting.

PCI-SIG SigTest clock recoveryalgorithm is used to ensureconsistency with SigTest.

Measurement connection setups aredisplayed when you must change thetest setup.

Oscilloscope setup is automaticallyconfigured for each test.

Test results report formallydocuments your test configuration,measurements made, pass/failstatus, and waveforms.

Pass/fail margin analysis providesan indication of how close yourdevice is to meeting a testspecification.

The Agilent E2688A serial dataanalysis package for the Infiniiumreal-time oscilloscope offers clockrecovery and mask templates for PCIExpress, as well as other popularserial buses, such as Serial ATA,Fibre Channel and Gigabit Ethernet.The E2688A allows you to easilyperform pass/fail mask testing onthe PCI Express physical layer.

PCI-Express 1.1 Testing

Testing of PCI Express under the 1.1 revision requires the use of aclean clock source. For testing add-incards a 1.1 compatible CBB with aclean clock oscillator is availablefrom the PCI-SIG. In addition, jittermeasurements using this version of the CBB are made using a clockrecovery function specified as a firstorder PLL response with a cornerfrequency at 1.5 MHz.

PLL Loop bandwidth tests foradd-in cards can also be made withthis board using an Agilent E4440Aspectrum analyzer and an E8267DPSG vector signal generator.

For lower speed reference clocktesting, the DSO80000 Seriessupports a very long memorycapture of up to 64 M points. Agilentrecommends using 4 GSa/s samplerate to capture 2 GHz of bandwidthfor this signal. This gives youexcellent spectral data to perform thenecessary band pass filtering requiredfor the phase jitter measurement.

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Validating the receiver side of PCI Express designs is often more challenging than testing the transmitter side. With an Agilent 81134A pulse/patterngenerator, signals and datasequences or test sequences can be generated that stimulate the PCI Express device under test(DUT). This DUT, in turn, responds by outputting a similarsequence–the bit flow of the answeris predictable and can be measuredby a logic analyzer. This behaviorcan be used to characterize thereceiver input performance.

The training sequence can be sent as a clean signal or with stressapplied to it. For functional testing,the 81134A pulse/pattern generatorprovides clean signals with lownoise and low jitter, exceeding theminimum requirements defined inthe PCI Express standard. Stressmeasurements are made by reducing the levels/swing below the minimum requirements of thereceiver. The Agilent 81134A, incombination with a functiongenerator, generate the stress. Fortesting PCI Express x4, x8, and x16,the scalable 81250 ParBERTplatform is the ideal solution formaking functional and stress testson multiple channels (up to 64 channels).

Pulse/Pattern Generator

Figure 6. Generate training sequences with or without stress for driver andreceiver validation.

Description Measure Equipment Compliance

Receiver voltage Application of Pulse/pattern RX eye training sequence, generator, logic detection of answer analyzer

Jitter outlier Eye modulation Same as above plus Jitter budget, (Tolerance) function generator section 4.3.4

Common mode Common mode Same as above Common mode noise noise < 100 mV, section 4.3.4

Crosstalk on idle Single-ended noise Same as above Noise < 65 mV, section 4.3.3

Delay between Multiple lane ParBERT 81250 < 20 ns any lane lanes stimulus per port

Table 2. The Agilent 81134A pulse/pattern generator enables design validationand compliance measurements at the receiver.

Data Link Layer

Physical Layer

Increasing speed rate for PCIExpress II is driving designs to newdimensions. Validating and testing of PCI Express devices at thephysical layer is getting more andmore challenging for today’sengineers.

The important test requirement ismeasuring BER on the PCI Express I/O ports. The PCI Express designworks in loopback mode forcharacterization. The AgilentParBERT 81250 platform providesstandard compliant trainingsequences, compliance patterns andSKP frames to stimulate PCIExpress design. The bit flow can becontrolled and combined by theParBERT sequence editor to acomplex data flow including looplevel control.

For testing and validating the PCIExpress receiver site, the ParBERT81250 is able to provide a very clean data signal with low noise and jitter. Conversely, ParBERT isflexible in creating a differential de-emphasized data signal includinglarge eye closure by jittermodulation. For data analysis,ParBERT provides differentialconnectivity and CDR. The ParBERT81250, in combination with afunction generator, can modulate adefined jitter amplitude to testminimum receiver eye widthcharacteristics and jitter tolerancemeasurements. Spread spectrumclocking is achieved by frequencymodulation of clock and data. Fortesting PCI Express x4, x8 and x16,multiple stimulus channels can beconfigured for functional and stresstest on multiple channels.


Parallel Bit Error Ratio Tester

Data Link Layer

Physical Layer

Required feature set Compliance / test need

Differential de-emphasis RX data detectionTSI, TS2, SKP, compliance patterns

Jitter modulation Minimum detectable eye width jitter tolerance

Frequency modulation @ clock/data Spread spectrum clocking (SSC)

Multiple lane stimulus Measure delay between Lanes x4,x8,x16

Sequence editor to generate Set device into loopback modePCI Express training sequences

Differential analysis with CDR BER measurement

Speed rate up to 7 Gbit/s Support for PCI II

Table 3.

Figure 7. De-emphasizedsignal with jittermodulation.

Figure 8. Multi channel ParBERTsystem generates training sequencesand controls PCI express into loopbackmode for standard compliancemeasurements.


Protocol Analyzer and Protocol Exerciser

Can act as an end-node (for platformtesting) or act as a root-complex (foradd-in card testing)Emulation of configuration space ofa switchCompliance test capabilitiesLAN interface for remote control

The Agilent E2960-A08 protocolanalyzer provides non-intrusivemonitoring of captured PCI Expresstraffic between an adapter card anda system or between an external PCI Express device and a system. It is involved in bring-up and debug of PCI Express designs andincludes an intuitive graphical userinterface with search and displayfilter capabilities.

Link training analysis, root causeanalysis and troubleshoot problemsPatented “Dynamic Trigger

Conditions” for simplified triggeringon sophisticated transactions(Dynamic pattern terms is apatented technology that allows the user to trigger on a certain partof a packet where the content isdetermined at runtime) Protocol exerciser as controlled endnode stimulus to complementprotocol analyzer — all in one frameHierarchical views (byte / packet /transaction)LAN interface for remote controland to share applicationsCaptures data link layer packets andtransaction layer packetsBi-directional, interleaved display,including time-stampsDedicated PCI Express trigger andstorage qualification

Transaction Layer

Data Link Layer

The new Agilent Technologiessystem protocol tester is comprisedof a protocol analyzer and protocolexerciser for PCI Express. The toolsenable users to exercise and analyzebus protocols on the data link andtransaction layers and providebring-up, debug, validation andcompliance testing capabilities. They are ideal tools for R&D and QA engineers who are developinghardware and software designs for PCI Express systems spanningthe entire computer industry,including semiconductors, chips,motherboards, BIOS, drivers, servers and add-in cards.

“Support for PCI Express x8technology will acceleratedevelopment of enterprise systemsand adapters enabled by the serialI/O technology,” said Jim Pappas,director of initiative marketing,Intel Enterprise Platform Group.“The demonstrations at the PCI SIG Developers Conference andAgilent’s aggressive delivery of PCI Express testing suites areimportant steps for the industry.”

The Agilent E2960-E08 protocolexerciser is used to test and validatex1, x2, x4 or x8 PCI Express designs.It can interactively generate andrespond to arbitrary transactions as well as test corner cases andbehavior by inserting errorconditions and protocol violationsand monitor the system in responseto these errors.

Command Application ProgrammingInterface (CAPI) for automatedtesting (C++ and TCL programminginterfaces)Error insertion

Figure 9. The system protocol testerprovides increased test coverage forhigher test quality, reducing the riskof costly recalls and redesigns andfaster test times, enabling fastertime-to-market.

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The Agilent E2969A protocol testcard performs tests to verify andensure compliance with PCI Expressas defined by the PCI-SIG. Inaddition, the card also guaranteesthe interoperability of the DUT with other PCI Express devices. It is primarily for use by R&Dengineers who wish to validate the functional compliance of their PCI Express-based designs,including chips, add-in cards or systems.

The E2969A protocol test card is a collaborative developmentbetween Agilent and Intel thatcoincides with the Intel productdevelopment solution for the PCI Express market.

Automated pre-programmedcompliance tests for the transactionand data link layerTests power management andconfiguration spaceCarefully monitors the behavior ofthe DUT in response to certain errorconditionsConnection to protocol analyzerKnown endpoint and switchfunctionalityField upgradeable FPGA-based cardUSB 2.0 interface for programmingand topology simulation modeSupports add-in cards with up tox16 lane widthCan act either as a PCI Expressstandalone add- in card, or as a PCI Express interposer card for x1 operationCard controlled via PCI Express or via an external host

Protocol Compliance Test Card

Transaction Layer

Data Link Layer

The protocol test card providesthree test modes. During the add-in card test mode, the card isplugged in between the system andthe add-in card. It monitors thebehavior of the add-in card, itsdevice drivers and operating systemin response to a range of insertederrors. The platform test modemonitors the behavior of theplatform, its device drivers and OS, also in response to various

error conditions. During the topology simulation mode, the protocol test card appears as a complex PCI Express topology. It aids in verifying the PCI Expresscompliance of the BIOS, so that it is able to detect and initialize acomplex PCI Express topology.

Figure 10. Easily validate the functional compliance of your PCI Express-baseddesigns with the E2969A protocol test card.

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Logic Analysis System

Proper system validation underscoresthe need for full system visibility.The traffic flowing over PCI Expresslinks usually travels to and fromother buses, such as the CPU frontside bus, memory, InfiniBand, PCIand PCI-X, Serial ATA, and AGP 3.0.The ability to simultaneously traceactivity on these buses, as well as PCI Express, is crucial whenvalidating the complete system.

The N4220B packet analysis probecaptures PCI Express traffic and,coupled with a 16900 Seriesmainframe and the 16950A or16753/54/55/56A logic analyzermodules, provides triggering, cross-correlation, and detailedmeasurements for complete PCI Express system hardware and software debugging.

The PCI Express architecture isscalable and extensible, and includesa rich set of features. It supportsmultiple interconnect options, such asthe slot connection and chip-to-chipinterconnect. PCI Express has avariety of link widths from x1through x16. These bus features, inaddition to the heavy protocol natureof PCI Express, require the ability toset up your traces, your triggers andyour packet view of the traffic onthe link at the protocol level.

PCI Express has many interestingfeatures that require validation atthe various layers. Common areasfor investigation include squelchmode, power-down mode, decode ofthe 10b codes to 8b traffic, variouslink training sequences, differentkinds of packets, spread spectrum clocking, and data scrambling

employed to reduce EMI emissionsfrom PCI Express implementations.

Traditionally a logic analyzer hasbeen used to look into multiplepoints in a complete system so it canperform all of the measurements thatyou need for full validation. Due tothe serial nature of PCI Express, thelogic analyzer must now handle notonly the traditional parallel commonclock and source synchronous clockbuses, but also these very high-speed,multi-lane, packet-oriented,embedded clock serial buses.

The first major challenge encounteredwhile probing PCI Express is thephysical access to the signals. Whenyou are doing point-to-pointconnections between chips, it

becomes necessary to physicallyprobe the traces that go between the chips. Agilent’s new soft touchconnectorless probing technologyhelps overcome this challenge. Withextremely low loading, soft touchprovides a space-saving, pre-definedprinted circuit board footprint youcan design into your board. TheAgilent soft touch probe for PCIExpress uses light compressiontechnology on the exposed area ofyour circuit board and picks up thesignals as they travel from chip tochip. When a footprint isn’t available,the Agilent N4221F flying lead probeset allows you to probe a chip-to-chiplink up to x16 without a midbusfootprint. For developers of PCIExpress slot connectors, a lowintrusion interposer is also available.

Transaction Layer

Data Link Layer

Figure 11. Achieve low loading (<0.7 pF), an easy connection and a smallfootprint with soft touch connectorless probes.


The nature of PCI Express protocolalso adds to the validationcomplexity. The PCI Express trafficon the bus consists of encodedpackets that are placed into serial bitstreams with data scrambling andspread spectrum clocks. It’s essentialthat the logic analyzer removes all ofthat complexity from the trigger setup.

The Agilent N4220B Series packetanalysis probes provide you anintuitive GUI (graphical userinterface) so you can quickly and

easily define the different kinds ofPCI Express packets. You can selectthe kind of packet you want thelogic analyzer to look for to help youexamine the link operation in realtime and identify that packet whenit crosses the link.

The final step in validating your PCI Express system is to actuallyview the trace results. The Agilent N4220B Series of analysis

Figure 13. Optimize your PCI Expressvalidation efforts with a low-intrusion,easy-to-use packet analysis probe.

Figure 12. With L0s power management mode, bit lock is acquired in 48 symbols (192 ns) the fastest in the industry, andcritical for L0s’ capture.

probes includes a software packetdecode that handles format details,including lane deskew, datascrambling and data format. Theability to view raw 8b and/or 10b codes is still retained. Thiscomplements the packet analysiscapability Agilent provides for otherbuses, such as serial ATA andInfiniBand, but is even more powerful due to the wide-lane feature of PCI Express.


Test and Measurement Engineering Services

Agilent offers a comprehensive setof services to help accelerate yourtime to market and ensure thesuccessful development of your PCI Express design. Gain quickaccess to Agilent’s experts andnewest technologies. Tap into a deep well of expertise and toolsgleaned from Agilent’s 60 years oftest and measurement experience.Whether you want to outsource your test, build your in-house testcapability, get help with testplanning, or just learn more aboutPCI Express, Agilent is ready towork for you.

Physical Layer

Protocol Layer

Figure 14. You will benefit from a wide variety of tools and broad expertisewhen you use Agilent's measurement services.

Technology Training

Ramp up on PCI Express quickly. If you are responsible for validation,debug or compliance testing, our PCI Express training courses willhelp you succeed. After completionof the course you will have masteryof the PCI Express specification andyou’ll be equipped to develop yourproduct test plan.

Test Plan Development

As you push the envelope onproduct development, design andplanning for test is paramount.Agilent’s knowledge and expertisecan help ensure you’re ready.

Agilent’s Product Training andApplication Services

Agilent’s broad range of serviceswill help you get the most out ofyour PCI Express development tools.Our flexible productivity assistanceofferings can be custom-tailored tohelp your organization withanything from ensuring the properconfiguration and installation ofyour equipment, to assisting youwith test and debug of your product.We also offer a number of qualitytraining courses to help you fullyunderstand the measurementcapabilities of your tools,accelerating your ramp-up time significantly.

Outsourcing

With Agilent MeasurementOutsourcing Services, Agilentbecomes an extension of your designvalidation/test process. Agilent’sMeasurement services provideflexible access to Agilent expertiseand technology. Our services lowerthe overall cost of your validationand test processes by allowing you to: Use operational money instead of capital.Have the correct resource, with theright expertise, when and where youneed them.Have higher utilization of testequipment in the lab.Evaluate the feasibility of a testtechnology before making a largerinvestment

For more information about Agilent’s professional engineering services, log ontowww.agilent.com/find/usproducts_services

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Stay Ahead of Emerging Technologies

Related Literature

86100B Agilent Infiniium DCA Color Brochure 5988-5235EN

16900 Series Logic Analysis System Color Brochure 5989-0420EN

N4220B Packet Analysis Probe Technical Overview 5989-0086EN

81133A and 81134A Pulse/Pattern Generators Data Sheet 5988-5549EN

Physical Layer Test Systems Data Sheet 5988-5288EN

Physical Layer Test System (PLTS Version 3.0) Technical Overview 5989-0271EN

Infiniium 80000 Series OscilloscopesInfiniiMax II Series Probes Data Sheet 5989-1487EN

PCI Express Receiver Design Validation Application Note 5988-7432EN

ParBERT 81250 Parallel Bit ErrorRatio Tester Data Sheet 5968-9188E

E2960 Series System Protocol Testerfor PCI Express Color Brochure 5989-2526EN

Jitter Solutions for Digital Circuits Color Brochure 5988-8427EN

Agilent’s High Speed PhysicalLayer Characterization and Modeling Service Technical Overview 5988-7042EN

Conclusion

Agilent has been there for you in thepast and will continue to be there as PCI Express evolves. Agilent is committed to providing the PCI Express test tools you need. With the experience gaineddeveloping PCI/PCI-X and InfiniBand tools, Agilent is wellpositioned and ready to provide the best solutions for this evolvinginterconnect technology.

www.agilent.com

For more information on PCI Express tools visit www.agilent.com/find/pci_express

Agilent Technologies’ Test and Measurement Support, Services, and AssistanceAgilent Technologies aims to maximize the value you receive, while minimizing your risk andproblems. We strive to ensure that you get the test and measurement capabilities you paidfor and obtain the support you need. Our extensive support resources and services can helpyou choose the right Agilent products for your applications and apply them successfully.Every instrument and system we sell has a global warranty. Two concepts underlie Agilent'soverall support policy: "Our Promise" and "Your Advantage."

Our PromiseOur Promise means your Agilent test and measurement equipment will meet its advertisedperformance and functionality. When you are choosing new equipment, we will help youwith product information, including realistic performance specifications and practicalrecommendations from experienced test engineers. When you receive your new Agilentequipment, we can help verify that it works properly and help with initial product operation.

Your AdvantageYour Advantage means that Agilent offers a wide range of additional expert test andmeasurement services, which you can purchase according to your unique technical andbusiness needs. Solve problems efficiently and gain a competitive edge by contracting withus for calibration, extra-cost upgrades, out-of-warranty repairs, and on-site education andtraining, as well as design, system integration, project management, and other professionalengineering services. Experienced Agilent engineers and technicians worldwide can help you maximize your productivity, optimize the return on investment of your Agilentinstruments and systems, and obtain dependable measurement accuracy for the life ofthose products.

For more information on Agilent Technologies’products, applications or services, pleasecontact your local Agilent office. The completelist is available at:

www.agilent.com/find/contactus

Phone or FaxUnited States:(tel) 800 829 4444(fax) 800 829 4433

Canada:(tel) 877 894 4414(fax) 800 746 4866

China:(tel) 800 810 0189(fax) 800 820 2816

Europe:(tel) 31 20 547 2111

Japan:(tel) (81) 426 56 7832(fax) (81) 426 56 7840

Korea:(tel) (080) 769 0800(fax) (080) 769 0900

Latin America:(tel) (305) 269 7500

Taiwan:(tel) 0800 047 866(fax) 0800 286 331

Other Asia Pacific Countries:(tel) (65) 6375 8100(fax) (65) 67556 0042Email: [email protected] revised: 1/12/05

Product specifications and descriptions in thisdocument subject to change without notice.

© Agilent Technologies, Inc. 2005Printed in USA June 2, 20055988-7780EN

www.agilent.com/find/emailupdatesGet the latest information on the products and applications you select.

Agilent T&M Software and ConnectivityAgilent's Test and Measurement software and connectivity products, solutions anddeveloper network allows you to take time out of connecting your instruments to yourcomputer with tools based on PC standards, so you can focus on your tasks, not on yourconnections. Visit www.agilent.com/find/connectivity for more information.

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