PCI Express 4 - teledynelecroy.com.cn · The PCI Express 4.0 Timetable Preliminary workshop:...

PCI Express 4.0

Electrical compliance test overview

Agenda

PCI Express 4.0 electrical

compliance test overview

Required test equipment

Test procedures:

Transmitter Electrical testing

Transmitter Link Equalization

testing

Receiver Link Equalization

testing

PLL Bandwidth testing

Q&A

2

PCI Express: terminology and history

PCIE Terminology

PCI Express Standards are maintained by the PCI-SIG

Peripheral Components Interface Special Interest Group

PCI Express specifications:

BASE specification: defines device behavior at the chip level

CEM (Card ElectroMechanical) specification: defines device behavior at the card connector

Test specification: how to test a device for CEM spec compliance

3

History

A new version of each of these

specifications is developed for each

generation of PCIE

2005: PCIe 1.0, 2.5 Gb/s

2007: PCIe 2.0, 5 Gb/s

2010: PCIe 3.0, 8 Gb/s

2018: PCIe 4.0, 16 Gb/s

The PCI Express 4.0 Timetable

Preliminary workshop: Primary purpose is test and specification development. Test results are not required to be shared with device vendors.

FYI workshop: Vendors receive pass/fail results but no official integrator’s list. At least 2 FYI workshops are run before official compliance testing begins.

Compliance workshop: Test specification is complete and approved. Devices are officially tested, and passing devices are added to the integrator’s list.

4

Not a Gen4 workshop

Possible Gen4

FYI workshop

First Gen4

preliminary workshop

Gen4 preliminary workshop

Likely Gen4

FYI workshop

Possible first Gen4

compliance workshop

WS101

April 2017

WS102

August 2017

WS103

October 2017

WS104

December 2017

WS105

April 2018

WS106

August? 2018

Compliance Test Specification overview

Test name New for Gen4? Notes

Transmitter Signal Quality Automated using SigTest

Transmitter Pulse Width Jitter Yes New for 4.0 – still being defined

Transmitter Preset Automated using SigTest

Transmitter initial Tx Equalization

Transmitter Link Equalization response

Lane Margining Timing Yes New for 4.0 – still being defined

Lane Margining Voltage Yes New for 4.0 – still being defined

Receiver Link Equalization Replaces receiver test from Gen3

PLL Bandwidth Only tested for add-in card

PCB Impedance Informative only – VNA test

5

(PCI Express 4.0 PHY test spec, Rev 0.5)

Defined PCI Express 4.0 compliance tests:

PCI Express 4.0 test equipment

Oscilloscope (all tests)

High-bandwidth real-time oscilloscope

25 GHz bandwidth is required for Gen4

13 GHz bandwidth was required for Gen3

Integrated eye diagram and jitter analysis tools

Channel embedding and fixture de-embedding

PCI Express decoding with waveform annotation and tabular analysis

ProtoSync for high-level protocol decode

Server-class CPU with 20 cores gives a significant speed advantage in PCIe Gen4 testing

7

Teledyne LeCroy LabMaster 10Zi-A

Oscilloscope models from 25 GHz to 100 GHz,

to support 16 Gb/s, 32 Gb/s and beyond

BERT (all tests except Tx tests)

Anritsu MP1900A SQA-R

Multi-channel BERT from 2.4 Gbit/s to 32.1 Gbit/s

Max 16-ch 32G NRZ or 8-ch 64G PAM4

Link Training/Equalization and LTSSM Analysis

Signal Integrity (low intrinsic jitter and fast Tr/Tf)

Maximum 10 Tap +/-20dB Emphasis function

12 dB CTLE and clock recovery functions

Jitter and noise generation

Applications

PCIe Gen1 to 5, Thunderbolt 3, USB3.1 Gen1/2

IEEE 100/200/400 GbE, CEI-25/28/56/112G

InfiniBand EDR/HDR, Fibre Channel

Optical Module, SERDES, AOC, High-Speed Interconnect

8

Built-in PCI Express Link Training and LTSSM Analysis Functions

MP1900A series supports Physical layer evaluations

PCIe Gen1 to Gen4 and future Gen5 receiver tests

Analyzing LTSSM (Link Training Status State Machine)

Tx/Rx Link Equalization Response Test

Rx Link Equalization Test

Receiver Jitter Tolerance Test

Identify the root of the Link Failure problem.

9

Test automation software

QualiPHY PCIe4-Tx-Rx

Can be run on LabMaster 10Zi-A or external PC

Automates all testing Collection and analysis of

waveforms for Tx test

BERT calibration and jitter tolerance for Rx test

Automated Link EQ testing

Connection diagrams

Report generation

Can be integrated with external test automation through simple, powerful Host Program Control feature

10

Additional automation options

TF-PCIe4-CTRL

PCIe Gen4 Compliance Base Board will feature dedicated automation control headers for:

Board power on/off

DUT reset

Tx preset toggle

Teledyne LeCroy TF-PCIe4-CTRL CBB automation controller connects directly to the oscilloscope

Fully integrated into QPHY-PCIe4-Tx-Rx to enable total test automation for PCIe Gen4 testing

11

Test system components and the specification

Teledyne LeCroy

LabMaster 10Zi-A

Anritsu

MP1900A SQA-R

Qu

aliP

HY

co

mp

lian

ce

so

ftw

are

TF

-PC

IE4

-CT

RL

au

tom

ation

25

GH

z b

an

dw

idth

Ch

an

ne

l e

mb

ed

din

g

Mu

lti-

co

re

pro

ce

ssin

g

PC

Ie d

eco

de

Pro

toS

yn

c

2.4

– 3

2.1

Gb

/s

PP

G

2.4

– 3

2.1

Gb

/s E

D

Inte

gra

ted

jitt

er

so

urc

es

Inte

gra

ted

no

ise

so

urc

es

Em

ph

asis

Lin

k T

rain

ing

LT

SS

M A

na

lysis

Transmitter Signal Quality X X X X X

Transmitter Pulse Width Jitter Specification still in progress

Transmitter Preset X X X X

Transmitter initial Tx Equalization X X X X X X X X X

Transmitter Link Equalization response X X X X X X X X X

Lane Margining Timing Specification still in progress

Lane Margining Voltage Specification still in progress

Receiver Link Equalization X X X X X X X X X X X X

PLL Bandwidth X X X X

12

PCI Express 4.0 test overview

Transmitter electrical testing

Transmitter electrical testing












14


Transmitter testing overview

Two basic transmitter tests:

Preset test: check that each transmitter emphasis preset is within limits

Signal quality test: eye diagram, jitter etc.

Transmitter tests are performed using SigTest software from PCI-SIG

SigTest for PCIe Gen4 is still in development and not available outside test development subgroup

15

PCIe 4.0 nominal channel

16

System Board

Add-in c

ard

CEM connector Root complex

Endpoint

Package

DIE Tx

Rx

5dB package loss

Pa

cka

ge

DIE

T

x

Rx

3dB

package loss

20 dB loss (incl 5 dB package loss)

8dB loss (incl 3 dB package loss)

28 dB total system loss All loss values specified at 8 GHz (Nyquist frequency for 16 Gb/s)

Add-in card transmitter test

17

System Board

Add-in c

ard


Endpoint


Signal

We want to measure the Tx signal here:

Root-complex Rx after worst-case (20 dB) loss

Device under test

Add-in card transmitter test: connection schematic

18

Add-in card under test

5dB package model • 5dB is in the root-complex package, which we emulate by embedding an s4p file using the scope’s software

• The other 15dB comes from the ISI board

15dB channel

Add-in card transmitter test: connection schematic

Transmitter

test uses the

same setup

for both

preset and

signal quality

tests

19

Device preset selection

For Gen4 testing, it’s necessary to acquire at least one 1.6MUI waveform at each preset

Use compliance toggle button (circled) or TF-PCIe4-CTRL to toggle through presets: Gen1: 1 x 2.5 Gb/s preset

Gen2: 2 x 5 Gb/s presets

Gen3: 10 x 8 Gb/s presets

Gen4: At least 11 presets: P0-P10 compliance waveforms Toggle (1010) pattern on all lanes Toggle on each Tx lane with traffic on all other lanes

20

Transmitter test execution

21

QPHY-PCIe4-Tx-Rx runs SigTest preset and signal quality tests on

acquired waveforms

Signal Quality test can be time-consuming

QPHY-PCIe4-Tx-Rx leverages the 20-core processor in the LabMaster 10Zi-

A to execute many SigTest instances in parallel, reducing test time

PCIE 4.0 Test Report

Add-in card test procedure: Preset test results

SigTest runs the preset test on

all acquired waveforms

It measures the pre-shoot and

de-emphasis on the P4 (0dB,

0dB) waveform and tests all

others relative to that

22

Add-in card test procedure: Signal Quality test

Signal Quality test is performed

only on one preset – typically P5

or P6 for PCIe Gen4

23

Add-in card test procedure: Signal Quality results

24


Teledyne LeCroy

LabMaster 10Zi-A

Anritsu

MP1900A SQA-R

Qu

aliP

HY

co

mp

lian

ce

so

ftw

are

TF

-PC

IE4

-CT

RL

au

tom

ation

25

GH

z b

an

dw

idth

Ch

an

ne

l e

mb

ed

din

g

Mu

lti-

co

re

pro

ce

ssin

g

PC

Ie d

eco

de

Pro

toS

yn

c

2.4

– 3

2.1

Gb

/s

PP

G

2.4

– 3

2.1

Gb

/s E

D

Inte

gra

ted

jitt

er

so

urc

es

Inte

gra

ted

no

ise

so

urc

es

Em

ph

asis

Lin

k T

rain

ing

LT

SS

M A

na

lysis










25


Transmitter Link Equalization testing

Transmitter Link Equalization












27


Transmitter Link Equalization testing

28

CBB

Ad

d-in c

ard

Device under test

Preset

request

Requested

preset

Measure

response

time

Verify

presets

Capture signals with all transmitter emphasis presets, and test using SigTest

Preset changes are initiated through protocol request from the test equipment

Not switched manually using fixture as for Tx electrical tests

1.

2. 3.

Trigger

Example test: response time

“The test verifies that the add-in card will respond correctly to

transmitter equalization commands sent via the link protocol.”

BERT negotiates DUT to change its transmitter emphasis preset

Time, t, between request for preset change (protocol layer) and actual

preset transition is measured using the oscilloscope:

t < 500ns: Pass

500ns < t <1us: Pass with warning

t > 1us: Fail

29

Transmitter Link Equalization – test setup

Signal from BERT to DUT and from DUT to BERT are split to the oscilloscope

Trigger signal from BERT enables scope to be triggered at any point in the link training sequence

30


BERT requests DUT change its Tx emphasis preset from P7 to P4

BERT sends trigger to oscilloscope at the time of preset change request

31


Oscilloscope

acquires

both sides of

transaction

32

Downstream signal (from BERT)

Upstream signal (from DUT)


The emphasis change is clearly visible: this is the end-point of the measurement

But we need to determine the exact timing of the protocol-layer request so we know where to start the measurement

33

?


The oscilloscope decodes the downstream signal into digital data and passes it to Teledyne LeCroy protocol analysis software

34


The oscilloscope trace is time-correlated with the protocol analysis

The packet can be easily identified in the waveform

35


Now it’s trivial to measure the response time from protocol request to physical emphasis change

This device’s response time is 81.18ns – an easy pass

36


Teledyne LeCroy

LabMaster 10Zi-A

Anritsu

MP1900A SQA-R

Qu

aliP

HY

co

mp

lian

ce

so

ftw

are

TF

-PC

IE4

-CT

RL

au

tom

ation

25

GH

z b

an

dw

idth

Ch

an

ne

l e

mb

ed

din

g

Mu

lti-

co

re

pro

ce

ssin

g

PC

Ie d

eco

de

Pro

toS

yn

c

2.4

– 3

2.1

Gb

/s

PP

G

2.4

– 3

2.1

Gb

/s E

D

Inte

gra

ted

jitt

er

so

urc

es

Inte

gra

ted

no

ise

so

urc

es

Em

ph

asis

Lin

k T

rain

ing

LT

SS

M A

na

lysis










37


Receiver Link Equalization testing

Receiver electrical testing












39


Add-in card receiver test

40

System Board

Add-in c

ard


Endpoint


Signal

We want to calibrate the Rx signal here:

Root-complex Tx after worst-case (20 dB) loss

Device under test

Jitter and Noise Injection

41

CM/DM Noise White Noise Sinusoidal Jitter(SJ) Random Jitter(RJ)

Jitter Injection

• Dual Tone SJ: 1UI @ 250MHz

• Random Jitter (RJ): 0.5UIpp (2.2ps RMS @16GHz)

• BUJ and Half Period Jitter (Even/Odd Jitter)

• SSC

Noise Injection

• Common mode noise frequency: 0.1 GHz to 6 GHz

• Differential mode noise frequency: 2 GHz to 10 GHz

• White noise band: 10 GHz; Crest Factor: >5

Add-in card receiver test, Step 1:

Preset, Rj, Sj calibration

42

Preset calibration

Jitter calibration


DMI, CMI, initial preset/CTLE selection

Differential and common-mode noise are calibrated with a 27 dB channel

Optimal Tx preset + Rx (scope) CTLE combination is established with 27dB channel

43

BERT

Scope with embedded

3dB package model

DMI, CMI, Eye calibration: Connection schematic

44

Jitter

ED

PPG

Noise

1m SMA-SMA cables

19-22dB channel

5dB channel

3dB package model


DMI, CMI, initial preset/CTLE selection

45

The next steps in Rx calibration should be performed with the best combination of: Tx emphasis Preset 5 or Preset 6

One of 9 CTLE peaking values available for SigTest

At least 5 waveforms of each preset should be analyzed for averaging

5 waveforms x 2 presets x 9 CTLE presets = 90 SigTest runs at ~2 minutes each = 3 hours for this stage of calibration if done sequentially

LabMaster 10Zi-A can process up to 20 waveforms in parallel, substantially reducing test time for this step to approx. 20 minutes

Preset 5 or Preset 6

CTLE from 7.5dB – 9dB


Find marginal channel Increase total channel loss in 0.5dB increments

Check eye width and height, stop incrementing if final calibration targets are violated

Otherwise, stop at 30dB channel

46

BERT

Scope with embedded

3dB package model


Find marginal channel

47

At least 5 waveforms at each channel should be analyzed for averaging

When the new channel is established, optimal preset/CTLE must be established AGAIN

5 waveforms x 2 presets x 9 CTLE presets = 90 SigTest runs at ~2 minutes each = 3 hours for this stage of calibration if done sequentially

LabMaster 10Zi-A can process up to 20 waveforms in parallel, substantially reducing test time for this step to approx. 20 minutes

Preset 5 or Preset 6

CTLE from 7dB – 9dB


Final Eye calibration

Using final channel, converge to target eye height and width values by

varying amplitude, DM interference, and Sj

48

BERT

Scope with embedded

3dB package model


Negotiate into loopback

The DUT must now be negotiated into loopback by the BERT

This must happen through the “Recovery path”, where the device performs link training and requests the optimal transmitter preset from the BERT

49


Perform BER test

Once in loopback, a BER test is run

A PASS is defined as no more than one error in 1012 bits

50

Jitter Tolerance Test

51


Teledyne LeCroy

LabMaster 10Zi-A

Anritsu

MP1900A SQA-R

Qu

aliP

HY

co

mp

lian

ce

so

ftw

are

TF

-PC

IE4

-CT

RL

au

tom

ation

25

GH

z b

an

dw

idth

Ch

an

ne

l e

mb

ed

din

g

Mu

lti-

co

re

pro

ce

ssin

g

PC

Ie d

eco

de

Pro

toS

yn

c

2.4

– 3

2.1

Gb

/s

PP

G

2.4

– 3

2.1

Gb

/s E

D

Inte

gra

ted

jitt

er

so

urc

es

Inte

gra

ted

no

ise

so

urc

es

Em

ph

asis

Lin

k T

rain

ing

LT

SS

M A

na

lysis










52


PLL Bandwidth

PLL Bandwidth












54


PLL Bandwidth overview

“The test verifies that the add-in card PLL bandwidth and peaking are within the limits allowed by the PCI Express specifications.”

This is essentially a jitter transfer function measurement, with the intention of checking:

That the -3dB point of the DUT’s jitter transfer function is within an acceptable frequency range

That the DUT’s jitter transfer function does not have excessive peaking

To perform this test, we use the BERT’s subrate clock output to intentionally apply calibrated jitter to the reference clock used by the DUT

55

PLL Bandwidth: Calibration

Apply a defined amount of

sinusoidal jitter (Sj) across the

PLL bandwidth measurement

range to a 100MHz subrate

clock

Measure the jitter at each

frequency using the oscilloscope

56

PLL Bandwidth: Test

For each applied calibrated Sj value, measure the periodic jitter (Pj) at the device transmitter

Plot a curve of the jitter transfer for each frequency, and compare to the specification limits

57


Teledyne LeCroy

LabMaster 10Zi-A

Anritsu

MP1900A SQA-R

Qu

aliP

HY

co

mp

lian

ce

so

ftw

are

TF

-PC

IE4

-CT

RL

au

tom

ation

25

GH

z b

an

dw

idth

Ch

an

ne

l e

mb

ed

din

g

Mu

lti-

co

re

pro

ce

ssin

g

PC

Ie d

eco

de

Pro

toS

yn

c

2.4

– 3

2.1

Gb

/s

PP

G

2.4

– 3

2.1

Gb

/s E

D

Inte

gra

ted

jitt

er

so

urc

es

Inte

gra

ted

no

ise

so

urc

es

Em

ph

asis

Lin

k T

rain

ing

LT

SS

M A

na

lysis










58

Please visit LeCroy and Anritsu at Designcon 2018

Anritsu live demos at booth 741:

PCIe Gen4 Receiver Compliance Test

High Speed Serial Bus RX automation Test (PCIe, Thunderbolt, USB)

400G PAM4 Direct Attach Cupper (DAC) Cable BER Test

100G Active Optical Cable (AOC) JTOL Test

Teledyne LeCroy live demos at booth 515:

PCIe Gen4 Link Equalization Compliance Test

PCIe Gen4 Protocol Analysis

USB 3.1 Type-C Compliance Solutions

PAM4 Test, Analysis and Debug

DDR Memory Testing

59

Thank you

PCI Express 4 - teledynelecroy.com.cn · The PCI Express 4.0 Timetable Preliminary workshop:...

Documents

Transcript of PCI Express 4 - teledynelecroy.com.cn · The PCI Express 4.0 Timetable Preliminary workshop:...