Parity bit generator Project Presentation Instructor: Dr.Roman Stemprok Submitted by Srujana...

16
Parity bit generator Parity bit generator Project Presentation Instructor: Dr.Roman Stemprok Submitted by Srujana Aramalla

Transcript of Parity bit generator Project Presentation Instructor: Dr.Roman Stemprok Submitted by Srujana...

Parity bit generatorParity bit generator

Project Presentation

Instructor: Dr.Roman Stemprok

Submitted by

Srujana Aramalla

Basic circuit diagram

Inverter layout

Inverter consists of 1 p-MOSFET and 1 n-MOSFET

.SPC file for inverter

.CIR file for inverter

PSPICE simulation of inverter

Transmission gate layout

.CIR file for transmission gate

PSPICE simulation of transmission gate

XOR gate layout

This gate consists of 2 inverters and 2 transmission gates.

Each transmission gate has 1 PMOSFET and 1 NMOSFET.

Each transmission gate has 1 PMOSFET and 1 NMOSFET.

.SPC file for XOR gate

.CIR file for XOR gate

PSPICE simulation of XOR gate

Layout of the 3 bit even parity bit generator in L-EDIT

Extraction file for complete layout* Circuit Extracted by Tanner Research's L-Edit V5.13 / Extract V2.06 ;

* TDB File C:\PARITY, Cell Cell0, Extract Definition File C:\MORBN20.ext ;

C17 119 0 31.291FF

C18 112 0 31.291FF

C19 105 0 31.291FF

C20 99 0 31.291FF

C37 123 0 30.303FF

C38 122 0 30.303FF

C39 121 0 30.303FF

C40 120 0 30.303FF

C41 118 0 14.065FF

C42 116 0 44.08FF

C43 115 0 27.057FF

C44 113 0 163.473FF

C45 111 0 14.065FF

C46 109 0 48.372FF

C47 108 0 27.057FF

C48 106 0 20.996FF

C49 104 0 14.065FF

C50 102 0 60.668FF

C51 101 0 27.057FF

C52 98 0 14.065FF

C53 96 0 27.057FF

C54 94 0 20.996FF

M1 119 109 118 4 PMOS L=2U W=14U

M2 113 109 116 7 PMOS L=2U W=13U

M3 115 118 116 11 PMOS L=2U W=13U

M4 119 113 115 15 PMOS L=2U W=14U

M5 112 102 111 19 PMOS L=2U W=14U

M6 106 102 109 22 PMOS L=2U W=13U

M7 108 111 109 26 PMOS L=2U W=13U

M8 112 106 108 30 PMOS L=2U W=14U

M9 105 106 104 33 PMOS L=2U W=14U

M10 113 106 102 36 PMOS L=2U W=13U

M11 101 104 102 40 PMOS L=2U W=13U

M12 105 113 101 44 PMOS L=2U W=14U

M13 99 47 98 48 PMOS L=2U W=14U

M14 94 47 113 51 PMOS L=2U W=13U

Extraction file for complete layout (contd…)

M15 96 98 113 55 PMOS L=2U W=13U

M16 99 94 96 59 PMOS L=2U W=14U

M57 123 109 118 93 NMOS L=2U W=13U

M58 115 109 116 93 NMOS L=2U W=13U

M59 113 118 116 93 NMOS L=2U W=13U

M60 123 113 115 93 NMOS L=2U W=13U

M61 122 102 111 93 NMOS L=2U W=13U

M62 108 102 109 93 NMOS L=2U W=13U

M63 106 111 109 93 NMOS L=2U W=13U

M64 122 106 108 93 NMOS L=2U W=13U

M65 121 106 104 93 NMOS L=2U W=13U

M66 101 106 102 93 NMOS L=2U W=13U

M67 113 104 102 93 NMOS L=2U W=13U

M68 121 113 101 93 NMOS L=2U W=13U

M69 120 47 98 93 NMOS L=2U W=13U

M70 96 47 113 93 NMOS L=2U W=13U

M71 94 98 113 93 NMOS L=2U W=13U

M72 120 94 96 93 NMOS L=2U W=13U

.MODEL NMOS NMOS LEVEL=2 LD=0.250000U TOX=417.000008E-10

+ NSUB=6.108619E+14 VTO=0.825008 KP=4.919000E-05 GAMMA=0.172

+ PHI=0.6 UO=594 UEXP=6.682275E-02 UCRIT=5000

+ DELTA=5.08308 VMAX=65547.3 XJ=0.250000U LAMBDA=6.636197E-03

+ NFS=1.98E+11 NEFF=1 NSS=1.000000E+10 TPG=1.000000

+ RSH=32.740000 CGDO=3.105345E-10 CGSO=3.105345E-10 CGBO=3.848530E-10

+ CJ=9.494900E-05 MJ=0.847099 CJSW=4.410100E-10 MJSW=0.334060 PB=0.800000

.MODEL PMOS PMOS LEVEL=2 LD=0.227236U TOX=417.000008E-10

+ NSUB=1.056124E+16 VTO=-0.937048 KP=1.731000E-05 GAMMA=0.715

+ PHI=0.6 UO=209 UEXP=0.233831 UCRIT=47509.9

+ DELTA=1.07179 VMAX=100000 XJ=0.250000U LAMBDA=4.391428E-02

+ NFS=3.27E+11 NEFF=1.001 NSS=1.000000E+10 TPG=-1.000000

+ RSH=72.960000 CGDO=2.822585E-10 CGSO=2.822585E-10 CGBO=5.292375E-10

+ CJ=3.224200E-04 MJ=0.584956 CJSW=2.979100E-10 MJSW=0.310807 PB=0.800000

.TRAN 2ns 20ns

.PROBE

.END