Organic Interposer Advanced BuildAdvanced Build -Up ...meptec.org/Resources/9 - Kyocera.pdfFCA pitch...

KYOCERA SLC Technologies Corporation-Advanced Packaging Development Group 12012.11.14

Organic Interposer

Advanced Build-Up Package Technology

Organic InterposerOrganic Interposer

Advanced BuildAdvanced Build--Up Package TechnologyUp Package Technology

Joseph DangField Applications Engineer

November 14, 2012MEPTEC


• Technology Trend

• Low CTE Characteristics – APX

• High Density Design Rules – APX

• APX Applications

• Technology Trend

• Low CTE Characteristics – APX

• High Density Design Rules – APX

• APX Applications

Table of Contents


0

20

40

60

80

100

120

140

160

180

2009 2014 2019 2024

I/O

Pit

ch ,

µm

I/O Pitch Trend & Technical Challenges

http://www.itrs.net/Links/2009ITRS/Home2009.htm

FC : High Performance

Coarse TSVFC Peripheral

FC : Mobile Products

Fine TSV

Wedge WBDRAM

100μμμμm at 2015

Next Generation of Organic Build-Up SubstrateNext Generation of Organic Build-Up Substrate

Technology Wall : Pitch Restriction by CTE and Wiring Density of Substrate Technology Wall : Pitch Restriction by CTE and Wiring Density of Substrate

FC Pitches are Limited by

- Bonding Technology

- Substrate Technology

(Density and CTE limitations)


Size Reduction of IC and Package

Development Concept for APX (Tentative)High Density and Low CTE

Stress on Chip - Substrate Joint

Substrate

IC Chip

Line width (µm)

100

(15）

20

25

35

50

5

6812

0.10.3

13

5

Inside IC

APX

Current organic substrate

Board

- High Density -- High Density - - Low CTE -- Low CTE -

Standard

Build-up

For 15 mm square chip

Low stress with Low CTE

1

2

3

4

5

6

0 3 6 9 12 15 18 21

CTE, ppm /℃

Joint Stress, Index

3

Current Organic

Ceramic

10

IC

APX

For 15 mm square chip

Low stress with Low CTE

1

2

3

4

5

6

0 3 6 9 12 15 18 21

CTE, ppm /℃

Joint Stress, Index

3

Current Organic

Ceramic

10

IC

APX

APX


Development of APX 1st Step

FCx/BCxLine Width:10 min.Space:10 min.

FCA PadPitch : 120Pad dia : 50

ViaVia pitch: 60 Via dia. : ≦≦≦≦30Via land dia. : 50

PTHPitch : 120Hole dia.:(57/30)Land dia. : 80

Core Material4785TH-B

FC1/BC1Line Width: 20 min.Space: 20 min.

BGAPitch: 500Pad dia. : 250

Layer2+2+2

Size 21 x 21mm

Build-Up Material

XENOMAX+Y20

Semiconductor ChipSize:10x10 mmBump Pitch : 120

Ø25µm VIA

25µm

120µm-p FCA

chip

②②②② Via Connection②②②② Via Connection①①①① Chip Assembly①①①① Chip Assembly

L/S=10/10µm

③③③③ Trace Insulation③③③③ Trace Insulation

120µm-p TH

120µm

④④④④ TH Insulation④④④④ TH Insulation

Development Target

120µm

>50μμμμm

10µm

>8μμμμm

Development Item●●●● Low CTE Core (7ppm/℃℃℃℃)

(Substrate：：：：10～～～～12ppm/℃℃℃℃)

●●●● Low tanδδδδ Core (0.004)

●●●● Select Low CTE – Elasticity

Insulator

●●●● 120µm Pitch Through Hole

●●●● 20µm Space on Core Surface

●●●● ≦≦≦≦30µm Via Hole

●●●● 10/10µm Line/Space in BU

●●●● Low Roughness on Insulator

●●●● Low Roughness on Copper

●●●● 120µm Pitch Chip Assembly

(With Warpage, Flatness)

●●●● Low-K Chip Assembly

●●●● Low Stress Underfill

●●●● 500µm Pitch 2nd Assembly

●●●● Setup Repair Process

●●●● Setup Inspection Stage


4

7

10

13

16

19

22

25

CT

E p

pm

/deg

.C

CTE versus Material, Thickness, Structure

Ｃ 0.2t

Ｂ 0.2t

Ａ 0.2t

Ａ 0.4t

Ａ 0.6t

ＢＢＢＢ

ＣＣＣＣ

Ａ 0.6t + 4 layer Bup

Ａ 0.2t + 2 layer Bup

Ａ 0.4t+2 layer Bup

Core only After

TH drill

After Cu Plating

Add 2 Bup

2-2-2Add 6 Bup

6-4-6

CSP

Measured by Optical

Build-up:

Epoxy

Bup: PI (CTE=0 ppm)

Bup: Build-up

SUMITOMO BAKELITEELC-4785

ＡＡＡＡ


Limitation of Substrate CTE for 20mmSQ Chip Assembly

λλλλ2

Package Substrate (PKG)Package Substrate (PKG)

Flip Chip Die

λλλλ2

Pad Pitch

Wid

th (

d)

Flip Chip Pad

PKG Pad

λλλλ 2

(unit: µm)

Pad Pitch 300 250 220 185 150 120 100 80 65 50 40

Pad Dia. 150 125 110 95 75 60 50 40 33 25 20

Width (d) 424 354 311 262 212 170 141 113 92 71 57

22 129 129××××1/2⇒⇒⇒⇒ 65 65 65 65 65 65 65 65 65 65 65

20 115 115××××1/2⇒⇒⇒⇒ 58 58 58 58 58 58 58 58 58 58 58

18 102 102××××1/2⇒⇒⇒⇒ 51 51 51 51 51 51 51 51 51 51 51

15 81 81××××1/2⇒⇒⇒⇒ 41 41 41 41 41 41 41 41 41 41 41

13 68 68××××1/2⇒⇒⇒⇒ 34 34 34 34 34 34 34 34 34 34 34

11 54 54××××1/2⇒⇒⇒⇒ 27 27 27 27 27 27 27 27 27 27 27

9 41 41××××1/2⇒⇒⇒⇒ 21 21 21 21 21 21 21 21 21 21 21

7 27 27××××1/2⇒⇒⇒⇒ 14 14 14 14 14 14 14 14 14 14 14

5 14 14××××1/2⇒⇒⇒⇒ 7 7 7 7 7 7 7 7 7 7 7

3 0 0××××1/2⇒⇒⇒⇒ 0 0 0 0 0 0 0 0 0 0 0

Flip Chip Die Size: 20mm SQ

CTE of PKG

(ppm)Delta CTE of

Width (d) [λλλλ]

Width (d) : Width across corner on PAD

KYOCERA SLC Technologies Corporation-Advanced Packaging Development Group 82012.11.14 8

Chip Attached on Current Substrate

�Chip Size: 20mm

�Bump Pitch: 170µm

�Chip CTE: 3.5ppm

Diagonal Distance: 28mm

35um

2um 25um

�Substrate CTE: 18ppm

�Solder: 63Sn37Pb

�Melting Point: 183℃℃℃℃

Misalignment of Bump to Pad：：：：60µm/28mm


� Chip Size: 10mm

� Bump Pitch: 120µm

� Chip CTE: 3.5ppm

Chip Attached on APX Substrate

Misalignment of Bump to Pad：：：：12µm/10mm

9.5um9.5um 2.5um2.5um

10mm

� APX CTE: 10ppm

� Solder: Sn2.5Ag

� Melting Point: 220℃


Current APX Current APX

L / S L / S L / S L / S L / S L / S L / S L / S

15 / 15 µm 10 / 10 µm 8 / 8 µm 6 /6 µm 15 / 15 µm 10 / 10 µm 8 / 8 µm 6 /6 µm

120 µm

pitch

100 µm

pitch

n =5n =3n =3n =0 n =3n =2n =2n =0

Current APX Current APXL / S L / S L / S L / S L / S L / S L / S L / S

15 / 15 µm 10 / 10 µm 8 / 8 µm 6 /6 µm 15 / 15 µm 10 / 10 µm 8 / 8 µm 6 /6 µm

185 µm

pitch

150 µm

pitch

n =10n =7n =6n =2

n =7n =5n =4n =1

Land

95 µm

Land

50 µm

Wiring between pins: more than double, half the number of layers

Wiring Capability of APX 1st Step Substrate

Mobile: FCCSP with Via.φ25μm


Reliability of APX-0.5

<Chip>

<Evaluation TV>

<Evaluation Substrate>

Reliability Evaluation ResultReliability Evaluation Result1st level evaluation PKG1st level evaluation PKG

2nd level evaluation PKG2nd level evaluation PKG

Size 21x21x0.32 mm

Layer 　　2-2-2

FCA pitch 120 µm

FCA pad dia. 50 µm

Via land dia. 50 µm

Line width 10 µm

min. space 10 µm

TH pitch 150 µm

TH land dia. 80 µm

BGA pitch 500 µm

No. BGA I/O 1680

Size mm

Bump pitch 120 µm

No. of I/O 6,888

Underfill

Solder

10x10x0.3

U8437-2

Sn3Ag0.5Cu

TEST Condition Result Package

DTC -55/125℃℃℃℃,2cph pass 1000 cycle 1st level

WTC -55/125℃℃℃℃,10cph pass 1000 cycle 1st level

HTC 150℃℃℃℃ pass 1000 hrs 1st level

THB 85℃℃℃℃/85%RH/5V pass 1000 hrs 2nd level

PCBT 130℃℃℃℃/85%RH/5V pass 96 hrs 2nd level

Precon: JEDEC L3

Objective


Image of APX 1st Step Substrate


Stiffness Comparison of Each PKG ConceptStiffness

CTE of PKG (Now)

Core: 0.2mmtCore: 0.2mmtCore: 0.2mmt

CorelessGX13

CorelessCorelessGX13GX13

APXAPXAPXAPX----0.50.50.50.5APXAPXAPXAPXAPXAPXAPXAPX--------0.50.50.50.50.50.50.50.5

8ppm 10ppm 12ppm 14ppm 16ppm 18ppm 20ppm 22ppm 24ppm

28GPa

27GPa

26GPa

25GPa

24GPa

23GPa

22GPa

21GPa

20GPa

Young Modulus (as total PKG/simulation)

CorelessGZ41

CorelessCorelessGZ41GZ41



Core: Current Material (E glass)Bup Dielectric: Epoxy and SiO2

Core: Low CTE material (E glass)B/U: Epoxy and SiO2

CTE: Simulation

Core: Low CTE (T glass)

B/U: Polyimide

PKG Stiffness depends on core and Bup dielectric material.

PKG CTE is mainly dependent on core and PKG construction and design


FCBGA

MCM IP for ASIC＋Memory

Ultra high pin count μ-FCBGA

FCBGA

FCBGA

(40)

(60)

80

100

120

150

185

2252012 2013 2014 2015 2016 2017 2018 2019 2020 2021

MCM IP for ASIC＋Memory Ultra high pin count μ-FCBGA

MCM IP for ASIC

MCM IP for CPU＋Wide Bus DRAM

Fine InterposerL/S: 1～2μm

Coarse InterposerL/S: 5～10μm

Current Bup territoryL/S: ≧12μm

APX territoryL/S: 5～10μmSilicon IP

Glass IPOrganic IP

Leading candidate:Silicon Interposer ?

Blank area: Flip chip 120μm PitchNow, Current Bup technology did not realize.

Assembly technology has not been developed.

Estimation of PKG Technology for ASICFC Pitch orVia. Pitch(μm)


0

20

40

60

80

100

1995 2000 2005 2010 2015 2020

Lin

e w

idth

, u

mWiring (Line Width) Trend

8 µm

20 µm

50 µm

100 µm

15 µm

(year)

5 µm

APX

By KST

Subtractive

Semi-additive8 µm

5 µm

8 µm50 µm


Further Miniaturization of the Wiring

Top View

Cross

Section

5μm6μm8μm10μmLine / Space

Cu Thickness:10µm (Dry Film Resist Test for High Resolution)


0

20

40

60

80

100

120

140

1995 2000 2005 2010 2015 2020

Via

Dia

., u

mVia, Via Land Diameter Trend

Photo CO2, UV YAG Laser 355, 266 YAG Laser

60 µm via

125 µm via

Electrolytic CuSputter Ni/Cr+Cu

Electrolytic Cu80 µm via

(year)

355nm UVYAG

By KST

25 µm via

20 µm via

40 µm

APX

CO2 Laser

266nm UVYAG


0

100

200

300

400

500

1995 2000 2005 2010 2015 2020

TH

Pit

ch, u

mTH Pitch Trend (Drill, Laser)

105 µm bit

300 µm bit

Laser

250 µm bit

(year)

Drill MC

Laser MC

New Process (Development comp.)

Pitch : 100µm

By KST

57 µm bit

APX


Enable High-Density Routing With Narrow TH Pitch

Front Side

Routing

Back Side

Routing

It is possible to make fine wiring at the back side with the same pitch

APX

Core

CoreCore

Current Technology


Si InterposerSi Interposer APXAPX

APX

CPUSi Interposer

Organic or Ceramic

Memory

CPU Memory

- High Density with High Cost

- Double Assembly

- High Density with Low cost

- Simple Assembly

APX

APX

Si Interposer and APX Applications

C

A

D

E

B


Inte

gra

tion

APX 1st Step

APX 3rd Step

6 layers (2+2+2)CTE: 10ppm/℃

L/S: 10μm

µ-via： φ 25 µmTH Pitch：120μm

6 layers (2+2+2)CTE: 5ppm/℃

L/S: 5μmTH Pitch： 50μmAPX 2nd Step

Multiple Layers>10 layers (4+2+4)

OE Substrate

Waveguide Pitch: 80μmLoss： 0.1dB/cm

◆ High Density

◆ Low CTE

◆ High Speed

◆ Low Cost

◆ High Density

◆ Low CTE

◆ High Speed

◆ Low Cost

Ultra HD Substrate

CTE: 5ppm/℃L/S: 3μm

µ-via： φ 5 µmTH Pitch： 25μm

APX Development Roadmap

Light

2010 2011 2013 2016


SummarySummary

�� Lower CTE and higher density routing Lower CTE and higher density routing

substrate has been realized by enhancing substrate has been realized by enhancing

current build up technologies.current build up technologies.

�� TheThe new technology can evolve to even lower new technology can evolve to even lower

CTE and higher routing density. CTE and higher routing density.

�� Optical routing embedded on the substrate Optical routing embedded on the substrate

can be realized for future higher speed and can be realized for future higher speed and

increasing data bandwidth requirements.increasing data bandwidth requirements.


Special Acknowledgements

KST R&D TeamMasahiro Fukui – Director, R&DKenji TeradaMasaki HarazonoTeruya FujisakiTomoyuki Yamada *

Organic Interposer Advanced BuildAdvanced Build -Up ...meptec.org/Resources/9 - Kyocera.pdfFCA pitch...

Documents

Transcript of Organic Interposer Advanced BuildAdvanced Build -Up ...meptec.org/Resources/9 - Kyocera.pdfFCA pitch...