© K.W. Martin, 1997 1

Opamp Design1

Ken Martin

Dept. of Elec. and Comp. Eng.University of Toronto

Toronto, Canada M5S 1A4

martin@eecg.toronto.edu(416) 978-6695

1. Much of the material presented in this section comes from the text “AnalogIntegrated Circuit Design,” by D. Johns and K. Martin, ISBN 0-471-14448-7,Wiley, 1997.

© K.W. Martin, 1997 2

Two-Stage CMOS Op-Amp

• Capacitor, , is used to ensure stability during feedback applications.

• Example design for a process is shown below.

Note: is in triode region and realizes a small resistor used to obtain lead

compensation.

All transistor lengths equal .

A1 -A2 1Vin Vout

DifferentialInput Stage

SecondGain Stage

OutputBuffer

CC

CC1µm

1.6 µm

Q9

Q11

Q12

Q13Q15

Q14

Q5

Q3 Q4

Q2Q1

Q8

Q6

Q7

Rb

CC

VDD

2525

25 25

25100

300

300300

150 150

300

300

Q16

Q10

Vin- Vin

+Vout

500

500

Bias Circuitry Differential-Input

First Stage

Common-Source

Second Stage

Output

Buffer

VSS

Q16

© K.W. Martin, 1997 3

Op-Amp Gain

• First stage differential-to-single ended gain is given by

(1)

where

• Second stage gain is given by

(2)

• Third stage is a source-follower and is usually only included if resistive loadsneed to be driven. If the load is purely capacitive, as is usually the case forintegrated op-amps, it is seldom included.

(3)

where GL is the load conductance being driven by the buffer stage.

Frequency Response

• Ignore all capacitors except for (to find response up to unity-gain freq).

• Also ignore for now as it is used for lead compensation (discussed later).

Av1 gm1 rds2 rds4||( )=

Av2 g– m7 rds6 rds7||( )=

Av3

gm8GL gm8 gds8 gds9+ + +--------------------------------------------------------------≅

CCQ16

Q5

Q3 Q4

Q2Q1

300

300300

150

150

Vin-

Vin+

Vbias

-A2 A3 Vout

CCv1

i = gm1 vin

v2

© K.W. Martin, 1997 4

• Using Miller’s Theorem, one can show that the equivalent load capacitance,, at node is given by,

(4)

• The gain in the first stage can now be found resulting in

(5)

where

(6)

For mid-band frequencies, the impedance of Ceq dominates, and we can write

(7)

• Now, for the overall gain, we have

(8)

and assuming , then the overall gain simplifies to

(9)

• This simple equation can be used to find the approximate unity gain frequency.Specifically, to find the unity-gain frequency, ωt, we set , and solvefor ωt. Performing such a procedure results in,

(10)

• Note here that the unity-gain frequency is directly proportional to andinversely proportional to .

Slew Rate

Ceq v1Ceq CC 1 A2+( ) CCA2≈=

A1

v1vin------- gm1Zout1–= =

Zout1 rds2 rds41

sCeq-------------|| ||=

Zout11

sCeq-------------

1sCCA2------------------≅ ≅

Av s( )voutvin

----------≡ A3A2A1= A3A2

gm1sCCA2------------------≈

A3 1≅

Av s( )gm1sCC-----------=

Av jωt( ) 1=

ωta

gm1CC----------=

gm1CC

© K.W. Martin, 1997 5

• Slew-rate is the maximum rate at which the output changes when there are largeinput signals.

• For the op-amp above, when it slew-rate limits due to a large input signal present,all of the bias current of Q5 goes into either Q1 or Q2, depending on whetheris negative or positive. In either case, the maximum current going into or out of

is simply the total bias current, .

• Defining the slew-rate, , to be the maximum rate that can change (andhence ), we have

(11)

where we made use of the charge equation which leads to.

• Now since , we can also write

(12)

As well, from (10), we have , and substituting into (12), we

have

(13)

Recalling that

(14)

we finally have another relationship for the slew-rate value.

(15)

where

(16)

Vin

CC ID5SR v2

vout

SRd vout

d t--------------

max≡

ICC maxCC

--------------------ID5CC--------= =

q CV=I dq dt⁄ C dV dt⁄( )= =

ID5 2ID1=

SR2ID1CC

-----------=

CC gm1 ωta⁄=

SR2ID1ωta

gm1---------------------=

gm1 2µpCoxWL-----

1ID1=

SR 2ID1

2µpCoxWL-----

1ID1

------------------------------------------ωta Veff1ωta= =

Veff1 VGS Vt–2ID1

µpCox W L⁄( )1--------------------------------------= =

© K.W. Martin, 1997 6

• As a result, the only way of improving the slew rate for the two-stage CMOS op-amp (besides maximizing ) is to choose to be as large as possible. Thisis one of the major reasons for choosing p-channel input transistors rather than n-channel input transistors. Other reasons are less 1/f noise and higher unity-gainfrequency (as it is limited by the transconductance of the second stage).

Systematic Offset Voltage

• To guarantee that no systematic offset voltage occurs, one need ensure that for adifferential input voltage of zero, the gate voltage of results in .

Due to the symmetry of the circuit, for zero differential input voltage, the drain offollows that of and one can easily show that the following relationship

must hold for zero systematic offset voltage.

(17)

• Random variations result in offset-voltages on the order of 5 mV (or less).

ωt Veff1

Q7 ID7 ID6=

Q4 Q3

W L⁄( )7W L⁄( )4

-------------------- 2W L⁄( )6W L⁄( )5

--------------------=

© K.W. Martin, 1997 7

Feedback and Op-Amp Compensation

• This section discusses using op-amps in closed-loop configurations and how tocompensate an op-amp to ensure the closed-loop configuration is not only stable,but also has good settling characteristics.

First-Order Model of Closed-Loop Amplifier

• A simple first-order model for the transfer-function of a dominant-polecompensated op-amp, , is given by

(18)

where is the dc gain of the op-amp and is the (real-axis)

dominant pole.

• Since the unity-gain frequency of the op-amp, , is much higher than , wehave,

(19)

and thus the following important relationship for this first-order model.

(20)

• From here on, we define to be exactly equal to which isapproximately equal to the unity-gain frequency of the op-amp assuming afirst-order model for the op-amp.

• Substituting (20) into (18) for the case where , we have at mid-band frequencies

(21)

where for two-stage op-amp.

• This approximate relationship is often used to analyze a closed-loop circuit forthe effects of the op-amp’s finite bandwidth at mid-band frequencies.

Second-Order Model of Closed-Loop Amplifier

A s( )

A s( )Ao

1 s ωp1⁄+( )-------------------------------Ao

1 sτ1+( )-----------------------= =

Ao ωp1 1 τ1⁄=

ωta ωp1

A jωta( ) 1=Ao

ωta ωp1⁄-----------------------≈

ωta Aoωp1≈

ωta Aoωp1

ωp1 ω ωta« «

A s( )ωtas

--------≈

ωta gm1 CC⁄≈

© K.W. Martin, 1997 8

• When we are interested in accurately modelling the frequency response aroundthe unity-gain frequency of the op-amp, then (18) and (21) are inadequate. Wemust take into account higher-frequency poles and perhaps zeros. All of these canbe approximately taken into account by adding a single high-frequency pole

. is now given by

(22)

where is the time constant of the first dominant pole and

is the time-constant modelling higher frequency poles.

In practice, , is found from simulation as the inverse of the frequency at which

the transfer-function has a -135° phase shift (-90° due to the dominant pole andanother -45° due to the higher frequency poles and zeros).

• At frequencies much greater than the dominant pole frequency,, we see that and so (22) can be accurately

approximated by

(23)

where again for the two-stage op-amp.

• Recalling that the closed-loop gain is given by

(24)

we have using (23)

(25)

where

(26)

ωeq 1 τeq⁄= A s( )

A s( )A0

1 sτ1+( ) 1 sτeq+( )------------------------------------------------A0

1 sωp1----------+

1 sωeq----------+

---------------------------------------------------= =

τ1 1 ωp1⁄=

τeq 1 ωeq⁄=

τeq

ω ωp1» 1 τ1⁄= 1 jωτ1+ jωτ1≈

A s( )A0

sωp1--------- 1

sωeq---------+

----------------------------------≈

ωta

s 1s

ωeq----------+

----------------------------=

ωta A0ωp1 gm1 Cc⁄= =

ACL s( ) A s( )1 βA s( )+------------------------=

ACL s( )ACL0

1 sβωta-----------

s2

βωtaωeq---------------------+ +

-------------------------------------------------=

ACL0

A01 βA0+-------------------=

1β---≈

© K.W. Martin, 1997 9

• The result of (25) can be equated to the general equation for a second-order all-pole transfer function written as

(27)

where is called the resonant frequency and is called the Q-factor.

• Equating (25) with (27), and solving for and results in

(28)

and

(29)

• For good transient response, we prefer . Using (29), we see we need

(30)

• For the two-stage op-amp, where , we need

(31)

• In the case where , the poles are complex conjugate and the percentageovershoot of the output voltage for a step input change is given by

(32)

H2 s( )Kωo

2

s2 ωo

Q------- s ωo

2+ +

------------------------------------------K

1 sω0Q-----------

s2

ω02

-------+ +-----------------------------------= =

ωo Q

ωo Q

ω0 βωtaωeq=

Qβωtaωeq------------=

Q 1 2⁄=

βωtaωeq------------

14---=

ωta gm1 Cc⁄=

Cc

4βgm1ωeq

-----------------=

Q 0.5>

% overshoot 100e

π

4Q2

1–-----------------------–

=

© K.W. Martin, 1997 1 0

Op-Amp Compensation - Loop Response and Phase Margin

• Consider the transfer function for the loop-gain

(33)

• We have

(34)

• The unity-gain frequency, , of the loop-gain, LG(s), can now be found bysetting . This gives

(35)

For , and therefore from (30) , using (35) we get

which is slightly less than .

• The phase-margin, , is an often-used figure-of-merit for how far an op-ampwith feedback is from becoming unstable. It is defined as the difference betweenthe actual phase-shift and -180°. From (23), the actual phase-shift, , iseasily found as

(36)

implying that at the unity-gain frequency, , we have

(37)

and therefore for , and we get the required phase

margin is

(38)

For practical designs, we actually need more than this to account forprocessing and temperature variations. Prudent designers would normallydesign for to phase margins.

LG s( ) βA s( )=

LG s( )βA0

sωp1--------- 1

sωeq---------+

----------------------------------≅

βωta

s 1s

ωeq----------+

----------------------------=

LG ω( )βωtaω------------

1

1 ω ωeq⁄( )2+--------------------------------------=

ωtLG ωt( ) 1=

βωtaωeq----------

ωtωeq---------- 1

ωtωeq---------- 2

+=

Q 1 2⁄= βωta( ) ωeq⁄ 1 4⁄=

ωt ωeq⁄ 0.243= 1 4⁄

PM

LG jω( )∠

L∠ G jω( ) 90°– tan 1– ω ωeq⁄( )–=

s jωt=

PM L∠ G jωt( ) 180°–( )– 90° tan 1– ωt ωeq⁄( )–= =

Q 1 2⁄= ωt ωeq⁄ 0.243=

PM 76°=

80° 85°

© K.W. Martin, 1997 1 1

• Note that for a specified phase marging the unity-gain frequency of the loop isindependent of the the feedback factor, , and therefore of the closed-loop gain aswell, for an optimally compensated amplifier.

• It is now possible to relate a specified phase-margin to the Q-factor. Equation (37)can be used to find . This result can be substituted into (35) to find

, which can then be substituted into (29) to find the equivalent Q-factor. Finally, (32) can be used to find the corresponding percentage overshootfor a step input. This procedure allows the following table to be constructed.

Soon, we shall see that when lead-compensation is used, then an ration

of 0.7 can be achieved with greater than phase marging. This is a substantialimprovement over when lead compensation is not used and .

• It is worth mentioning here that in the case where the feedback network isfrequency independent and less than unity, (i.e. ), the worst-case phase-margin occurs for . Thus, for a general purpose op-amp where ,if the op-amp is compensated for , it is guaranteed to be stable for all other

although it will not be optimally compensated and will be slower thannecessary.

(Phase-Margin)

Q-factor%-overshoot for

a step input

55° 0.700 0.925 13.3%

60° 0.580 0.817 8.7%

65° 0.470 0.717 4.7%

70° 0.360 0.622 1.4%

75° 0.270 0.527 0.008%

β

ωt ωeq⁄β ωta ωeq⁄( )

PM ωt ωeq⁄

ωt ωeq⁄

80°ωt ωeq⁄ 0.25<

β 1≤β 1= 0 β 1≤<

β 1=β

© K.W. Martin, 1997 1 2

Compensating the Two-Stage Op-Amp

• Consider the first two stages of the two-stage op-amp as shown below.

• Capacitor, , realizes dominant-pole compensation. It controls the dominantfirst pole, (i.e. ), and thereby the frequency , since from (20)

(39)

• The transistor, , has since no dc bias current flows through itand is therefore hard in the triode region. Thus, this transistor operates as aresistor, , of value given by

(40)

• The reason for the inclusion of this transistor is to realize a left-half-plane zero atfrequencies around or slightly above resulting in lead-compensation.

• A simplified small-signal model for this op-amp is shown below,

• To see the need for , the analysis will first be done assuming .Performing nodal analysis at the nodes designated by v1 and vout, the followingtransfer function is obtained.

Q5

Q3 Q4

Q2Q1

Q6

Q7

VDD300

300300

150 150

300

300

Vin- Vin

+ Vout2

Vbias1

CcQ16

Vbias2

CCωp1 1 τ1⁄= ωta

ωta Aoωp1=

Q16 VDS16 0=

RC

RC rds161

µnCoxWL-----

16Veff16

--------------------------------------------------= =

ωt

RC RC 0=

© K.W. Martin, 1997 1 3

(41)

where

(42)

and

(43)

• It is possible to find approximate equations for the two poles based on theassumption that the poles are real and widely separated. This assumption allowsus to express the denominator, D(s), as

(44)

• Setting the coefficients of (41) equal to the coefficients of (44) and solving forand results in the following relationships. The dominant pole, , is

given by

(45)

gm1vin R1 C1

Cc Rc

gm7v1

v1vout

R2 C2

voutvin

----------

gm1gm7R1R2 1sCCgm7-----------–

1 sa s2b+ +---------------------------------------------------------------=

a C2 CC+( )R2 C1 CC+( )R1 gm7R1R2CC+ +=

b R1R2 C1C2 C1CC

C2CC

+ +( )=

D s( ) 1 sωp1----------+

1 sωp2----------+

= 1 sωp1----------

s2

ωp1ωp2--------------------+ +≈

ωp1 ωp2 ωp1

ωp11

R1 C1 CC 1 gm7R2+( )+[ ] R2 C2 C+C

( )+-----------------------------------------------------------------------------------------------------------≈

1R1CC 1 gm7R2+( )------------------------------------------------≈

1gm7R

1R2CC

----------------------------------≈

© K.W. Martin, 1997 1 4

while the non-dominant pole, , is given by

(46)• Note that from (41), there is also a zero, , located in the right-half-plane given

by

(47)

(Note that is the coefficient in the factor and therefor a negative

sign represents a right-half-plane zero)

• Making larger leaves the second pole larger unaffected but moves the firstpole to a lower frequency. This ‘pole-splitting’ minimizes the affect of the secondpole.

• A problem arises due to the right-half-plane zero, . Because the zero is in theright-half-plane, it introduces negative phase-shift (or phase-lag) in the transferfunction of the op-amp. This makes achieving stability more difficult. Making

larger does not help because it decreases the frequencies of both the first poleand the zero without making them more widely separated.

• Fortunately, all is not lost, as introducing allows adequate compensation, aswill be discussed next.

ωp2

ωp2

gm7CCC1C2 C2CC C1CC+ +----------------------------------------------------------≈

gm7C1 C2+--------------------≈

ωz

ωz

gm7CC----------–=

ωz 1 s ωz⁄+( )

CC

ωz

CC

RC

© K.W. Martin, 1997 1 5

Lead Compensation

• If the small-signal model is re-analyzed, but with RC non-zero, then a third orderdenominator results. The first two poles are still approximately at the frequenciesgiven by (45) and (46). The third pole is at a high frequency and has almost noeffects.

• The zero is now determined by the relationship,

(48)

• This result allows the designer a number of possibilities. One could take

(49)

to eliminate the right-half-plane zero altogether.

• Alternatively, one could consider choosing to be even larger and thus movethe right-half-plane zero into the left-half-plane to cancel the non-dominant pole,

. Setting (48) equal to (46) and solving for results in the followingequation for .

(50)

• Unfortunately, is often not known a priori, especially when no output stage ispresent.

• The third possibility is to choose even larger yet to move the now left-half-plane zero to a frequency slightly greater than the unity-gain frequency thatwould result if the lead-resistor was not present — say, 20% larger. For this case,one should satisfy the following equation

(51)

and assuming , then and recalling

then one should choose according to

(52)

ωz1

CC RC 1 gm7⁄–( )---------------------------------------------=

RC 1 gm7⁄=

RC

ωp2 RCRC

RC1

gm7---------- 1

C1 C2+

CC--------------------+

=

C2

RC

ωz 1.2ωt=

RC 1 gm7⁄» ωz 1 RCCC( )⁄≈

ωt gm1 CC⁄≈ RC

RC1

1.2gm1------------------≈

© K.W. Martin, 1997 1 6

Compensation Pocedure

The recommended procedure for compensation is as follows:

a) Start by choosing somewhat arbitrarily pF.

b) Using SPICE, find the frequency where there is a -125° phase shift. Let the gain atthis frequency be denoted A'. Also let the frequency be denoted ωt. This is the

frequency that we would like to become the unity-gain frequency of the loop gain.

c) Choose a new so that becomes the unity-gain frequency of the loop-gain,thus resulting in a phase-margin (and the reason for the choice of -125° usedabove). This can be achieved by taking according to the equation

(53)

It might be necessary to iterate on a couple of times using SPICE.

d) Choose RC according to

(54)

This choice will increase the unity-gain frequency by about 20%, leaving the zeronear to the final resulting unity-gain frequency, which will end up about 15% belowthe the equivalent second pole frequency. The resulting phase margin isapproximately 1. This allows a margin of to account for processingvariations without the poles of the closed-loop response becoming real. This choiceis also near optimum lead-compensation for almost any opamp when a resistor isplaced in series with the compensation capacitor. It might be necessary to iterate on

a couple of times to optimize the phase-margin. However, it should be checkedthat the gain continues to steadily decrease at frequencies above the new unity-gainfrequency, otherwise the transient response can be poor. This situation sometimesoccur when unexpected zeros at frequencies only slightly greater than are present.

e) If after d), the phase-margin is not adequate, then increase CC while leaving RCconstant. This will move both and the lead-zero to lower frequencies, whilekeeping their ratio approximately constant, thus minimizing the effects of higher-frequency poles and zeros which, hopefully, do not also move to lower frequencies.In most cases, the higher-frequency poles and zeros (except for the lead zero) will notmove to significantly-lower frequencies when increasing .

Making Compensation Independent of Process and

1. The first pole contributes phase margin, the lead zero contributes approximately phase margin, and the

equivalent second pole contibutes approximately phase margin.

CC ′ 5≅

CC ωt55°

CCCC CC ′A ′=

CC

RC1

1.2ωtCC----------------------=

85°– 5°

90°– 45°45°–

RC

ωt

ωt

CC

© K.W. Martin, 1997 1 7

Temperature

In this section, it is shown how lead-compensation can be made process andtemperature insensitive. Re-iterating equations (10), and (46), we have

(55)

and

(56)

• We see here that the second pole is proportional to the transconductance of thedrive transistor of the second stage, . Also, the unity-gain frequency isproportional to the transconductance of the input transistor of the first stage,

. Furthermore, the ratios of all of the transconductances remain relativelyconstant over process and temperature variations since the transconductances areall determined by the same biasing network. As well, most of the capacitancesalso track each other since they are primarily determined by gate oxides.Repeating (48), when a resistor is used to realize lead compensation, the leadzero is at a frequency given by

(57)

• Thus, if RC can also be made to track the inverse of transconductances, and inparticular 1/gm7, then the lead zero will also be proportional to thetransconductance of . As a result, the lead zero will remain at the samerelative frequency with respect to and , as well as all other high-frequency poles and zeros. In other words, the lead-compensation will be mostlyindependent of process and temperature variations.

• RC can be made proportional to as long as is realized by a transistorin the triode region having an effective gate-source voltage proportional to that of

. To see this result, recall that is actually realized by , and thereforewe have

(58)

Also, is given by

(59)

ωt

gm1CC----------=

ωp2

gm7C1 C2+--------------------≈

gm7

gm1

ωz1

CC 1 gm7⁄ RC–( )---------------------------------------------=

Q7ωt ωp2

1 gm7⁄ RC

Q7 RC Q16

RC rds161

µnCox W L⁄( )16Veff16---------------------------------------------------------= =

gm7

gm7 µnCox W L⁄( )7Veff7=

© K.W. Martin, 1997 1 8

• Thus the product , which is desired to be a constant, is given by

(60)

• Therefore, all that remains is to ensure that is independent ofprocess and temperature variations since clearly the remaining terms depend onlyon a geometric relationship. The ratio can be made constant byderiving from the same biasing circuit used to derive . Specifically,consider the circuit shown below, It is straightforward to show that

(61)

which is only dependant on geometry and not on processing or temperaturevariations.

• As a result, we have guaranteed that the drain-source resistance of a transistor inthe triode region is inversely matched to the transconductance of a differenttransistor.

• This relationship can be very useful for many other applications as well. Indeed,in the next section, we will see that it’s quite simple to make all of thetransconductances of transistors in an IC match the conductance of a single off-

The bias circuit, second-stage and compensation circuit of the two-stage op-amp.

Rcgm7

RCgm7

W L⁄( )7Veff7W L⁄( )16Veff16

---------------------------------------=

Veff16 Veff7⁄

Veff16 Veff7⁄VGS16 VGS7

Q11

Q12

Q13Q15

Q14

Q6

Q7

RB

CC

2525

25 25

25100

300

300

Q16

Q10

Va

Vb

RCgm7

W L⁄( )7W L⁄( )16

-----------------------W L⁄( )12W L⁄( )13

-----------------------=

© K.W. Martin, 1997 1 9

chip resistor. This approach results in the possibility of on-chip “resistors”,realized using triode-region transistors, that are accurately ratioed with respectto a single off-chip resistor.

© K.W. Martin, 1997 2 0

Biasing an Op-Amp to Have Stable Transconductances

• This stabilization can be achieved by using a circuit approach first proposed in[Steininger, 1990] where transistor transconductances are matched to theconductance of a resistor. As a result, to a first-order effect, the transistortransconductances are independent of power-supply voltage, as well as processand temperature variations.

• For convenience, the bias-circuit above is shown again.

• First, it is assumed that . This equality results in bothsides of the circuit having the same current due to the current-mirror pair

. As a result, we also must have . Now, around the loopconsisting of , , and , we have

(62)

and recalling that , we can subtract the threshold voltage, ,

from both sides resulting in

(63)

This equation can also be written as

(64)

and since , we can also write

Q11

Q12

Q13Q15

Q14

RB

2525

25 25

25100

Q10

W L⁄( )10 W L⁄( )11=

Q10 Q11, ID15 ID13=Q13 Q15 RB

VGS13 VGS15 ID15RB+=

Veffi VGSi Vt–= Vt

Veff13 Veff15 ID15RB+=

2ID13µnCox W L⁄( )13----------------------------------------

2ID15µnCox W L⁄( )15---------------------------------------- ID15RB+=

ID13 ID15=

© K.W. Martin, 1997 2 1

(65)

Re-arranging, we obtain

(66)

and recalling that results in the important

relationship

(67)

• Thus, the transconductance of is determined by geometric ratios only,independent of power-supply voltages, process parameters, temperature, or anyother parameters with large variability. For the special case of

, we have simply

(68)

• Note that, not only is stabilized, but all other transconductances are alsostabilized since all transistor currents are derived from the same biasing network,and, therefore, the ratios of the currents are mainly dependant on geometry. Wethus have for all n-channel transistors

(69)

and for all p-channel transistors

(70)

• It should be noted here that the above analysis has ignored transistor output-impedance. This effect can be made of little consequence by replacing the simplecurrent mirrors with cascode mirrors.

2ID13µnCox W L⁄( )13----------------------------------------

2ID13µnCox W L⁄( )15---------------------------------------- ID13RB+=

2

2µnCox W L⁄( )13ID13

----------------------------------------------------------- 1W L⁄( )13W L⁄( )15

-----------------------–

RB=

gm13 2µnCox W L⁄( )13ID13=

gm13

2 1W L⁄( )13W L⁄( )15

-----------------------–

RB---------------------------------------------=

Q13

W L⁄( )15 4 W L⁄( )13=

gm131

RB-------=

gm13

gmi

IDiID13-----------gm13=

gmi

µpµn------

IDiID13-----------gm13=

© K.W. Martin, 1997 2 2

• Also note that the above circuit can have a second stable state where all thecurrents are zero. To guarantee this condition doesn’t happen, it is necessary toadd a “start-up circuit” which only effects the operation if all the currents are zeroat start up.

© K.W. Martin, 1997 2 3

Wide-Swing Current-Mirror

• The “wide-swing cascode current-mirror” is shown below [Babanezhad, 1987].

• The basic idea is to bias the transistors closest to ground to have almost theminimum possible drain-source voltages without going into the triode region.

• Before seeing how these bias voltages are created, note that the transistor pairact like a single diode-connected transistor in creating the gate-source

voltage for . These two transistors operate very similar to how alonewould operate if its gate was connected to its source.

• To determine the bias voltages for the above circuit, let be the effective gate-source voltage of Q2 and Q3 and assume all of the drain currents are equal. Wetherefore have

(71)

• Since has the same drain current but is times smaller, we have

(72)

• Similar reasoning results in the effective gate-source voltages of andbeing given by

(73)

Thus,

(74)

and

Q5Q4

Q3 Q2

Q1

W L⁄n 1+( )2

-------------------

W L⁄n2

-------------W L⁄

n2-------------

W L⁄W L⁄

Ibias Iin VoutIout Iin=

Vbiasn 1+( )Veff Vtn+

VGS4 VGS1 nVeff Vtn+= =

Veff

Q3 Q4,Q3 Q3

Veff

Veff Veff2 Veff3

2ID2µnCox W L⁄( )-----------------------------------= = =

Q5 n 1+( )2

Veff5 n 1+( )Veff=

Q1 Q4

Veff1 Veff4 nVeff= =

VG5 VG4 VG1 n 1+( )Veff Vtn+= = =

© K.W. Martin, 1997 2 4

(75)

• This drain-source voltage puts both Q2 and Q3 right at the edge of the trioderegion. Thus, the minimum allowable output voltage is now

(76)

• A common choice for might be simply unity, in which case the current mirroroperates correctly as long as

(77)

• With a typical value of Veff between 0.2V and 0.25V, the wide-swing current-mirror can guarantee all of the transistors are in the active (i.e. saturation) regioneven when the voltage drop across the mirror is as small as 0.4V to 0.5V.

• There is one other requirement that must be met to ensure all transistors are in theactive region. Specifically, we need

(78)

to guarantee that is in the active region.

• To find , we note that the gate of is connected to the drain ofresulting in

(79)

• As a result, one need only ensure that be greater than for toremain in the active region (not a difficult requirement).

• In most applications, an experienced designer might take (W/L)5 smaller than thesize shown above to bias transistors Q2 and Q3 with slightly larger drain-sourcevoltages than the minimum required (perhaps 0.1V to 0.15V larger).

• Q2 and Q3 might be chosen to have length just a little larger than the minimumallowable gate length (as the voltage across them is quite small) but Q1 and Q4might be chosen to have longer gate lengths since the output transistor (i.e. Q1)often has larger voltages across it. Minimizing the lengths of Q2 and Q3maximizes the frequency response, as their gate-source capacitances are the mostsignificant capacitances contributing to high frequency poles.

VDS2 VDS3 VG5 VGS1– VG5 nVeff Vtn+( )– Veff= = = =

Vout Veff1 Veff2+> n 1+( )Veff=

n

Vout 2Veff>

VDS4 Veff4> nVeff=

Q4

VDS4 Q3 Q4

VDS4 VG3 VDS3– Veff Vtn+( ) Veff– Vtn= = =

Vtn nVeff Q4

© K.W. Martin, 1997 2 5

Wide-Swing Constant-Transconductance BiasCircuit

• It is possible to include the wide-swing current-mirrors into the constant-transconductance bias circuit [Martin, 1985]. This eliminates many of the second-order errors of the constant transconductance circuit and is still useable at 3Vpower supplies voltages.

• Notice that a start-up circuit has been included in a real implementation.

• Notice also that cascode transistors are taken as , whereas common-sourcetransistors are

Bias Loop Cascode Bias Start-Up Circuitry

Q3Q2

Q4Q1

Q7

Q6Q9

Q8Q11

Q10

Q5 Q12

Q14

Q15

Q17

Q18

Q13

RB

Small W/L

10/1.6

10/1.610/140/1

20/1

20/1.6

20/1

20/1.620/1.6

20/1

10/1.6

10/12.6/1.6

10/1

10/1

2/20

2.6/1.6

10/1

Q16

Vbias-n

Vcasc-n

Vbias-p

Vcasc-p

2Lmin1.2Lmin

© K.W. Martin, 1997 2 6

Enhanced Output-Impedance

• The basic idea is to use a feedback amplifier to keep the drain-source voltageacross Q2 as stable as possible, irrespective of the output voltage. The addition ofthis amplifier ideally increases the output impedance by a factor equal to one plusthe loop gain over that which would occur for a classical cascode current-mirror.

• The implementation proposed by Säckinger is shown below.

Iout

AVbias

Q1

Q2

IinVout

Q3

rout

rout gmrds2 1 A+( )≈

Iout

Q1

Q2

IB1IB2Iin

Q3

Q4

Q5

Q6

© K.W. Martin, 1997 2 7

• The feedback amplifier in this case is realized by the common-source amplifierconsisting of Q3 and its current source IB1. Assuming the output impedance ofcurrent-source IB1 is approximately equal to rds3, the loop-gain will be

, and the final ideal output impedance will be given by

(80)

• The circuit consisting of Q4, Q5, Q6, Iin, and IB2 operates almost identically to adiode-connected transistor, but is instead used to guarantee that all transistor biasvoltages are accurately matched to those of the output circuitry consisting of Q1,Q2, Q3, and IB1. As a result, will very accurately match Iin.

• This realization has a major limitation that the signal swing is significantlyreduced. This reduction is a result of Q2 and Q5 being biased to have drain-sourcevoltages much larger than the minimum required.

• For a wide-swing current mirror with enhanced output-impedance [Gatti, 1990]and [Coban, 1994], [and myself after the fact]. is used as a level-shift to bias

near the edge of the active region.

• Output-impedance enhancement significantly increases the gain, has little effecton the small-signal transfer function, but significantly degrades the large-signaltransient response (by about 50%) due to large voltage excursions at the gate of

during slew-rate limiting.

gm3rds3( ) 2⁄

rout

gm1gm3rds1rds2rds32

-------------------------------------------------------≅

Iout

Q4

Q1

Q2

Q3Q4

Q6

Q7

70

70

10

70

70

10

Ibias

4IbiasIin Iout Iin=

Q5

10

Vcasc-n

Q2

Q1

© K.W. Martin, 1997 2 8

Folded-Cascode Op-Amp

• An example of an op-amp with a high-output impedance is the folded-cascodeop-amp as shown below.

• Although a folded-cascode amplifier is basically a single gain-stage, its gain canbe quite reasonable, on the order 700 to 3,000 typically. Such a high gain occursbecause the gain is determined by the product of the input transconductance andthe output impedance, and the output impedance is quite high due to the use ofcascode techniques.

• The shown differential-to-single-ended conversion is realized by the wide-swingcurrent-mirror composed of Q7, Q8, Q9, and Q10. In a differential-output design,these might be replaced by two wide-swing cascode current sinks, and common-mode feedback circuitry would be added, as is discussed later.

• Two extra transistors, and , have been included to increase the slew-rateperformance of the op-amp. Also, more importantly, during times of slew-ratelimiting, these transistors prevent the drain voltages of and having largetransients where they change from their small-signal voltages to voltages veryclose to the negative power-supply voltage.

Ibias1

Ibias2

Q1 Q2

Q3 Q4Q11

Q12 Q13Q5 Q6

Q7

Q9 Q10

Q8

VinVout

CL

VB1

VB2

τ2

Cgs6 Cdb4 Cdb1+ +

gm6------------------------------------------------≈

Q12 Q13

Q1 Q2

© K.W. Martin, 1997 2 9

• The compensation is realized by the load capacitor, CL, and realizes dominant-pole compensation.

Small-Signal Analysis

• In a small-signal analysis of the folded-cascode amplifier, it is assumed that thedifferential output current from the drains of the differential-pair, , isapplied to the load capacitance, .

(81)

where is the transconductance of each of the transistors in the input

differential-pair and is the impedance to ground seen at the output node.

(82)

where is the output impedance of the op-amp.

• For mid-band and high frequencies, we can ignore the unity term in thedenominator and thus have,

(83)

from which the unity-gain frequency of the op-amp is easily found to be

(84)

• Therefore, for large load capacitances, maximizing the transconductance of theinput transistors maximizes the bandwidth, assuming the load capacitance is largeenough so that the unity-gain frequency is much less than the limit imposed bythe second poles. The transconductance of the input transistors is maximized byusing wide n-channel devices and ensuring the input-transistor-pair’s bias currentis substantially larger than the bias-current of the cascode transistors and current-mirror.

• Note that this approach also maximizes the dc gain (i.e. ) since not onlydoes it maximize , but it also maximizes by resulting in all transistorsconnected to the output node being biased at lower current levels (for a giventotal power dissipation).

Q1 Q2,CL

AV

vout s( )vin s( )------------------- gm1ZL s( )= =

gm1

ZL s( )

AV

gm1rout1 sroutCL

+------------------------------=

rout

AV

gm1sCL----------≅

ωta

gm1CL----------=

gm1routgm1 rout

© K.W. Martin, 1997 3 0

• The second-poles of this op-amp are primarily due to the time-constantsintroduced by the impedance and parasitic capacitances at the sources of the p-channel cascode transistors, and . The impedances at these nodes is oneover the transconductances of the cascode transistors. Since p-channel transistorsare used here, possibly biased at lower currents, these impedances are typicallysubstantially greater than the source-impedances of most n-channel transistors inthe signal path. As a consequence, when high-frequency operation is important,these impedances can be reduced by making the currents in the p-channelcascode transistors around the same level as the bias-currents of the inputtransistors.

• The parasitic capacitance at the sources of the cascode transistors is primarily dueto the gate-source capacitances of the cascode transistors as well as the drain-to-bulk and drain-to-gate capacitances of the input transistors and the current-sourcetransistors Q3 and Q4. Therefore, minimizing junction areas and peripheries atthese two nodes is important.

Slew-Rate

• The diode-connected transistors, Q12 and Q13, are turned-off during normaloperation and have almost no effect on the op-amp. However, they substantiallyimprove the operation during times of slew-rate limiting [Law, 1993].

• To appreciate their benefit, consider first what happens during times of slew-ratelimiting when they are not present. Assume there is a large differential inputvoltage that causes Q1 to be turned on hard and Q2 to be turned off. Since Q2 isoff, all of the bias-current of Q4 will be directed through the cascode transistorQ5, through the n-channel current-mirror, and out of the load capacitance. Thus,the output voltage will decrease linearly with a slew-rate given by

(85)

• Also, since all of is being diverted through Q1, and since this current isusually designed to be greater than , both Q1 and the current-sourcewill go into the triode region causing to decrease until it is equal to .

• As a result, the drain voltage of Q1 approaches that of the negative power-supplyvoltage. When the op-amp is coming out of slew-rate limiting, the drain voltageof must slew back to a voltage close to the positive power-supply before theop-amp operates in its linear region again. This additional slewing time greatlyincreases the distortion and also increases the transient times during slew-rate

Q5 Q6

SRID4CL--------=

Ibias2ID3 Ibias2Ibias2 ID3

Q1

© K.W. Martin, 1997 3 1

limiting (which occurs often for op-amps used in switched-capacitorapplications).

• Next, consider the case where the diode-connected transistors, Q12 and Q13, areincluded. One effect is to clamp the drain voltages of or so they don’tchange as much during slew-rate limiting.

• A second, more-subtle effect dynamically increases the bias currents of both Q3and Q4 during times of slew rate limiting. This increased bias current results in alarger maximum current available for charging or discharging the loadcapacitance.

• To see this increase in bias current, consider the same case as above where a largedifferential input causes to be fully on while is off. In this case, thediode-connected transistor Q12 conducts where the current through it comes fromthe bias diode-connected transistor, Q11. Thus, the current in increasescausing the currents in bias-transistors Q3 and Q4 to also increase until the sum ofthe currents of Q12 and Q3 are equal to the bias current . Note that thecurrent in Q4 also increases since it is equal to the current in Q3. This increase inbias-current of Q4 results in an increase of the maximum current available fordischarging .

• In summary, not only are the voltage excursions less, but the maximum availablecurrent for charging or discharging the load capacitance is also greater duringtimes of slew-rate limiting.

Q1 Q2

Q1 Q2

Q11

Ibias2

CL

© K.W. Martin, 1997 3 2

Equivalent Second-Pole Frequency

• There are three important internal nodes having time constants that contribute tothe second-equivalent-pole-frequency: these are the source nodes of the common-source transistors and , and the input node of the n-channel current mirror(i.e. the gate nodes of and ). Since and are p-channel transistors,the time constants at these nodes are probably dominant, although since there aretwo gates connected to the input node of the current mirror, the time constantthere can be significant.

• Consider the time constant at the source of and assume is thedominant capacitance. In analog circuits, the gate-source capacitances normallydominate since the transistors are often quite wide and junction capacitances canoften be minimized by careful layout techniques..

• At the source of , the impedance is approximately given by

(86)

Approximating the total capacitance by the gate-source capacitance of , we

have

(87)

and the time constant at the node is approximately given by

(88)

Note that for a given effective gate-source voltage, the time constant is relativelyindependent of any design parameters and primarily dependent on technology.Often the 2/3’s factor is dropped to roughly take into account the junctioncapacitance which was ignored. For , ,and , this gives . This corresponds to an equivalent-second-pole-frequency of or .Assuming is 1/4 times , gives . Normally, this would bedominated by the load capacitance.

• By symmetry, the time constant at the source of will have a similar effect inthe other differential signal path. The time constant due to the n-channel current

Q5 Q6Q9 Q10 Q5 Q6

Q5 Cgs-5

Q5

R51

gm5----------

1µpCox W L⁄( )5Veff-5----------------------------------------------------= =

Q5

C523--- WL( )5Cox=

τ523---

L52

µpVeff-5---------------------=

µp 0.0175m2 V s⋅⁄= Veff-5 0.25V=L5 0.4µm= τ5 36.6ps=

ωeq 1 τ5⁄≈ 2.710×10 r s⁄= feq 4.3GHz=

ft feq ft 1.1GHz=

Q6

© K.W. Martin, 1997 3 3

mirror may be significant but is unlikely to decrease by more than about1/3’rd.

• Thus, for the folded-cascode op-amp, normally the load capacitance will begreater than is needed for stability (assuming ) and will cause theunity-gain frequency to be significantly less than that constrained by thetime constants of the internal nodes. Furthermore, there is little incentive touse p-channel transistors for the input differential-pairs (i.e. thecomplementary op-amp) in order to minimize the internal time constants.

ϖeq

CL 2pF>

© K.W. Martin, 1997 3 4

Current-Mirror Op-Amp (CMA)

• All nodes are low impedance except for the output node.

• By using good current-mirrors having high output-impedance, a reasonable over-all gain can be achieved.

• Example of an CMA with wide-swing current mirrors is shown below.

Ib

Q1 Q2Vin

Vout

CL

1:K

1:K

1:1

KID1

KID2

Ib

Q1 Q2Vin

Vout

CL

VB2 VB2

VB1

Q5

Q3 Q4

Q6 Q7

Q9

Q11

Q14

Q12

Q10

Q8

Q13

ID14 = KI1 = KIb/2

τ2

Cgs5 Cgs8 Cdb1 Cdb3+ + +

gm5------------------------------------------------------------------≈

© K.W. Martin, 1997 3 5

• Similar analysis to that given for the folded-cascode op-amp, we have

(89)

• The factor is the current-gain from the input transistors to the output sides ofthe current-mirrors connected to the output node. Using (89), we can solve for theunity-gain frequency resulting in

(90)

• If the power dissipation is specified, the total current,

(91)

is known for a given power-supply voltage. Substituting (91) into (90), we obtain

(92)

• For larger values of , the op-amp’s transconductance is larger (i.e. ), andtherefore, the unity-gain frequency is also larger.

• This simple result assumes the unity-gain frequency is limited by the loadcapacitance rather than any high-frequency poles caused by the time-constants ofthe internal nodes.

• A practical upper limit on might be around 5. The use of large values alsomaximizes the gain for fixed since is roughly independent of forlarge . In other words, for fixed and large , the current through theoutput stage is almost equal to .

• The important nodes for determining the non-dominant poles are the drain of Q1,primarily, and the drains of Q2 and Q9, secondly. Increasing increases thecapacitances of these nodes while also increasing the impedances and thus theequivalent second pole moves to lower frequencies.

• If it is very important that speed is maximized, might be taken as small as 1. Areasonable compromise for a general purpose op-amp might be to let .

Slew-Rate

AV

vout s( )vin s( )------------------ Kgm1ZL s( )

Kgm1rout1 sroutCL

+------------------------------

Kgm1sCL

---------------≅= = =

K

ωta

Kgm1CL

---------------K 2ID1µnCox W L⁄( )1

CL----------------------------------------------------------= =

Itotal 3 K+( )ID1=

ωta

K 2Itotal3 K+-------------µnCox W L⁄( )1

CL----------------------------------------------------------------

K

3 K+-----------------

2ItotalµnCox W L⁄( )1CL

---------------------------------------------------------= =

K Kgm1

K KItotal rout K

K Itotal KItotal 2⁄

K

KK 2=

© K.W. Martin, 1997 3 6

• All of the bias-current of the first stage will be diverted through either Q1 or Q2and amplified by the current gain of the output stage.

(93)

• For a given total power dissipation, this slew-rate is maximized by choosing alarge value.

• For example, with and during slew-rate limiting, 4/5 of the total bias-current of the op-amp will be available for charging or discharging .

• This result gives a CMA superior slew-rates when compared to a folded-cascodeop-amp, even when the clamp transistors have been included in the folded-cascode op-amp. Also, there are no problems with large voltage transients duringslew-rate limiting for the CMA.

• In summary, due primarily to the larger bandwidth and slew rate, the CMA isusually preferred over a folded-cascode op-amp.

• However, it will suffer from larger thermal noise when compared to a folded-cascode amplifier because its input transistors are biased at a lower proportion ofthe total bias current and therefore have a smaller transconductance.

SRKIbCL---------=

K

K 4=CL

© K.W. Martin, 1997 3 7

Equivalent Second-Pole Frequency

• There are three important internal nodes having time constants that contribute tothe second-equivalent-pole-frequency: these are the input nodes of the currentmirrors.

• Consider the node at the gate of : the impedance is approximately given by

(94)

Approximating the total capacitance by the gate-source capacitances of and

, and assuming , and therefore , we have

(95)

and the time constant at the node is approximately given by

(96)

Note that for a given effective gate-source voltage, the time constant is relativelyindependent of any design parameters and primarily dependent on technology. Toroughly take into account the junction capacitance which was ignored we canreplace the 2 factor by 2.5. For , , and

, this gives . This corresponds to an equivalent- second-pole-frequency of or . Assumingis 1/4 times , gives . Normally, this would be dominated by theload capacitance.

Q5

R51

gm5----------

1µpCox W L⁄( )5Veff-5----------------------------------------------------= =

Q5

Q8 K 2= W8 2W5=

C523--- 3WL( )5Cox=

τ5 2L5

2

µpVeff-5---------------------=

µp 0.0175m2 V s⋅⁄= Veff-5 0.25V=L5 0.4µm= τ5 91ps=

ωeq 1 τ5⁄≈ 1.110×10 r s⁄= feq 1.7GHz= ft

feq ft 435MHz=

© K.W. Martin, 1997 3 8

Fully-Differential Folded-Cascode Op-Amp

Fully-Differential CMA

Ibias

Q1 Q2

Q3 Q4

Q5 Q6

Q8

Q7Q9

Q10

Vin

Vout

VB2

VB1

VB3

CMFBCircuit

Vcntrl

Q11 Q12

Ibias

Q1 Q2

Q4

Q3Q5

Q6

Vin

Vout

VB3

CMFBCircuit

Vcntrl

1:K

1:K

© K.W. Martin, 1997 3 9

Common-Mode Feedback Circuits

• A continuous-time CMFB circuit is shown above.

• It has a major limitation in that the voltage drop across the source-followertransistors, , severely limits the differential signals that can be processed(unless transistors with native threshold voltages, such as 0.3 volts, are available).

• The stability of the CMFB loop should be checked separately. Normally, its speedshould match that of the differential loop. Since the same capacitors are used tocompensate both loops, the only degree of freedom for the CMFB loop is thegain. This does not need to be large.

• Stability can be especially difficult to achieve when the differential gain is large

• A higher linearity CMFB circuit is shown below [Martin, 1985] [Gray, 1986][Whatly,1986].

• Assuming the CMRR is perfect, this CMFB is perfectly linear irrespective of thenon-linearity of the transistors.

• It should be designed so that for the maximum expected input signal, when thebias current sources are at the edge of the triode region, the transistors in thedifferential pair are all still conducting somewhat. This limits swings in thepositive going direction to be not closer than within the positive powersupply voltage.

• A modified version of this CMFB with more gain is shown below [Duque, 1993]

• These CMFB circuits would be greatly improved if low-threshold devices wereused for the differential pairs.

Vout+ Vout

-

Vcntrl

1.5pF

20kΩ

1.5pF

20kΩ

VA VCM Veff1 Vt1+( )–=

Vref

Vref Veff1 Vt1+( )–=

VA

Q1 Q2

Q1 Q2,

Vtp 2Veff+

© K.W. Martin, 1997 4 0

• A switched-capacitor CMFB circuit is shown below [Senderowicz, 1982].

• In this approach, the capacitors labelled CC generate the average of the outputvoltages which is used to create control voltages for the op-amp current sources.The dc voltage across CC is determined by capacitors CS which are switched

An example of a continuous-time CMFB circuit.

A modified CMFB circuit having twice the common-mode gain as compared tothe previous realization.

IBIB

Vcntrl

IB/2-∆I

IB/2+∆I IB/2-∆I

IB/2+∆I

IB

IB

Q1

Q2Q3

Q4

Q5

Q6

Vout+ Vout-

IBIB

vcntrl

IB/2-∆Ib

IB/2+∆Ib IB/2-∆Ib

IB/2+∆Ib

IB

IB

Q1

Q2Q3

Q4

Q5

Q6

Q7

IBVout+ Vout-

© K.W. Martin, 1997 4 1

between bias voltages and between being in parallel with CC. This circuit actsmuch like a simple switched-capacitor low-pass filter having a dc input signal.The bias voltages are designed to be equal to the difference between the desiredcommon-mode voltage and the desired control voltage used for the op-ampcurrent sources.

• In applications where the op-amp is being used to realize switched-capacitorcircuits, switched-capacitor CMFB circuits are generally preferred over theircontinuous-time counterparts since they allow a larger output signal swing.

• When continous-time CMFB is required, the CMFB circuit is the majorlimitation on the signal-swing.

φ1 φ2

φ1 φ2

CCCS

φ1φ2

φ1φ2

CC CS

Vcntrl

Vo+ Vo-

VBIAS

© K.W. Martin, 1997 4 2

Alternative Fully-Differential Configurations• A current-mirror op-amp with bi-directional drive capability is shown below. This

has a much improved slew rate in the negative direction (for an n-channeldifferential pair).

• Another alternative with bi-directional drive capability is shown below[Castello,1989]. This configuration has a very-good slew rate but poor signal swing.

• Another alternative with bi-directional frive capability is shown below. It consistsof two single-ended output op-amps connected in parallel to get a differentialoutput op-amp.

• A low-voltage op-amp capable of handling large input common-mode voltages isshown below [Babanezhad, 1988] [Hogervorst, 1992] [Coban, 1994]. This circuit can have atransconductance and input offset voltage that are dependent on input CM voltage.

A fully-differential opamp with bi-directional output drive.

Vin+

Ibias

Vout+ Vout-

Q1 Q2

1:K

1:11:1

1:KK:1

Vin-

K:1

© K.W. Martin, 1997 4 3

A class AB fully-differential opamp. CMFB circuit not shown.

A fully-differential opamp composed of two single-ended output current-mirroropamp’s. CMFB circuit not shown.

Vin+ Vin-Vout-Vout+

Q1

Q2

Q8

Q3 Q7

Q4

Q5

Q6

1:K

1:K

K:1

K:1

Vin+ Vin-

Vout-Vout+1:K

1:K1:11:1

K:1

K:1

© K.W. Martin, 1997 4 4

An opamp having rail-to-rail input common-mode voltage range. CMFB circuitnot shown.

Vin+ Vin

-

Vsp

Vsn

Vout+ Vout

-

Vb1

Vb2

Q1 Q2

Q5

Q3 Q4

Q6

Q9 Q10

Q7 Q8

M1

M2

I1

I2I1

© K.W. Martin, 1997 4 5

Current-Feedback Amplifiers

[Comlinear, 1985], [Bowers, 1990]

Advantages:• Open-loop gain is independent of closed-loop gain. Thus, a single size

compensation capacitor can be used irrespective of gain. Furthermore, closed-loop -3dB frequency is approximately independent of closed-loop gain.

• The amplifier almost never slew-rate limits.

• Amplifier is very fast due to all internal nodes being low impedance.

Disadvantages:• Requires complementary process (i.e. vertical pnp’s if bipolar).

• First commercially available designs have larger input referred noise and inputoffset voltages, as compared to voltage-mode amplifiers. These limitations maypossibly be minimized in the future by careful circuit design.

© K.W. Martin, 1997 4 6

Simplified Schematic

Current-mirrors would normally be Wilson current-mirrors.

Assume 1/gm1, 1/gm2 << R1 || R2.

Thus,

vx ≅ vin (97)

And,

(98)

And

Wilson CurrentMirror

R2

R1

FeedbackResistors

1

if

IR + if2

IR - if2

IR + if2

RoCc

if

IR - if2

IR

IR

Unity-GainBuffer

vout

vxvin

ifνout ν in–

R2------------------------

ν inR1-------–=

if⇒νoutR2

----------- ν in1

R1-------

1R2-------+

–=

© K.W. Martin, 1997 4 7

(99)

where

(100)

The open-loop gain is given by

(101)

Thus, LG(s) is independent of R1! Therefore, R1 can be changed as desired torealize any closed-loop gain without affecting the stability.

Setting

(102)

For the closed-loop gain, substitute (3), (4) into (2) and simplify to get.

(103)

(104)

For R0 >> R2, we have

(105)

• Thus, the -3dB frequency of Acl(s) is approximately equal to the unity-gainfrequency of the open-loop gain, independent of R1 and the closed-loop gain.

• This approach is becoming quite popular recently despite some problems withnoise and input-offset voltages (compared to voltage-mode amplifiers). Examplesare op amps from Comlinear, Harris, and Analog-Devices.

vout ifZL–=

ZL1

sCc 1 Rc⁄+-------------------------------=

LG s( )if

vout----------

νoutif

-----------–ZLR2-------

R0 R2⁄1 sCcR0+--------------------------

1sCcR2-----------------≈= = =

LG s( ) s jωt= 1 ωt⇒ 1R2Cc--------------= =

voutvin

----------1 R1 1 R2⁄+⁄

1 R0 1 R2 sCc+⁄+⁄--------------------------------------------------=

R0 R1 R2+( )R0 R2+( )R1

---------------------------------1

1 sCc R0 R2||( )+

--------------------------------------------=

Acl s( )voutvin

----------R1 R2+

R1--------------------

11 sR2Cc+---------------------------= =

© K.W. Martin, 1997 4 8

References

• J.N. Babanezhad and R. Gregorian, “A programmable gain/loss circuit,” IEEEJournal of Solid-State Circuits, vol. 22, No 6, pp. 1082-1090, Dec. 1987.

• J.N. Babanezhad, “A rail-to-rail CMOS opamp,” IEEE Journal of Solid-StateCircuits, vol. 23, No. 6, pp. 1414-1417, Dec. 1988.

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