INTEGRATED ANALOG ELECTRONICS

DESIGN OF TWO-STAGE OPAMP

PROJECT REPORT

GÜLÇİN KÖSE

152123

Opamp is a high-gain dc coupled differential amplifier. It is generally used for negative

feedback to obtain precise closed-loop transfer function. Some of the requirements of

opamp are large gain, differential inputs, frequency characteristics that permit stable

operation when negative feedback is applied (GBW , phase margin), high input and low

output impedance, high speed, low noise, high output swing etc. In this Project two-stage

differential amplifier is used to obtain the required performance parameters. 0.35µm CMOS

technology and +/- 1.65V powe supplies are used.

In the circuit topology, that is chosen for project, there are three subcircuits. These are input

differential amplifier stage, output common-source amplifier, biasing circuit and

compensation resistance with Miller capacitor in series. Below it is mentioned about these

subsections briefly.

Two stage opamp used in the Project

First Stage

The differential gain stage is made up of transistors from M1 to M4. M1 and M2 are NMOS

input transistors. G1 and G2 are the inverting and non-inverting input terminals respectively.

Applied differential signal from these inputs will be amplified but common-mode signal will

be rejected. M3 and M4 are PMOS transistors, they are used as active load. By this way, it is

obtained beter common-mode signal rejection. The main aim in this stage is to obtain

relatively high gain according to second stage.

Second Stage

Second gain stage is a common-source amplifier with the transistors M5 and M8. M5 takes

the output of the first-stage as an input signal and amplifies it. M8 is an active device that is

used as load resistance of M5. This stage provides additional gain but the main purpose of

using is providing high output swing.

Biasing

The transistors M6, M7 and M8 and the current source Ibias create biasing fort he amplifier.

The transistor M6 supplies voltage for M7 and M8 by the help of Ibias.

Design Procedure

According to design procedure, design starts with evaluating the noise voltage. The input

noise voltage is given by the equation below, it neglects the flickr noise:

For minimizing the noise voltage is chosen as < . Then the equation

reduces to :

Boltzman constant

input noise voltage

is the operation temperature

The minimum value for is:

For obtaining high gain it is choosed as . (The gain of the differential

amplifier depends on )

Now, the maximum value of compensation capacitor can be determined according to the

following equation:

MHz

This is the maximum value of for stabil operational amplifier and closed-loop response.

This value helps to determine the maximum values of drain current with contribution of

slew rate.

Slew rate of the differential amplifier stage is:

Since is effects the power dissipation of the amplifier and first-stage gain, lower drain

current is beter choice. To obtain low power consumption is chosen as which is

lower than the maximum value .

Then according to , compensation capacitor calculated again.

Slew rate of second-stage is given as:

Internal and external slew-rate values are taken equal for proper operation.

Now it can be determined the aspect ratio of , that is ,

is the minimum value, after first simulation is chosen for getting

and like in hand-calculations.

The next step is determining tranconductance of , , this is given by

According to design requirements phase margin should be at least , so it is taken as

.

Now, is known, so it can be determined aspect ratio of , , with the following

equation

=

This value is minimum values of , and it is not enough for to be operate in saturation

region. By using HSpice, after tuning it is determined as .

Once is known, compensation capacitor can be calculated as:

And the seperation factor , , between the second pole and the gain-badwidth product is

To reduce the systematic ofset and improve CMRR, between the transistor , and

there should be accurate matching. To obtain this, drain-source voltages of these transistors

are taken equal.

From this relation,

We know that

and

It is seen that and are current mirror pairs. This design procedure give

us to choose bias current and aspect ratio of , freely. So they are chosen as

and . By using current-mirror property, aspect ratio of and are

determined easily.

It is known that

With the same property

At this point we have to control that the design paramaters satisfy output swing and input

common mode range.

Positive output swing is given as:

Negative output swing is:

Positive input common mode range of the amplifier is:

Negative input common mode range of the amplifier is:

After first determination physical values of the amplificator are:

Parameter Values Unit 10

8.3 8.3/1

0.89 1.78/2

13.7 13.7/1

1 2/2

3 6/2

23 46/2

3

2.29

Simulations

DC Differential Voltage Gain

To determine DC differential voltage gain, a differential input signal is taken as input from

positive and negative input terminals. DC sweep analysis and DC small-signal analysis are

made to obtain the result. HSpice command for DC analysis is:

*DC analysis

.OP

.DC Vid -2.5 2.5 0.05

.TF V(12) Vid

.PROBE

Node 12 is output node of amplifier.

According to simulation result, differential mode DC gain is

**** small-signal transfer characteristics

v(12)/vid = 9.637e+03

input resistance at vid = 1.000e+20

output resistance at v(12) = 8.851e+04

If it is calculated in dB

Output voltage versus differential input voltage

Common Mode Rejection Ratio

To determine CMRR, only common mode input is applied to amplifier and its DC analysis is

done. According to this simulation common mode gain is obtained and by using the previous

simulation, differential gain, CMRR is calculated. For common mode dc analysis,

*DC analysis

.OP

.DC Vic -2.5 2.5 0.05

.TF V(12) Vic

.PROBE

Simulation result of common mode dc analysis:

**** small-signal transfer characteristics

v(12)/vic = 3.060e-01

input resistance at vic = 1.000e+20

output resistance at v(12) = 8.851e+04

Common-mode rejection ratio in dB is:

Frequency analysis

To see the frequency response of amplifier, ac differential input is applied and ac sweep analysis is done. Unity gain bandwidth and phase margin of amplifier are verified with ac analysis.

* AC analysis section****************************************************

.OP

.AC DEC 10 0.1 10000MEG

**measure*************************************************************

.meas ac 'unitgainfreq' when vdb(12)=0

.measure ac 'unitphase' find vp(12) when vdb(12)=0

.measure ac 'phasemargin' param='180-abs(unitphase)'

.measure ac 'gain(db)' max vdb(12)

.measure ac 'gain(mag)' max vm(12)

The simulation result is:

****** ac analysis

unitgainfreq= 5.1066E+06

unitphase= -1.4724E+02

phasemargin= 3.2761E+01

gain(db)= 7.9679E+01 at= 2.5119E-01

from= 1.0000E-01 to= 1.0000E+10

gain(mag)= 9.6376E+03 at= 2.5119E-01

from= 1.0000E-01 to= 1.0000E+10

According to simulation results

Bode amplitude and phase plots

After this first design simulation results, it is seen that phase margin must be improved. For this aim, optimized design procedure will be done for the amplifier.

Slew Rate

To calculate slew rate of opamp unity-gain feedback configuration is used.

A pulse signal is applied from the positive input terminal of opamp as an input signal. In the output graph, slope of rising edge of output signal gives positive slew rate and similarly slope of falling edge gives negative slew rate. Transient analysis is done to see time response of amplifier.

*transient analysis

.TRAN 5ns 2us

.probe tran v(2)

.PROBE tran V(12)

.save all

From the simulation result:

The negative and positive slew-rates must be improved to achieve design goals. After optimization they will be beter.

Input Offset Voltage

Determination of dc input ofset voltage is done by using unity gain feedback configuration. A dc input voltage is given from positive input terminal of opamp. Output voltage is equal to sum of input reference voltage and ofset voltage. 0.5V dc voltage is used as reference voltage.

Offset voltage determination circuit

The simulation results as:

node =voltage node =voltage node =voltage

+0:1 = 4.999e-01 0:2 = 5.000e-01 0:3 =-4.782e-01

+0:4 = 1.875e-02 0:5 = 3.764e-03 0:6 = 1.650e+00

+0:7 =-1.650e+00 0:8 =-7.466e-01 0:11 = 3.764e-03

+0:12 = 4.999e-01

Common-Mode Range

To determine input common mode range and output swing, unity gain feedback configuration is used. From positive input terminal of opamp dc input signal is applied and dc sweep analysis is done.

From the graph

Output Swing

For measuring output swing an inverting amplificator configuration is used. We want to be sure that output voltage clipping is due to output swing not from input common mode range.

Opamp configuration to measure OS

After DC sweep analysis, OS swing is obtained as:

Noise Analysis

For noise analysis, ac input is applied and swept. The noise voltage of output node with taking input node as reference node is seen like below:

*Noise analysis

.AC DEC 10 0.1 10000MEG

.NOISE V(12) Vid 10

The simulation result:

frequency = 1.000e+06 hz

**** total output noise voltage = 1.290e-14 sq v/hz

= 1.136e-07 v/rt hz

frequency = 1.000e+07 hz

**** total output noise voltage = 1.357e-16 sq v/hz

= 1.165e-08 v/rt hz

Optimization Procedure

By compensation techniques of the right half-plane zero, it is possible to obtain beter frequency response. While other electrical paramaters remain same, gain-bandwidth product and phase margin are optimized.

According to nulling resistor technique, compensation capacitor and resistor are recalculated.

To calculate , simulation results are used.

And the compensation resistor is:

After simulation with these values, it is obtained that:

****** ac analysis ******

unitgainfreq= 2.4585E+07

unitphase= -1.2045E+02

phasemargin= 5.9549E+01

gain(db)= 7.9679E+01 at= 6.3096E-01

from= 1.0000E-01 to= 1.0000E+10

gain(mag)= 9.6376E+03 at= 6.3096E-01

from= 1.0000E-01 to= 1.0000E+10

The slew-rate analysis result after compensation

Power consumption

According to simulation results power consumption of the opamps is:

total voltage source power dissipation= 8.959e-04 watts

total current source power dissipation=-2.397e-05 watts

Main electrical parameters of the opamp is:

parameters target simulated

Figure of Merit

Compensation with current buffer

In this method, a current buffer is used to prevent feedforward path that is created by Miller capacitor. The current buffer is placed between output node of first stage amplifier and output of opamp instead of nulling resistor.

It is asumed that transconductance of this new mosfet is:

And the new coupling capacitor is:

Where and

Current source is chosen as , and now aspect ratio of can be determined

The frequency analysis result of current buffer compensation is:

*ac analysis of amplifier

****** ac analysis

unitgainfreq= 3.1237E+07

unitphase= -1.3519E+02

phasemargin= 4.4809E+01

gain(db)= 7.9679E+01 at= 3.9811E-01

from= 1.0000E-01 to= 1.0000E+10

gain(mag)= 9.6376E+03 at= 3.9811E-01

from= 1.0000E-01 to= 1.0000E+10

Unity gain freqeuncy and phase margin are:

Voltage buffer compensation

Like current buffer compensation, also voltage buffer can be placed between the nodes

output of first stage and output of opamp.

Coupling capacitor in this case is:

Transconductance of this mosfet is:

Current source is chosen as , now aspect ratio can be determined.

According to these values, frequency analysis simulation result of opamp is:

*ac analysis of amplifier

****** ac analysis

unitgainfreq= 1.3736E+07

unitphase= -1.3515E+02

phasemargin= 4.4850E+01

gain(db)= 7.9679E+01 at= 1.9953E+00

from= 1.0000E-01 to= 1.0000E+10

gain(mag)= 9.6376E+03 at= 1.9953E+00

from= 1.0000E-01 to= 1.0000E+10

Compensation method comparison according to simulation results:

Resistance

Current Buffer

Voltage Buffer

References

1)B. Razavi, “Design of Analog Cmos Integrated Circuit”

2) G. Cappuccino , F. Amoroso, “Lecture notes of Analog Integrated Circuits”

3)G. Palmisano, G. Palumbo and S.Pennisi, “Design Procedure for CMOS Transconductance Operational Amplifiers: A Tutorial”

4)P.E. Allen, “Lecture 240, Simulation and Measurement of Opamps”

5)H. Li,” Characterization of Two Stage Opamp”

6)J. Mahattanakul, “Design Procedure for Two-Stage CMOS Operational Amplifiers Employing Current Buffer”

7)P. Kakoty, “Design of a High Frequency Low Voltage CMOS Operational Amplifier”