Microelectronic Engineering 67–68 (2003) 769–774www.elsevier.com/ locate/mee

N ovel technologies for the realisation of GaAs pHEMTs with120 nm self-aligned and nanoimprinted T-gates

*D. Moran , E. Boyd, H. McLelland, K. Elgaid. Y. Chen, D.S. Macintyre,S. Thoms, C.R. Stanley, I.G. Thayne

Ultrafast Systems Group, Nanoelectronics Research Centre, Department of Electronics and Electrical Engineering,The University of Glasgow, Glasgow G12 8QQ, UK

Received 19 September 2002; received in revised form 2 December 2002; accepted 14 January 2003

Abstract

To address the major issues of increasing device frequency performance and reducing fabrication costs of 100nm scale gate length III–V HEMT devices, two novel technologies developed for GaAs pHEMT are reported,namely: (i) A low resistance, non-annealed Ohmic contact technology based on a thin metallisation and highlydoped In GaAs/GaAs cap layer which is compatible with a self-aligned gate process. (ii) A succinic acid0.2

based gate recess etch which selectively etches the In GaAs/GaAs cap required for the non-annealed ohmic0.2

contact technology, stopping on a 5-nm Al GaAs etch stop layer. Incorporating both of these processes,0.3

self-aligned T-gate and nanoimprinted T-gate devices have been realised. Completed self-aligned T-gate GaAspHEMT devices of 120 nm gate length exhibited anf and f of 135 and 180 GHz, respectively, whileT max

nanoimprint 120 nm GaAs pHEMT devices demonstrated excellent DC characteristics, including a transconduct-ance of 450 mS/mm. 2003 Elsevier Science B.V. All rights reserved.

Keywords: GaAs pHEMT; Nanoimprint; Ohmic contact; Self-aligned; Succinic acid

1 . Introduction

It is well recognised that for a scaled HEMT structure, the frequency performance of the device willincrease roughly as the inverse of the gate length [1], and has led to extensive research into short gatelength (sub 100 nm) HEMT devices, in pursuit of higher frequency responses [2]. Realistically asdevice dimensions are reduced, parasitic resistances associated with the channel out with the gateregion, i.e., access regions between the source and gate, and drain and gate, have a more detrimental

*Corresponding author.E-mail address: dmoran@elec.gla.ac.uk(D. Moran).

0167-9317/03/$ – see front matter 2003 Elsevier Science B.V. All rights reserved.doi:10.1016/S0167-9317(03)00137-0

770 D. Moran et al. / Microelectronic Engineering 67–68 (2003) 769–774

effect at shorter gate lengths [3]. By ignoring these effects, the full potential of the short gate lengthdevice can not be realised. These parasitics can be minimised by using a self-aligned gate process,where the gate is defined before the ohmic contact, thereby reducing the separation of the ohmiccontacts. This restricts the thermal budget of the total process flow however, as annealing/alloying theohmic contacts at high temperatures will degrade the Schottky gate contact.

In addition to increasing device performance, the expense of running electron beam lithographytools to define ultra-short gate lengths becomes significant. A less costly alternative technique knownas nanoimprinting has been developed [4]. Due to this process requiring the surface being patterned tobe planar, the gate levelmust be defined before the ohmic contacts and hence this places the samerestrictions as the self-aligned process.

With the above in mind, two novel technologies for GaAs pHEMT have been developed. The firstinvolves a low resistance, non-annealed/non-alloyed thin ohmic contact metallisation onto a highlydoped In GaAs cap. The second utilises a selective succinic acid based recess etch to remove the0.2

In GaAs cap and to stop on an Al GaAs etch stop layer.0.2 0.3

The non-annealed ohmic contact technology provides a solution to minimising the thermal budgetof the process while the succinic acid recess etch follows as a method of selectively removing theIn GaAs/GaAs cap.0.2

2 . Material

The GaAs pHEMT material structure used to realise the reported technologies is presented in Fig.1.

The structure incorporates 15 nm In GaAs and 15 nm GaAs layers forming the cap, followed by0.2

an Al GaAs etch stop/Schottky layer. A barrier layer comprising of Al GaAs and GaAs layers0.3 0.3

with selected delta doping, plus an Al GaAs spacer layer separate the cap and In GaAs channel.0.3 0.2

Fig. 1. GaAs pHEMT material structure.

D. Moran et al. / Microelectronic Engineering 67–68 (2003) 769–774 771

Fig. 2. T-gate resist profile with optimised recess etch.

3 . Device fabrication

120 nm gate length self-aligned T-gate GaAs pHEMT devices were fabricated as follows:A H O /NH /H O based wet etch was used for mesa isolation. This was followed by 120 nm2 2 3 2

T-gate definition using a Leica EBPG5-HR 100 electron beam lithography tool operating at 50 keV,with a tri-layer PMMA/P(MMA/MAA) resist stack. The selective succinic acid based recess etch wasused to remove the In GaAs/GaAs cap to create an optimum recess, (Fig. 2). The Ti:Pd:Au gate0.2

was then metallised onto the Al GaAs etch stop/Schottky layer. Non-annealed Ni:Ge:Au ohmic0.3

contacts of 100 nm height were subsequently self-aligned to the gate, (Fig. 3). These yielded a contactresistance of 0.12 Ohm.mm by the standard TLM method [5]. Finally coplanar waveguide bondpadswere defined to allow on-wafer DC and RF characterisation.

The process flow for the nanoimprinted devices was similar except that the mesa isolation level wasperformed after the standard source-drain ohmic contact definition.

Full details of the nanoimprint technology are given elsewhere [4].

4 . Device results

Completed self-aligned gate devices were characterised at DC using an Agilent 4155 semiconductorparameter analyser and at RF from extracteds-parameters taken using an Anritsu 360B networkanalyser. At DC the devices exhibited a peak transconductance of 350 mS/mm, with a maximum

772 D. Moran et al. / Microelectronic Engineering 67–68 (2003) 769–774

Fig. 3. Self-aligned T-gate with Ohmic metallisation.

saturation current of 150 mA/mm. Drain current pinch off was observed at a gate voltage of2 1.0 V,(Fig. 4).

Figures of 135 and 180 GHz forf and f were extracted from H21 and MAG taken fromT max

Fig. 4. Output characteristics from 23 50 mm wide self-aligned device.

D. Moran et al. / Microelectronic Engineering 67–68 (2003) 769–774 773

Fig. 5. H21 and MAG for 23100 mm self-aligned device giving anf of 135 andf of 180 GHz.T max

measureds-parameters, (Fig. 5). These can be compared with previous standard 120 nm gate pHEMTdevices fabricated on similar material at Glasgow University which yielded anf of 125 GHz and anT

f of 180 GHz. The increase inf demonstrates the benefit of the self-aligned process over themax T

standard non-self-aligned method. The maximum frequency,f remains similar for the twomax

processes.Completed non-self-aligned nanoimprint devices with 1.5mm standard source-drain separation

were measured using the same test rig as the e-beam written self-aligned gate devices. The imprinteddevices demonstrated excellent DC characteristics including a peak transconductance of 450 mS/mm(Fig. 6a,b). The variation in DC performance between the self-aligned and nanoimprinted devices may

Fig. 6. (a) I (V , V ) plot of 120 nm nanoimprinted T-gate GaAs pHEMT. (b)g (V ) and I (V ) plot of 120 nmds ds gs m gs ds gs

nanoimprinted T-gate GaAs pHEMT.

774 D. Moran et al. / Microelectronic Engineering 67–68 (2003) 769–774

be due to the properties of the etched surface in the gate recess region as there are differences in thepre-etch treatments between the two process flows. This variation is subject to an ongoinginvestigation, however, the important fact remains that the processes reported in this paper haveproven themselves in producing first-pass, functional devices.

High frequency characterisation of the nanoimprint devices is currently in progress and will bereported at a later date.

5 . Summary

By developing a thin non-annealed/non-alloyed ohmic contact technology in conjunction with anovel succinic acid based recess etch, self-aligned gate GaAs pHEMT devices of 120 nm gate lengthhave been realized. In addition, this technology has allowed the fabrication of 120 nm gatenanoimprint devices on similar material. Device results indicate an increase in high frequencyperformance of the self-aligned devices over their non-self-aligned counterparts, demonstrating theadvantage of reducing device parasitics through a self-aligned approach. This technology will befurther investigated by incorporating it into an InP based HEMT process flow, in conjunction with ashorter gate length technology to truly reap the benefits of the self-aligned system.

Completed nanoimprint devices have exhibited excellent DC characteristics, demonstrating thepotential of using a nanoimprint gate level as an alternative to electron beam lithography, reducing thecosts of short gate length device fabrication.

A cknowledgements

Thanks go to the various members of the Ultrafast Systems Group and Nanoelectronics researchcentre who contributed to this research.

R eferences

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