NextPowerS3 Technology 2. Features and benefits N · PDF fileL F P A K 3 3 PSMN010-30MLD...

LFPAK
33 PSMN010-30MLDN-channel 30 V, 10 m logic level MOSFET in LFPAK33 usingNextPowerS3 Technology19 October 2015 Product data sheet
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1. General descriptionLogic level gate drive N-channel enhancement mode MOSFET in LFPAK33 package.NextPowerS3 portfolio utilising NXPs unique SchottkyPlus technology delivershigh efficiency, low spiking performance usually associated with MOSFETs with anintegrated Schottky or Schottky-like diode but without problematic high leakage current.NextPowerS3 is particularly suited to high efficiency applications at high switchingfrequencies.
2. Features and benefits Ultra low QG, QGD and QOSS for high system efficiency, especially at higher switching
frequencies Superfast switching with soft-recovery; s-factor > 1 Low spiking and ringing for low EMI designs Unique SchottkyPlus technology; Schottky-like performance with < 1 A leakage at
25 C Optimised for 4.5 V gate drive Low parasitic inductance and resistance High reliability clip bonded and solder die attach Mini Power SO8 package; no glue,
no wire bonds, qualified to 175 C Exposed leads for optimal visual solder inspection
3. Applications On-board DC-to-DC solutions for server and telecommunications Secondary-side synchronous rectification in telecommunication applications Voltage regulator modules (VRM) Point-of-Load (POL) modules Power delivery for V-core, ASIC, DDR, GPU, VGA and system components Brushed and brushless motor control
4. Quick reference dataTable 1. Quick reference dataSymbol Parameter Conditions Min Typ Max Unit
VDS drain-source voltage 25 C Tj 175 C - - 30 V
ID drain current Tmb = 25 C; VGS = 10 V; Fig. 2 - - 45 A
Ptot total power dissipation Tmb = 25 C; Fig. 1 - - 38 W
http://www.nxp.com/pip/PSMN010-30MLD

NXP Semiconductors PSMN010-30MLDN-channel 30 V, 10 m logic level MOSFET in LFPAK33 using
NextPowerS3 Technology
PSMN010-30MLD All information provided in this document is subject to legal disclaimers. NXP Semiconductors N.V. 2015. All rights reserved
Product data sheet 19 October 2015 2 / 13
Symbol Parameter Conditions Min Typ Max Unit
Tj junction temperature -55 - 175 C
Static characteristics
VGS = 4.5 V; ID = 10 A; Tj = 25 C;Fig. 10
- 11.4 14.1 mRDSon drain-source on-stateresistance
VGS = 10 V; ID = 10 A; Tj = 25 C;Fig. 10
- 8.6 10.5 m
Dynamic characteristics
QGD gate-drain charge VGS = 4.5 V; ID = 10 A; VDS = 15 V;Fig. 12; Fig. 13
- 1.3 - nC
QG(tot) total gate charge VGS = 4.5 V; ID = 10 A; VDS = 15 V;Fig. 12; Fig. 13
- 4.1 - nC
Source-drain diode
S softness factor IS = 10 A; VGS = 0 V; dIS/dt = -100 A/s;VDS = 15 V; Fig. 16
- 1.4 -
5. Pinning informationTable 2. Pinning informationPin Symbol Description Simplified outline Graphic symbol
1 S source
2 S source
3 S source
4 G gate
mb D mounting base; connected todrain
1 432
LFPAK33 (SOT1210)
S
D
G
mbb076
6. Ordering informationTable 3. Ordering information
PackageType number
Name Description Version
PSMN010-30MLD LFPAK33 Plastic single ended surface mounted package(LFPAK33); 8 leads
SOT1210
7. MarkingTable 4. Marking codesType number Marking code
PSMN010-30MLD 10D30L

8. Limiting valuesTable 5. Limiting valuesIn accordance with the Absolute Maximum Rating System (IEC 60134).Symbol Parameter Conditions Min Max Unit
VDS drain-source voltage 25 C Tj 175 C - 30 V
VDGR drain-gate voltage 25 C Tj 175 C; RGS = 20 k - 30 V
VGS gate-source voltage -20 20 V
Ptot total power dissipation Tmb = 25 C; Fig. 1 - 38 W
VGS = 10 V; Tmb = 25 C; Fig. 2 - 45 AID drain current
VGS = 10 V; Tmb = 100 C; Fig. 2 - 31.5 A
IDM peak drain current pulsed; tp 10 s; Tmb = 25 C; Fig. 3 - 178 A
Tstg storage temperature -55 175 C
Tj junction temperature -55 175 C
Tsld(M) peak soldering temperature - 260 C
VESD electrostatic discharge voltage HBM 200 - V
Source-drain diode
IS source current Tmb = 25 C - 31 A
ISM peak source current pulsed; tp 10 s; Tmb = 25 C - 178 A
Avalanche ruggedness
EDS(AL)S non-repetitive drain-sourceavalanche energy
VGS = 10 V; Tj(init) = 25 C; ID = 10 A;Vsup 30 V; RGS = 50 ; unclamped;tp = 123 s
[1] - 24 mJ
[1] Protected by 100% test

Tmb (C)0 20015050 100
03aa16
40
80
120
Pder(%)
0
Fig. 1. Normalized total power dissipation as afunction of mounting base temperature
aaa-008469
0 25 50 75 100 125 150 175 2000
10
20
30
40
50
Tmb (C)
IDID(A)(A)
Fig. 2. Continuous drain current as a function ofmounting base temperature
aaa-009523
10-1 1 10 10210-1
1
10
102
103
VDS (V)
IDID(A)(A)
DCDC
100 ms100 ms10 ms10 ms1 ms1 ms
100 us100 us
tp = 10 ustp = 10 us
Limit RDSon = VDS / IDLimit RDSon = VDS / ID
Fig. 3. Safe operating area; continuous and peak drain currents as a function of drain-source voltage
9. Thermal characteristicsTable 6. Thermal characteristicsSymbol Parameter Conditions Min Typ Max Unit
Rth(j-mb) thermal resistancefrom junction tomounting base
Fig. 4 - 3.8 3.99 K/W

Fig. 5 - 57 - K/WRth(j-a) thermal resistancefrom junction toambient
Fig. 6 - 178 - K/W
003aaj399
single shot
0.2
0.1
0.05
10-2
10-1
1
10
10-5 10-4 10-3 10-2 10-1 1tp (s)
Zth(j-mb)(K/W)
= 0.5
0.02
10-6
tpT
P
t
tpT
=
Fig. 4. Transient thermal impedance from junction to mounting base as a function of pulse duration
aaa-008476
Fig. 5. PCB layout for thermal resistance junction toambient 1" square pad; FR4 Board; 2oz copper
aaa-008477
Fig. 6. PCB layout for thermal resistance junction toambient minimum footprint; FR4 Board; 2ozcopper
10. CharacteristicsTable 7. CharacteristicsSymbol Parameter Conditions Min Typ Max Unit
Static characteristics
ID = 250 A; VGS = 0 V; Tj = 25 C 30 - - VV(BR)DSS drain-sourcebreakdown voltage ID = 250 A; VGS = 0 V; Tj = -55 C 27 - - V
VGS(th) gate-source thresholdvoltage
ID = 1 mA; VDS = VGS; Tj = 25 C 1.2 1.7 2.2 V

VGS(th)/T gate-source thresholdvoltage variation withtemperature
25 C Tj 150 C - -3.7 - mV/K
VDS = 24 V; VGS = 0 V; Tj = 25 C - - 1 AIDSS drain leakage current
VDS = 24 V; VGS = 0 V; Tj = 125 C - 0.23 - A
VGS = 16 V; VDS = 0 V; Tj = 25 C - - 100 nAIGSS gate leakage current
VGS = -16 V; VDS = 0 V; Tj = 25 C - - 100 nA
VGS = 4.5 V; ID = 10 A; Tj = 25 C;Fig. 10
- 11.4 14.1 m
VGS = 4.5 V; ID = 10 A; Tj = 150 C;Fig. 11; Fig. 10
- - 23.3 m
VGS = 10 V; ID = 10 A; Tj = 25 C;Fig. 10
- 8.6 10.5 m
RDSon drain-source on-stateresistance
VGS = 10 V; ID = 10 A; Tj = 150 C;Fig. 11; Fig. 10
- - 17.3 m
RG gate resistance f = 1 MHz - 0.53 -
Dynamic characteristics
ID = 10 A; VDS = 15 V; VGS = 10 V;Fig. 12; Fig. 13
- 8.5 - nC
ID = 10 A; VDS = 15 V; VGS = 4.5 V;Fig. 12; Fig. 13
- 4.1 - nC
QG(tot) total gate charge
ID = 0 A; VDS = 0 V; VGS = 10 V - 7.5 - nC
QGS gate-source charge - 1.51 - nC
QGS(th) pre-threshold gate-source charge
- 0.86 - nC
QGS(th-pl) post-threshold gate-source charge
- 0.65 - nC
QGD gate-drain charge
ID = 10 A; VDS = 15 V; VGS = 4.5 V;Fig. 12; Fig. 13
- 1.3 - nC
VGS(pl) gate-source plateauvoltage
ID = 10 A; VDS = 15 V; Fig. 12; Fig. 13 - 2.9 - V
Ciss input capacitance - 478 - pF
Coss output capacitance - 4.61 - pF
Crss reverse transfercapacitance
VDS = 15 V; VGS = 0 V; f = 1 MHz;Tj = 25 C; Fig. 14
- 39 - pF
td(on) turn-on delay time - 6.4 - ns
tr rise time - 8.7 - ns
td(off) turn-off delay time - 7.2 - ns
tf fall time
VDS = 15 V; RL = 1.5 ; VGS = 4.5 V;RG(ext) = 5
- 4.8 - ns

PSMN010-30MLD All information provided in this document is subject to legal disclaimers. NXP Semiconduct

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