New plasma processes for improved dimensional control and...

New plasma processes for improved dimensional control and LWR for a 28nm gate patterning

Onintza Ros a, Erwine Pargon b, Sebatien Barnola c, Pascal Gouraud a, Marc Fouchier b

a STMicroelectronics, 850 rue Jean Monnet, 38926 Crolles Cedex, France

b LTM, UMR 5129, Université Grenoble Alpes ; CNRS,

c CEA-Leti Minatec, 17 rue des Martyrs, F-38054 Grenoble Cedex.17 rue des Martyrs, 38054 Grenoble Cedex9, France

PESM 2014

Issue description 2

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Local pattern distortion is observedafter gate patterning.

.

Planar deprocessing afterfull etch

Planar deprocessing afterfull etch

DesignDesignLocal OVL non-alignment of 11nm!

L1L2

L1>L2

PESM 2014

Gate Etch Process Partitioning3

PESM 2014 [email protected]

The cure step has been identified as a root cause for Gat e Shifting

POLY

Oxide HM

SoC

SiARC

PR

POLY

Oxide HM

SoC

SiARC

PR

POLY

Oxide HM

SoC

SiARC

PR

POLY

Oxide HM

SoC

POLY

Oxide HM

SoC

SoC

POLY POLYOxide

a) b) c) d) e) f) g)

Litho HBr Cure Trim SiARC Open SoC Open HM Open Full Etch

Cure HBrCure HBr

4Pattern shifting

New challenge � Pattern shifting

[email protected]

PR after lithography (50nm left)

PR after HBr cure (45nm left)

SEM Xsection (by LAM research)

Cure step leads to polymerdegradation and leads to an overall

resist flowing.

The resist reflow during HBr cure isresponsible of gate shifting.

LithographyLithography

PESM 2014

Pattern TransferSiARC etch without Cure

Cure step removal allows to maintain respectable Gate sh ifting but increases LWR

A compromise have to be found to control both Gate shif ting and LWR.

We will focus over SiARC etching process and subsequent pattern transfer steps

5

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With HBr CureWith HBr Cure Without HBr CureWithout HBr Cure

Low LWR~3.5nmHigh Gate Shift~4,5nm

High LWR~11,8nmLow Gate shift ~0,5nm

Pitch 1

Pitch 2

Pictures after SiARC open

PESM 2014

Metrology issue 6


0

2

4

6

8

10

Pitch 1 Pitch 2 Pitch 3 Pitch 4

Pitch (nm) Pitch

Shift (nm)

Pitc

h sh

ift (

nm)

Pitch 4 remains stable after etch while Pitch 2 is incre ased. Pitch 2 shift is a signature of pattern shifting from initial design.

pitch1

pitch2

pitch3

pitch4

pitch1

pitch2

pitch3

pitch4

a) b) c)

LithographyLithography Full EtchFull EtchDesignDesign

Pitch = CD+Space

Two methods for LWR 7


CD-SEMCD-SEM Tilted AFMTilted AFM

14µm

45°

� Top view observations

� LWR and LER

� Allows spectral analysis

Xi

LWR = 3 x stdev(CD)LWR = 3 x stdev(CD)

Line

y1

n

iyi

LER = 3 x stdev(y)LER = 3 x stdev(y)

� Only for LER

� Half profile scanning

� Estimation of LER all along the pattern height

Comparison of SiARC plasma etching processes 8


CD = 44,8nm PR Th = 78nm CD = 44,8nm

PR Th = 78nm

Lithography

CD = 43nmPR Th = 99nm


CF4 condition SF6 condition

CD = 47nm PR Th = 40nm


CD = 44,8nm PR Th = 78nm



CF4 conditionCF4 condition SF6 conditionSF6 condition


PR SiARC

0.20.40.60.81.01.21.41.61.82.0

1.2

1.8

1.1

ER

(nm

/s)

CF4 SF6

0.6

SiARC ER is higher in CF4 due O depletion by Carbon

C1s O1s Si2p F1s05

10152025303540455055

At %

Ref CF4 SF6

XPS results over SiARC

80 70 60 50 40 30 20

0.3

0.4

0.5

0.6

0.7

0.8

F/C

Angle

CF4 SF6

A R XPS over Photoresist

A C-rich surface layer in CF4 decreasesPR ER and increases LWR.

F-rich surface layer in SF6 increases PR ER and trims PR smoothing the surface.

Surface Bulk

POR CF4 SF60

2

4

6

8

10

12

14

4.8nm

11.8nm

LWR

(nm

)

LWR after SiARC open

3.5nm

Pattern TransferSiARC etch without Cure

New process in SF6 was proved to improve Gate Shifting an d LWR

9

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PORPOR CF4 conditionCF4 condition SF6 conditionSF6 condition

Pitch 1

Pitch 2

Pictures after SiARC open

PESM 2014

POR CF4 SF60123456789

10

0.5nm1.3nm

Gat

e S

hifti

ng (

nm)

GS in SiARC

6.5nm

Study of Roughness over Photoresist 10



LER PR 4.5nm 15.2nm 2.7nm

LER SiARC - 10.9nm 2.8nm

In CF4 photoresist LWR is degraded during process and partially transfered into SiARC.

In SF6, F rich surface layer will trim the photoresist and smooth it during transfer.

Resulting LER is better in SF6 plasmas

LER ~3.7nm

CF4 conditionCF4 condition

LER ~12.5nm

SF6 conditionSF6 condition

LER ~3.7nm

CD-SEM Measures

0 5 10 15 20 25 30 35 40 450

20

40

60

80

100

120

140

Hei

ght (

nm)

LER (nm)

Reference

SiARC

PR

0 5 10 15 20 25 30 35 40 450

20

40

60

80

100

120

140

Hei

ght (

nm)

LER (nm)

Reference

CF4

SiARC

PR

0 5 10 15 20 25 30 35 40 450

20

40

60

80

100

120

140

Hei

ght (

nm)

LER (nm)

Reference

CF4

SF6

SiARC

PR

POR

CF4 SF6

0

1

2

3

4

5

6

7

8

3.9nm

5.1nm

6.3nm

LWR

(nm

)

LWR in Silicon

Roughness transfer into Silicon 11

1

10

100

1E-3 0.01 0.1

1

10

PS

D (

nm)

Lithography SiARC Silicon

Spectral analysis after pattern transfer

PS

D (

nm)

Wavenumber (Kn, nm -1)

Lithography SiARC Silicon

CF4

SF6

In CF4 all roughness frequencies are increased but during pattern transfer just low frequencies are transferred, lead ing to high LWR.

Spectral analysis of LWR in SF6 does not show rough ness improvements since lithography value is underestima ted. Despite subsequent gate etch steps degrade LWR.

After transfer to Silicon, SF6 plasma is the best o ption for LWR and GS decrease

POR

CF4 SF6

0123456789

10

0.5nm1.3nm

G

ate

Shi

fting

(nm

)

GS in Silicon

6.5nm


How to improve LWR? 12


LWR = 4.9nm

TrimTrim

LWR = 3.7nm

HBr CureHBr Cure

LWR = 4.1nm

GS 1.0nm 6.0nm 1.4nm

LER 4.4nm 3.0nm 2.2nm

Photoresist trim has been identified as a good option to limit LWR without Gate Shifting.

Litho Trim

Measures over Photoresist


Trim steps to correct LWR 13



LWR = 4.9nm

Trim – SF 6Trim – SF 6

LWR = 4.0nm

LWR measures taken over SiARC show a big roughness improvement with Trim step addition.

Measures after transfer to Silicon prove that Gate shifting will not be degraded during gate etch but LWR can be degrade d due to

subsequent etch steps.

Std Process SF6 Trim-SF60

1

2

3

4

5

6

4.5nm5nm

LWR

(nm

)

LWR measure over Silicon

4nm

Std Process SF6 Trim SF60

2

4

6

8

10

1nm0.5nm

Gat

e S

hift

(nm

)

Gate Shifting measured over Silicon

6.6nm

85%

SF6SF6

LWR = 4.8nm

Measures over SiARC

Conclusion 14



� Cure steps improve LWR but distort gate patterns.

� Cure step removal requires new plasma processing for gate patterning.

�A new SiARC etching process in SF6 has been compared to the standard process in CF4

�SiARC etching in CF4 leads to C-rich hard surficiallayers that increase LWR

�SiARC etching in SF6 leads to F-rich reactive layers triming photoresist and resulting in lower LWR.

� AFM gate profile analysis shows that LER is lower i n SiARC than in Photoresist.

�Spectral analysis of LWR transfer for these two pla smas shows a degradation of LWR during gate etch processing.

�Addition of Trim steps has been proved to reduce initial LWR

� New process Trim-SF6 allows GateShiftingimprovement of a 85%

Std Process SF6 Trim SF60

2

4

6

8

10

1nm0.5nm

Gat

e S

hift

(nm

)

Gate Shifting measured over Silicon

6.6nm

85%

Thank you for your attention

How to solve it? 16

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Gate shifting has an impact on the

electrical performance of the device.

LITHOLITHO CURECURE Trim PR+SiARCTrim PR+SiARC

The cure step is mandatory to ensure minimized gate LWR but it is the

main contributor to pattern shifting.

SiARC woCURE, wo TRIM

SiARC woCURE, wo TRIM

New strategies have to be implemented to fulfill the requirements of the 20nm

technological node in terms of LWR and gate shifting:

1. Optimization of the hard mask opening steps (Si ARC etching and trim, SOC

and TEOS etching)

2. Optimization of the cure step

PESM 2014

Study of Roughness over Photoresist 17


CF4 conditionCF4 condition

SF6 conditionSF6 condition


0102030405060708090

100110120130

0 5 10 15 20 25 30 35 40 45

SF6 CF4 Reference

LER (nm)

Hei

ght (

nm)

SiARC

PR

LER PR 4.5nm 15.2nm 2.7nm

LER SiARC - 10.9nm 2.8nm

In CF4 initial PR roughness is partially transferred into SiARC sidewalls.

In SF6, initial PR roughness is smoothed during SiARC opening.

Resulting LER is better in SF6 plasmas

Comparison of SiARC plasma etchingprocesses

18



CD = 44,8nm PR Th = 78nm


A C-rich hard surface layer is deposed in CF4 plasmas thatprevents photoresist etching and increases LWR.

In SF6 plasmas a F-rich surface layer increases photo resistetch rate and LWR is not impacted.

SiARC ER is higher in CF4 due to a higher C and F conte nt that will increase Oxygen depletion and Si Etch



2530354045

80 70 60 50 40 30 20

0.30.40.50.60.7

At (

%)

F1s CF4 F1s SF6

AR XPS Measures over photoresist

F/C

Angle

CF4 SF6

SF6 70V CF4 600V0.00.40.81.21.62.0

Etc

h R

ate

(nm

/s)

ERPR ERSiARC

XPS & ER Measures over SiARC

C1s O1s F1s0

10203040

At %

CF4 SF6

New plasma processes for improved dimensional control and...

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