ECE 353Introduction to Microprocessor Systems

Michael J. Schulte

Week 8

Topics80C188 system designPeripheral Control Block (PCB)Characteristics of ROM and RAM ICsOrganization and operation of typical static RAM, EPROM and flash memory devicesMemory subsystem designAddress decoder implementation80C188EB Chip-Select Unit (CSU)

80C188EB System DesignMinimum-component system PSD9XXF

Single and multi-board systems Custom single board system COTS Single Board Computer Custom multi-board system Multi-board standard bus system SoC

Peripheral Control Block (PCB)

Configuration, control and operation of the 80C188EB’s integrated peripherals Diagram

128 contiguous word registers All PCB transfers are 16-bits over F-bus External bus cycles are still run At reset, PCB base address = FF00h in

I/O

pcb.incRelocating the PCB RELREG

Memory SubsystemsROM Masked OTP PROM EPROM EEPROM Flash

RAM SRAM DRAM Pseudo-SRAM Flash – non volatile RAM

Memory OrganizationLogical organization Organization as seen looking at the

device from the outside Linear array of registers (memory

locations)

Physical organization Different physical organizations can be

used to implement the same logical organization

Physical organization affects performance and cost

SRAM InterfacesRAM with 3 control inputs /CS, /OE, /WE Read Write

RAM with 2 control inputs /CS, /WE (or R/W)

/CS

/WE

/OE

internal write signal

internal read signal

/CS

/WEinternal write signal

internal read signal

SRAM OrganizationLogical Organization Typically 1, 4 , 8 or 16 bit widths

Physical Organization Rectangular bit array Two-level decoding (row and column) Characteristic delays and timing requirements are

specified in memory devices datasheet (Example)

NV-SRAM Uses an alternate power source to maintain SRAM

when system power is off Requires logic to switch power sources and

prevent spurious writes during power-up/power-down

EPROMElectrically programmable, non-volatileRequires UV light to erase Quartz window in package

Floating polysilicon gate avalanche injection MOS transistor (FAMOS) Operation

Programmer loads device out-of-circuitOTP EPROMs eliminate quartz windowEEPROMs are electrically erasable Byte-erasable / writeable Low-density

JEDEC Packages

Flash MemoryActually Flash EEPROM, commonly just called flash memoryCharacteristics Technologies Endurance Blocking, programming and erasing

Applications ROM replacement GP NV-RAM Solid-state disk (flash-disk) Example

Memory Subsystem Design

Memory banks Increasing memory width Increasing memory depth Increasing memory width and depth

Address decoding Exhaustive (full) vs. partial decoding Granularity Boundaries

If an address is a 2n boundary, then what is the result of (address AND (2n-1))?

Memory Subsystems Review

What is the purpose of an address decoder circuit, and where does its output usually get connected?What is exhaustive decoding, and what effects does it have?What is partial decoding, and what effects does it have?

80C186EB Memory Subsystem

Organization Logical Physical

Word operations Aligned words Unaligned words

Byte operations 80C186EB control signals

Byte-wide peripherals

Memory ArchitecturesWide (n-byte) buses Addressing effects Byte transfer support

Data lanes Control signals

Bus resizing Static Configurable Dynamic

80C188EB Chip Select Unit (CSU)

10 programmable chip selects /UCS, /LCS /GCS0 - /GCS7

Configuration Active address range Memory or I/O space Wait states Enable / disable Use or ignore READY

Programming Chip-Select Start Register Chip-Select Stop Register

External Address DecodersSSI/MSI Decoders Discrete gates 1-of-n Decoders

74xx138 Partial decoding issues

PLD Decoders PLAs PALs

PALCE22V10

PCB

pcb.inc;***********************************************;** I80C188 **;** **;** Peripheral Control Block **;** Include File for **;** I/O Mapping **;** **;***********************************************

PCBB EQU 0FF00H ; PCB Base Address

;Register Address

INTRVEC EQU PCBB + 0020H ; Interrupt Vector RegisterINTRMSK EQU PCBB + 0028H ; Interrupt Mask RegisterPRIRMSK EQU PCBB + 002AH ; Priority Mask RegisterINSERV EQU PCBB + 002CH ; In-Service Register

RELREG

Chip-Select Start Reg

Chip-Select Stop Register-Part 1

Chip-Select Stop Register -Part 2

Memory Organization

Physical Organization

JEDEC

Flash Blocks

Flash Memory Application:Disk-on-Key

Up to 1GB nonvolatile storageNo battery or power supply

Specifications:Size: 85x28x15mm (LxWxH) Weight: 17g Data retention up to 10 years Power consumption:

Write 36.0mA, Read 33.0mA Erase cycles: 1,000,000 times Read speed > 750KB / sec. Write speed >450 / sec. Shock resistance: 1000 G (maximum)

PALCE22V10 Organization

PALCE22V10 Macrocell

RAM Read – 3 control signals

/CS

Dx

Ax

/OE

/WE

RAM Write – 3 control signals

/CS

Dx

Ax

/OE

/WE

Cypress PSoC

Increasing Memory Depth

CE

A0

A15 D7

D0

CE

A0

A14 D7

D0

CE

A0

A14 D7

D0

Extending Depth

Increasing Memory Width

CE

A0

A15 D7

D0

CE

A0

A15 D3

D0

CE

A0

A15 D3

D0

Extending Width

Increasing Memory Depth & Width

CE

A0

A15 D7

D0CE

A0

A14 D3D0

Extending Width and Depth

CE

A0

A14 D3D0

CE

A0

A14 D3D0

CE

A0

A14 D3D0