Week #2 Slides
description
Transcript of Week #2 Slides
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Week #2 Slides
Diving Into Spartan 3
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Agenda
• Recap• 15 Years of Evolution to Virtex• Four generations of Spartan• Project discussion• Questions
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LogicCell
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XC2000 Family – The Original
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First Configuration Logic Block
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First IO Cell
Note: havingAll user pins beI/O was a bigDEAL!!!
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XC3000 Family CLB Second Generation
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XC3000 FabricArray
Little black dotsAre PIPs
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XC3000 IO Cell
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XC4000 CLB Third Generation
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XC4000 IO Cell
Note
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VIRTEX The Fourth Generation
NOTE: VIRTEXEquated withHaving hardFixed blocksEmbedded inThe fabric
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Virtex SLICE
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… which brings us to Spartan 3
(uh, we did skip a bunch of stuff, but the progression for our needs works out . . .)
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Spartan 3
• Xilinx and the industry track silicon technology– XC2000 @1.5 micron– XC3000 @ 1 micron– XC4000 @ 0.8 to 0.35 micron– Virtex @ 0.25 micron, V-II @ 0.18-0.13 micron– Spartan 3 & Virtex 4 @ 90 nm – Virtex 5 @65 nm– Spartan 6 @ 45 nm– Virtex 6 @ 40 nm– Etc.
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Spartan Philosophy
• Offer a more cost effective solution for higher volume markets
• Need to reduce costs to do that– Trim features– Reduce test cost– Sacrifice speed over die size– Cheaper packages– Etc.
• Spartan is the overall result
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Spartan 3 Family Chart
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General Architecture
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Package Migration
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IO Banks
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Spartan 3 IO Cell
Note
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Heterogeneous Logic Cells
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Stuff in Black & GreyCommon toSliceL & sliceM
Blue stuff inSliceM only
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Some Block RAM Detail
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Multiplier Blocks
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Digital Clock Managers
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Clock netsDo heavy lifting
Different netsIn each family
FYI
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Hierarchical Routing
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Adjust the mix: Spartan 3E
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Reduce the Banks: more IO pins available
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Spartan 3E IO Cell
Note
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Adjustable Input Delay
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Adjust the mix: Spartan 3A
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Stack the Flash: Spartan 3AN
A Single Chip Solution
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Internal SPI Flash
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Add a block: Spartan 3A DSP
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Spartan 3A DSP Architecture
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DSP48 with a Pre-Adder
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The Project . . .
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Projects Depend
• On your knowledge• Your skill level• Your confidence• Your interest• Uh . . .I don’t know any of the above points about
you!• Only YOU know where you are at on this continuum• My goal is to get you to where you can design on
Xilinx FPGAs, which has a LOT to do with the S/W!
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Some Ideas
• Interfaces – MIX & MATCH things
• Buses and memories• Peripherals & memories• Buses & peripherals• Processors & the above
• Systems– Build single function
items– Combine two or more
items– Invent something new
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Ahh, the Good Old Days . . .
Basic idea: Create useful, correct standard functions then . . . HOOK ‘EM UP!
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More
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More
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Still More
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Yet Another
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My All Time Favorite Part
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Ahh, the Good NEW Days!
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Graphic stolen from Doug Smith’sBook cover . . .I’m looking for theCD that was optional
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StolenFromSmith
Like OldTTL Manual
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Uh, also stolen fromSmith . . .
NOTE!!!!
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Modern Way to Design. . .
Follow the LIGHT!!
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TheLight
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Possible Projects
• The Light bulb area has design templates for both VHDL and Verilog
• I’d like to expand the documentation on them along the lines of the TTL Catalog, and Doug Smith’s book.
• Need volunteers to take say 10 of the templates, instantiate into a design, capture the schematic (automatic) and simulate to verify the operation
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Possible Project Continued
• The Deliverable would be a WORD file organized to have: – Template code– Graphic– Simulation
• I can make these available to the rest of the class and to future classes
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Another Idea
• The Digilent NEXYS2 board is supported by VHDL solutions, which are available.
• Most of them are 1-2 sheets of code.• I’d like to get them in Verilog, with simulations
and compiled onto Xilinx Spartan 3 parts.• Take a look at the “pmod” code chunks
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One more thing to remember
• Your project should you obtain your goal for this class– May be to log some credit to a credential– May be to learn something about FPGAs– May be to design something you always wanted
an excuse to design– I won’t know what that is . . .– It’s up to you