Modeling of High-k / Metal Gate MOSFET Devices with PSP

Modeling of High-k / Metal Gate MOSFET Devices with PSP1�st International MOS-AK Meeting

Joachim AssenmacherIFAG COM BTS T DIF CM

Jae-Eun Park, IBM

19-Dec-08 Copyright © Infineon Technologies 2006. All rights reserved.

Outline

! Modeling of High-k / Metal Gate Devices

□ Modeling of an Effective Dielectric Constant

□ Modeling of Gate Capacitances and Gate Currents

□ Fitting Examples

! PSP103 Non-Uniform Doping (NUD) Model Evaluation

□ Improved Body Effect Modeling for Short Channel Devices

□ Improved Mobility Modeling for Non-Silicon Channel Devices

! Miscellaneous

□ Vt-shift for CV

! PSP103 Runtime Performance

! Conclusion


Modeling of an Effective Dielectric Constant for High-k / Metal Gate Devices

! In PSP102.2 new parameters EPSOXin local EPSOXO in global model have been introduced, in order to decouple gate current and capacitance fittings

8.10228.05.42.2

5.4223

111

_

____

__

_

_

=⋅+⋅

⋅⋅=

⋅+⋅⋅⋅=

+=

+=

nmnmnm

TOXTOXTOX

TOXTOXTOX

CCC

total

total

total

effhighk

highkSiONphySiONhighkphy

SiONhighkeffphyeffhighk

SiON

SiONphy

highk

highkphy

effhighk

effphy

SiONhighkeff

ε

εεεεε

εεε

Poly

HfO2

TiN

MOS gate stack

SiO2

MG

22A

8Aεr = 22

εr = 4.5

effective physical oxide thickness ≈30A → TOXO (PSP global parameter)

EPSOXO(PSP global parameter)


Modeling of Gate Capacitances and Gate Currents for High-k / Metal Gate Devices

! Effective physical oxide thickness and effective dielectric constant adjustment for SiO2/HfO2 gate stack (extracted TOXO and EPSOXO are consistent to process)

! Tunneling barrier height adjustment for gate currents needed from 3.1eV for the

conventional Si-SiO2 interface to 1.5eV for Si-SiO2/HfO2 interface (→ CHIBO)

PSP102.2 parameter:

TOXO = 3nm EPSOXO = 10.8

CHIBO = 1.5 (tunneling barrier height)

NMOS CGGNMOS IGATE

Note: The TOXO parameter in PSP is defined as the physical oxide thickness (QM-effect andpoly depletion are separate).


Example PSP High-k / Metal Gate Modeling: Id-Vg and Id-Vd (global fitting)

gm @ Vds= 50mV transconductance

IdVd @ Vbs= 0Voutput characteristic

! 32nm NFET short channel characteristics - accurate DC model build (PSP102.2)

IdVg @ Vds=50mVtransfer characteristic

IdVg @ Vdd=1.2Vtransfer characteristic


Example PSP High-k / Metal Gate Modeling: Analog Figures (global fitting)

gmsat/Idsat

K�:=gmsat2 /(2⋅Idsat)

analog gain factor

gm3=d3Id/dVgs3

(3rd-order derivative) harmonic distortion

Va=-(Id/gds-Vd)early voltage

! 32nm NFET short channel characteristics - accurate analog model build (PSP102.2)

moderate inversion


Improved Body Effect Modeling for Short Devices Vt-roll-up/off (global fitting)

! PSP102: Severe issues for modeling of threshold voltage back bias dependence for short channel devices

! PSP103: Significant improvement for higher body biases with non-uniform doping (NUD) model

PSP102

32nm NMOS: Vtlin vs. L 32nm NMOS: Vtlin vs. L

PSP103


Improved Body Effect Modeling (cont�d) Short channel transfer characteristics (local fitting)

! PSP102: Body effect modeling issue also observed on local level. Thus, it seems to be a fundamental issue and not just a problem with the (NEFF) global scaling rule

! PSP103: Overall improvement for higher body biases with usage of the NUD-model

PSP102

32nm NMOS: narrow short Id-Vg

zoom in

32nm NMOS: narrow short Id-Vg

zoom in

PSP103


Improved Body Effect Modeling (cont�d) NUD-model of PSP103: Modified Model Equations

DVSBNUDODVSBNUD

VSBNUDOVSBNUD

GFACNUDLWGFACNUDWGFACNUDLGFACNUDOGFACNUDPGFACNUDLEX

=

=

⋅⋅⋅+⋅+

⋅+=

EE

ENEN

E

EN

E

EN

LWLW

WW

LL

PSP103 NUD-model: new global geometrical scaling rules

scattering due to measurement issues

GFACNUD L-scaling (body factor change due to NUD-effect)

NUD-model range parameters


SiSiGe-channel

SiO2

HfO2

TiN

Φm,eff ~4.5eV

High-k/Metal Gate: p-FET

( )OX

OB

gm

OX

Osm

OX

Oms C

QqE

CQ

CQVFB −

++−Φ=−Φ−Φ=−Φ= ψχ

2

! Flat-band voltage definition for metal gate and non-silicon channel:Work-function difference Φms due to metal gate is covered in PSP, even with a non-silicon semiconductor Φs, due to the flat-band voltage parameters VFB and VFBO.

Modeling of High-k / Metal Gate Devices with Non-Silicon Channels


Mobility Modeling Challenge for SiGe-Devices:PSP102 actual situation: Id-Vg and gm (local fitting)



32nm PMOS data: wide long device

! Additional mobility scattering/ interaction mechanism for SiGe-channel devices have been observed (especially for long / intermediate channel length devices).

32nm PMOS data: wide short device

32nm PMOS data: intermediate device



Improved Mobility Modeling for SiGe-Devices: PSP102-IFX Proposal: Id-Vg and gm (local fitting)




! Proposal for PSP102: Modification of mobility modeling have been implemented, in order to model MOSFETs with a composition of Si- and Ge-channel materials.





( )

( ) ( ) ρ

µµ

η

η

µ

µ

++⋅+⋅+

⋅=

⋅

⋅=

⋅+⋅=

2

2

0

1

PMOSfor 3/1

NMOSfor 2/1

imbm

bmTHEMUeff

x

imbmeffeff

qqqCSEMUE

MUO

qqEE

FETA

FETA

Improved Mobility Modeling (cont�d) Proposal for PSP102: Modified Model Equations

Proposal: Introduction of geometrical dependence for effective vertical field

FETA L-scalingPSP mobility expression: MUE and THEMU account for the mobility degradation by effective vertical field Eeff

⋅⋅⋅+⋅

⋅+⋅

⋅+=

EE

ENEN

E

EN

E

EN

LWLW

WW

LL FETALWFETAWFETALFETAOFETA

FETALEXP

11

Proposal: New FETA global geometrical scaling rule

FETA has no geometrical scaling in actual PSP102 versions (Note: ηµ has an influence on quantum mechanical correction as well)


Improved Mobility Modeling for SiGe-Devices: PSP103: Id-Vg and gm (local fitting)




! PSP103: Usage of the NUD-model will also increase the fitting accuracy for non-silicon (SiGe) channel devices, especially for higher reverse back-biases.





Miscellaneous: Vt-shift for CVExample: Long channel device with strong halo implants

! PSP102: Severe issues for modeling of long channel gate capacitances with heavy pockets, due to different Vt for IV and CV

! PSP103: Significant improvement for the gate capacitances (with SWDELVTAC=1)

PSP102

32nm NMOS: large area Cgg

PSP103


PSP103 Runtime PerformanceSummary

! With PSP102.3 and PSP103.0 we get about 15% longer (TR) simulation times than with PSP102.2, due to asymmetric junction formulations (even if it is switched off; i.e. SWJUNASYM=0). A speed improved Verilog-A code already exists for SiMKit.

! With PSP103.0 we expect for most of our circuits about 60% longer (TR) simulation times if either the NUD-model and/or Vt-shift for CV option will be used (i.e. SWNUD=1, SWDELVTAC=1), due to extra SP-calculations for CV.

1

1,1

1,2

1,3

1,4

1,5

1,6

PSP102.3: SWJUNASYM=0PSP103.0: SWNUD=0, SWDELVTAC=0PSP103.0: SWNUD=1, SWDELVTAC=1

Simulation speed ratio of PSP102.3 and PSP103.0 versus PSP102.2


Runtime Performance Evaluation of PSP103with IFX/QI in-house simulator (direct C-code implementation)

! Table 1: Transient analysis results - Test circuits with MOSFET �normalized load CPU times per iterations� for PSP102.3_SWJUNASYM=0/PSP102.2

1204

20679

# MOSFETs

1.1315.43 ms 17.41 ms

PSP102.2 PSP102.3

IFX 65nm Flash A/D Converter

1.1515.22 ms 17.55 ms

PSP102.2 PSP102.3

IFX 65nm ring oscillator INV

Ratio PSP102.3/PSP102.2

CPU time MOS load per iterat.

ModelCircuit

! Table 2: Transient analysis results - Test circuits with MOSFET �normalized load CPU times per iterations� for PSP103.0_SWNUD=1_SWDELVTAC=1_(SWJUNASYM=0)/PSP102.2

1204

20679

# MOSFETs

1.6015.43 ms 24.76 ms

PSP102.2 PSP103.0

IFX 65nm Flash A/D Converter

1.6215.22 ms 24.70 ms

PSP102.2 PSP103.0

IFX 65nm ring oscillator INV

Ratio PSP103.0/PSP102.2

CPU time MOS load per iterat.

ModelCircuit


Conclusion

! PSP is very suitable for modeling of high-k / metal gate devices (e.g. models gate capacitances and gate currents consistently, etc.).

! PSP provides accurate description of 32/28nm I-V and C-V device characteristics over complete bias, temperature and geometry range (incl. 1�st, 2�rd and 3�rd order derivatives).

! PSP103 non-uniform doping (NUD) model can describe reduced body-effect at high reverse back-biases, with significant improvement compared to PSP102.

□ Moreover, the NUD-model can improve modeling of non-silicon (SiGe) channel devices. → However, further evaluation required. Maybe an enhancement of the mobility model will

be needed as well, like the proposed introduction of length dependence for the effective vertical field (including adjustment of band-gap Eg and intrinsic carrier density ni).

□ But, with the current PSP103.0 NUD-model we expect for most of our circuits a significant additional runtime of about 50% (due to extra SP-calculation for CV). → This simulation runtime issue has been already addressed to the CMC and a more speed

efficient implementation of the NUD-effect has been requested to the PSP-team.

! PSP103 Vt-shift for CV option leads to the same slow down in runtime performance as the NUD-model (due to extra SP-calculation for CV), but we could recommend to our designers it�s usage just for critical CV applications, like large MOSCAP, etc.

Modeling of High-k / Metal Gate MOSFET Devices with PSP

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