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CHAPTER 5

NANOSCALE GATE ENGINEERING DOUBLE GATE MOSFET USING HIGH-K DIELECTRICS

5.1. INTRODUCTION

DG MOSFETs are used for CMOS applications beyond the 45 nm of the

ITRS roadmap 2010, due to their excellent scalability and better control. These

multi-gate devices, which can be fabricated as DG MOSFET, are potentially

scalable according to ITRS because of their ultra-thin bodies which suppress short

channel effects owing to the simultaneous control of the channel by more than one

gate (ITRS 2010). To overcome short channel effect, Gate Engineering technique is

used. The Dual Material DG MOSFET provides a better scalability option due to its

excellent immunity to SCEs (Frank et al 2001; Colinge 2004).

This chapter deals with the analysis of impact of gate engineering on the

performance of DG MOSFET for system-on-chip applications with high-k

dielectric materials. EOT of gate oxide can be reduced by using high-k dielectric

materials. ZrO2 (Zirconium-di-oxide) has been proposed to be the best alternative

for SiO2 (Silicon-di-oxide). Gate engineering technique used here is Dual Material

Gate technology and the simulations are carried out using Sentaurus simulator. The

parameters such as On current, Off current, Ion/Ioff ratio, DIBL, transconductance,

transconductance generation factor, Output resistance, intrinsic gain and intrinsic

gate capacitances using ZrO2 as gate oxide material in DMDG MOSFET are

estimated and compared with SiO2 as gate oxide dielectric material in same DMDG

MOSFET devices. The suitability of nano scale DMDG MOSFET device for circuit

applications is examined by comparing the performance of inverter for different

high-k dielectric materials. The inverter output shows a significant improvement in

gain for the proposed ZrO2 as gate oxide dielectric material in DMDG MOSFET.

Gate engineering technique such as DMDG MOSFET has two different

materials with different work functions being merged together to form a single gate

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of a SOI MOSFET. In the DMDG MOSFET the gate oxide dielctric material which

is replaced with various high-k material, is proposed in this chapter. In DMDG

MOSFET device, the work function of the gate material is taken as 4.55 eV (M1,

Molybdenum) close to the source is chosen higher than the drain end which is 4.1

eV (M2, Aluminium). As a result, the electric field and electron velocity along the

channel suddenly increases near the interface of the two gate materials which results

in increased gate transport efficiency (Mohan Kumar et al 2010). This shows that

the threshold voltage under gate material M1 is higher than the gate material M2.

When the drain voltage exceeds the drain saturation voltage, the excess voltage is

absorbed by gate material M2 preventing the drain field from penetrating into the

channel (Mohan Kumar et al 2009). Also the channel of the device is very lightly

doped (1015 cm -3). As a result it leads the device into reduction of mobility

degradation. This technique also avoids random microscopic dopant fluctuations

(Chakraborty et al 2007; Yuan et al 2005).

In both logic and memory applications, SiO2 gate dielectric has reached

minimum thickness due to direct tunnelling current and reliability concerns.

Exponentially increasing the Off current while decreasing the gate oxide thickness

is the main driver for the searching of new high-k dielectric materials. So in this

chapter the DMDG MOSFET device performance is analyzed by replacing SiO2

gate oxide dielectric material with nano size ZrO2.

5.2. DUAL MATERIAL DEVICE STRUCTURE AND PARAMETER

SELECTION

The DMDG MOSFET device is designed based on the technology

parameters and the supply voltages according to ITRS 2010 for 45nm gate length

devices (ITRS 2010). The proposed technology nodes with specifications matching

the ITRS requirements are shown in Table 5.1.

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Table 5.1 Proposed technology nodes with specifications matching the ITRS requirements

Gate Length (Lg)nm 65 45 32 22

Fin Width (Wfin) nm 22 15 11 8

Gate Oxide Thickness (Tox) nm 1.2 1.2 1.1 1.1

Spacer Length (Lsp) nm 35 22 16 11

Work Function (eV) 4.4 4.3 4.3 4.2

VDD (V) 1 1 1 1

Fin height (Hfin) nm 60 60 60 60

The schematic cross-sectional view of the DMDG MOSFET is shown in

Figure 5.1. The optimization of DMG technology, the work functions of metals M1

(molybdenum) and M2 (aluminium) are taken as 4.55 eV and 4.1 eV respectively,

with equal lengths of L1 and L2, and a threshold voltage of 0.3 V at a drain voltage

of 0.1 V is obtained (Chaudhry et al 2004). The source and the drain regions are

doped with Phosphorous active with doping concentration of 1x1020 cm-3 to design

DMDG MOSFET. The channel region which has a thickness of 20 nm is lightly

doped with Boron active concentration of 1x1016 cm-3. The device dimensions of the

two dimensional DMDG MOSFET is shown in Table 5.2. The use of poly-Si

electrodes in MOS devices can significantly increase the Capacitance Equivalent

Thickness (CET), resulting in high sheet resistance and cause dopant diffusion

through the high-k gate oxide layer.

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Figure 5.1 Cross-sectional view of the DMDG MOSFET

One viable way to solve these challenges is to use a metal as gate electrode.

Metal gates eliminate poly depletion effects resulting in the reduction of inversion

capacitance. All the simulations are carried out with the help of standard

experimental data used by Esseni et al.

Table 5.2 Device dimensions of DMDG MOSFET

Parameter Dimension

Gate Length 45 nm

Channel thickness 15 nm

Oxide thickness 1.2 nm

Source/Drain Doping 1020/cm3

Channel doping 1015/cm3

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An enhanced slicer is used to observe the doping profile, the electric field

and the carrier velocity along the channel. Simulations are carried out in DMDG

MOSFET replacing gate oxide SiO2 with wide range of possible high-k dielectric

materials like Si3N1 (k~7.5), Al2O3 (k~10), LaAlO3 (k~15), HfO2/ZrO2 (k~25),

La2O3 (k~27), TiO2 (k~40). The operation of the device in sub threshold regime is

the main consideration for the performance analysis for each of these devices. In the

simulation, the density gradient model is used which solves the quantum potential

equations self-consistently with the Poisson and carrier continuity equations. The

quantum potential is introduced to include quantization effects in a classical device

simulation. In the density-gradient transport approximation, the quantum potential

is a function of the carrier densities and their gradients.

5.2.1. Impact of high-k dielectrics on Dual Material DG MOSFETS

This chapter focuses on towards replacing SiO2 dielectric material gate oxide

with various high-k dielectric materials in DMDG MOSFET and analysing their

performance. As the oxide thickness scales below 2 nm, Off currents increase

drastically due to tunnelling, leading to unwieldy power consumption and reduced

device reliability (Despande et al 2001; Mohan Kumar et al 2010). Among the

various requirements of gate dielectric materials, the most important are the good

insulating properties and capacitance performance. Since, the gate dielectric

materials constitute the interlayer in the gate stacks; they should also have the

ability to prevent diffusion of dopants such as boron and phosphorus to avoid few

electrical defects which often compromise the breakdown performance. It must act

as an insulator, by having band offsets with Si of over 1 eV to minimize carrier

injection into its bands (Bouazra et al 2008). Meanwhile, they must have good

thermal stability, high recrystallization temperature, sound interface qualities, and

so on (Robertson 2004; Jung Han Kang et al 2009). The DMDG MOSFET device

using SiO2 dielectric material is replaced with suitable nano sized ZrO2 dielectric

material shows an improvement in the device performance.

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5.3 DMDG MOSFET SIMULATION RESULTS AND DISCUSSION

Based on the above stated requirements and specifications of the high-k

dielectric materials, six high-k materials are chosen for the analysis of DMDG

MOSFET. In each simulation, the physical gate oxide thickness was proportionately

scaled such that the EOT remains the same (Krishna Kumar Bhuwalka et al 2007).

For each simulation the oxide parameter file in the tool is replaced with synthesised

material parameters.

5.3.1. Analysis of parameters of DMDG MOSFET using high-k

dielectrics

Off current is the drain current at a gate to source voltage of 0.15 V and drain

to source voltage of 0.6 V. Saturation current or On current is the drain current at

drain to source voltage of 0.6 V. The gate engineered device shows an increase of

drain current by about 5% in the sub threshold regime using ZrO2 as compared with

SiO2. The reason behind such improvement of the drain current is attributed to the

increased electron velocity at the source end and thus improved carrier transport

efficiency of the device (Mohan Kumar et al 2009). Since this improvement is more

prominent in the sub threshold regime, the devices are also more suitable for low

power subthreshold analog circuits. The Off current and the On current of the

DMDG MOSFET are plotted for replacing various gate oxide material as high-k

dielectric materials and it is shown in Figure 5.2. In DMDG MOSFET the SiO2

based dielectric is found to have the highest Off current and it decreases

exponentially with increase in dielectric constant of different high-k dielectric

materials. Thus the integration of high-k dielectrics in the device reduces the Off

current in the device. On current also decreases exponentially in the DMDG

MOSFET dielectric constant is increased. So DMDG MOSFET with ZrO2 as gate

dielectric is used for low power applications.

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Figure 5.2 Comparison of Off current and On current for DMDG MOSFET with

different high-k dielectric materials

The IOn/IOff ratio is also plotted for different high-k dielectric materials as

shown in Figure 5.3 for DMDG MOSFET.

Figure 5.3 Comparison of On current to Off current ratio and DIBL for DMDG MOSFET with different high-k dielectric materials

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It is seen that the IOn/IOff ratio increases exponentially for different high-k

dielectric material in DMDG MOSFET, which shows the performance

improvement in the devices. It is clear that IOn/IOff ratio is only 1300000 for DMDG

MOSFET with SiO2 where as it is 2800000 for dielectric material ZrO2. The IOn/IOff

ratio increases approximately 73% for ZrO2 as gate oxide material as compared

with SiO2 in DMDG MOSFET. The IOn/IOff ratio current should be always high for

proper switching of the devices. Since the DMDG MOSFET with ZrO2 has a large

IOn/IOff ratio compared SiO2 as gate oxide dielectric material, these devices can be

used for all switching applications in semiconductor cutting edge technology.

For logic applications, DIBL plays an important role as device dimensions

are scaled rigorously. The DIBL co-efficient is computed as,

(5.1)

Where Vt,lin and Vt,sat are the threshold voltages measured at linear and

saturation region for drain voltages of 0.1 V and 1.2 V, respectively. The supply

voltage of 1.2 V is taken from ITRS 2010 for 45 nm gate length for logic

applications. From Figure 5.3 it is observed that DIBL is low for dielectric material

ZrO2 having a value of 1 and maximum for gate dielectric SiO2 with a value of 10.

In DMDG MOSFET the DIBL is exponential decrease of approximately 63% while

replacing the gate oxide dielectric material from SiO2 to ZrO2. The variation of

surface potential along the channel length for DMDG MOSFET for various high-k

dielectric materials is shown in Figure 5.4. Also the position along the channel is

plotted in the X-axis direction and the DMDG MOSFET devices show a step

potential profile at the interface of the two metals along the channel. It is clearly

visible that the DMDG MOSFET device provides a larger increase of potential,

thereby improving DIBL characteristics. The electrostatic surface potential is the

highest for the low dielectric constant value of 3.9 which corresponds to SiO2

material.

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Figure 5.4 Comparison of electrostatic surface potential along the channel in DM

n-channel DG MOSFET with different high-k dielectric materials

The lateral electric field profile at the surface is shown in Figure 5.5 for

different high-k dielectric material in DMDG MOSFET.

Figure 5.5 Comparison of Lateral Electric Field along the channel DM n-channel

DG MOSFET with different high-k dielectric materials

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The step increase of surface potential in the case of the DMDG MOSFET

devices results in an additional electric field peak at the interface which is in

addition to the electric field existing at the drain end. These additional peaks due to

gate engineering techniques reduce the effective field at the drain end, resulting in

smaller DIBL and hot-carrier effects, which are the major problems in the case of

the short-channel devices.

For DMDG MOSFET devices, the electric field discontinuity at the interface

of two gate metals causes channel field flattening, which results in a larger average

velocity when the electrons enter the channel from the source. The electron velocity

profile at the surface is shown in Figure 5.6 for different high-k dielectric materials

used as gate oxide in DMDG MOSFET.

Figure 5.6 Electron velocity variation along the channel thickness in DM n-channel DG MOSFET with different high-k dielectric materials

The electron velocity is low for SiO2 ,which is used as gate oxide dielectric

material in DMDG MOSFET as compared to ZrO2 ,which is used as a dielectric

material in the same device. So the speed of the DMDG MOSFET with nano sized

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ZrO2 as a gate oxide material is increased in the device, it can be used for high

speed applications.

5.3.2 Analysis of Analog parameters in DMDG MOSFET

The variation of different analog device parameters like the transconductance

(gm), transconductance generation factor (gm/Id) and output resistance (Ro) for

DMDG MOSFET with different high-k materials are discussed in this section.

The variation of transconductance with drain current at a drain bias of 1.2 V

for various high-k dielectric materials is shown in Figure 5.7.

Figure 5.7 Comparison of variation of drain current and transconductance in DM

n-channel DG MOSFET with different high-k dielectric materials as a function of

gate to source voltage

The DMDG MOSFET device shows an improvement in drain current and

increase in transconductance with different high-k dielectric material as gate oxide

material. The improvement in peak gm in DMDG MOSFET can be attributed to the

improved charge control by the top and bottom gates in the devices. The DMDG

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MOSFET with ZrO2 as the gate oxide dielectric material has high drain current and

transconductance as compared with other conventional gate oxide material.

Another parameter of interest is the transconductance generation factor

(TGF) or gm/Id ratio. In a MOS transistor, gm/Id is maximum when it is in the weak

inversion regime and degrades severely with increasing drain current in the strong

inversion regime. The variation of the transconductance generation factor with

respect to the gate voltage (Vgs) is shown in Figure 5.8. It is observed that the

DMDG MOSFET with ZrO2 as the gate oxide material offers high transconductance

generation factor at all gate voltage values compared with SiO2 as gate oxide

dielectric material.

Figure 5.8 Comparison of TGF for the DM n-channel DG MOSFET with different

high-k dielectric materials as a function of gate to source voltage

The output resistance, Ro of a MOS transistor is evaluated as

Ro= VA/ID (5.2)

where VA and ID are early voltage and saturated drain current. Gate engineered

device with ZrO2 as gate oxide material offers a higher output resistance. Such an

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improvement is due to the fact that the region of the channel under metal M2

provides a shielding effect such that the channel region under M1 is not affected by

drain to source voltage variations. The output resistance variation of the DMDG

MOSFET device with different high-k dielectric materials is shown in Figure 5.9.

From the Figure, it is clear that DMDG MOSFET with ZrO2 as gate oxide material

has high output resistance of 155 for SiO2 it is 8 The devices with

output resistance are more suitable for building feedback and cascade amplifier

(Mohan Kumar et al 2009). Hence the DMDG MOSFET with ZrO2 gate oxide will

perform better in feedback and cascade amplifier configuration.

The DMDG MOSFET device with an undoped body does not suffer from

any mobility degradation issue, thereby exhibiting an increased gain in both the

weak and strong inversion regimes. The intrinsic gain which is the product of

transconductance and output resistance is also shown in Figure 5.9.

Figure 5.9 Comparison of Intrinsic Gain and Output resistance for

DMDG MOSFET with different high-k dielectric materials

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The SiO2 gate oxide material in DMDG MOSFET has the minimum intrinsic

gain whereas for ZrO2, it is as high as 200, which makes the device useful for

amplifier applications. Since the gain of the device is very high it is best suited for

the implementation of amplifier circuits.

The intrinsic gate capacitances represent an important parameter in the case

of RF applications. The intrinsic gate capacitances in the DMDG MOSFET are gate

to- source (Cgs), gate-to-drain capacitances (Cgd). The total amount of capacitance is

equal to sum of all the intrinsic gate capacitances that is Cgg = Cgd + Cgs. The values

of Cgs, Cgd and Cgg of the DMDG MOSFET for various dielectric materials are

given in Table 5.4. The Cgs, Cgd and Cgg increase as dielectric constant values

increase thereby reducing the Off current and increasing the gate control in the

DMDG MOSFET.

Table 5.4 Comparison of Cgd, Cgs and Cgg of DMDG MOSFET for different gate dielectric materials

Dielectric

Constant

k

Gate to Drain

Capacitance, Cgd

(fF)

Gate to Source

Capacitance, Cgs

(fF)

Total Gate

Capacitance, Cgg,

(fF)

3.9 1 0.53 1.5

7.5 1.5 0.56 2.1

10 1.7 0.58 2.5

15 2.5 0.61 3.1

25 3.7 0.62 4.3

40 5.5 0.64 6

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The electron density at the source end of DMDG MOSFET is considerably

less when compared to the drain end in the case of the DMDG MOSFET devices.

This is due to the fact that the channel at the source side has a higher threshold

voltage due to the higher work function material at the source side of the device.

The larger values of Cgd in the case of the DMDG MOSFET result from capacitance

coupling between drain and gate electrodes.

5.3.3 Circuit applications

The circuit performance using DMDG MOSFET is analyzed by investigating

the gain of a simple CMOS inverting amplifier.

Figure 5.10 Comparison of Voltage transfer characteristics of CMOS

Inverter with DM n-channel DG MOSFET with different high- k materials

The voltage transfer characteristics of the CMOS inverter with DMDG

MOSFET with different high-k dielectric material is shown in Figure 5.10. The gain

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is computed by calculating the slope of the voltage transfer characteristics for

different dielectric materials, and it is summarised in Table 5.5.

Table 5.5 Comparison of voltage gain of DMDG MOSFET CMOS inverter with different high-k dielectric materials

Dielectric

Material

Dielectric

constant

Value (k)

Voltage

Gain

V/v

SiO2 3.9 0.7115

Si3N1 7.5 0.7337

Al2O3 10 0.8111

LaAlO3 15 0.8288

HfO2/ZrO2 25 0.8348

TiO2 40 0.8401

The Inverter circuit using DMDG MOSFET with ZrO2 as the gate oxide

dielectric shows higher gain of 0.8348 as shown in Table 5.5. So integration of

high-k dielectrics improves the performance of the circuit. Since the device shows

superior performance with the integration of high-k gate dielectrics, the device can

be utilised for circuit level implementation of NAND gates for Nano scale

technology.

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5.4 CONCLUSION

In this chapter, the performances of DMDG MOSFETs with different high-k

dielectric materials are clearly analyzed. An attempt has been made to improve the

performance of the inverter circuit by replacing SiO2 with various high-k dielectric

materials in the DMDG MOSFET and performance is observed. However from the

analysis, the gate oxide dielectric material ZrO2 is found to be the best alternative

for SiO2 because TiO2 has a band gap of 3 eV which is not favourable in DMDG

MOSFET. The integration of high-k dielectric material in the DMDG MOSFET

enhances the device performance to a great extend and it makes the device one of

the promising candidates for future semiconductor devices because of increase in

mobility. The proposed DMDG MOSFET with nano sized ZrO2 as gate oxide

dielectric improves the overall performance of the device as well as circuit and they

can be used for low power applications and high frequency applications. An attempt

has been made to improve the device performance using Channel Engineering

Technique in nano scale DG MOSFET which will be discussed in the next chapter.