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Lecture 25: Interconnect Modeling

EECS 312

Reading: 8.3 (text), 4.3.2, 4.4.1-4.4.4 (2nd edition)

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Last Time

• Simultaneous switching noise is a key problem for off-chip drivers– Drive them as slowly as allowed

• General interconnect characteristics– Local wires and global wires– Many metal levels, connect with vias

• Capacitance is the primary parasitic– Area, fringing, interwire components– Interwire dominates today– Both simple and complex models exist to compute

capacitance as a function of wire geometry

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Lecture Overview

• Interconnect resistance

• IR drop/Electromigration

• RC delay models

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Resistance & Sheet Resistance

Resistance seen by current going from left to right is same in each block

W

L

T

R = T W

L

Sheet ResistanceR

R1 R2

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Bulk Resistivity

Aluminum was dominant until ~2000

Copper has gradually taken over in the past 4-5 years

Copper is pretty much as good as it gets

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Interconnect Resistance

Resistance scales poorly – Full scaling calls for reduction in width and thickness by S each generation

R ~ S2 for a fixed line length and material!

Called reverse scaling wires get slower when smaller while devices get faster

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Polycide Gate Mosfet

n+n+

SiO2

PolySilicon

Silicide

p

Silicides: WSi2, TiSi2, PtSi2 and TaSi

Conductivity: 8-10 times better than Poly

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Impact of New Materials

• IBM back-end copper process at left

• Yields 12% improvement over an aluminum process in a PowerPC design

Transistor

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RI Introduced Noise

VDD

X

I

I

R’

R

VDD - V’

V

V

pre

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Power and Ground Distribution

GND

VDD

Logic

GND

VDD

Logic

GND

VDD

(a) Finger-shaped network (b) Network with multiple supply pins

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IR Drop in a High-Speed Design

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Electromigration

• Migration of metal atoms in conductors which pass large DC current densities

• Large current densities lead to fast moving eletrons that can rip metal atoms off their sites

• This leads to open circuits and short circuits between adjacent wires

• MTTF: mean time to failure• How long can we pass a constant current through a wire

before it fails?• Exponentially dependent on temperature and material type

(ex: Al vs. Cu)• Linear to quadratic dependence on current density

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Electromigration Results

Limits DC current densities to ~ 106 A/cm2

In a 1m x 1m wire 10mA

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Evolution of Interconnect Modeling

• Before 1990, wires were thick and wide while devices were big and slow– Large wiring capacitances and device resistances– Wiring resistance was << device resistance– Model wires as capacitances only

• In the 1990s, scaling theory led to smaller and faster devices and smaller, more resistive wires– Reverse Scaling properties of wires!– RC models became necessary

• In the 2000s, frequencies are high enough so that inductance is a major component of total impedance

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Global interconnect delay grows

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Lumped RC model of a wire

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RC Delay

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RC Models

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RC Propagating Wavefront

Step response of a distributed RC wire as a function of location along wire and time

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Delay expressions

238.069.0 LcrLcRt wwwsp We will typically have a load capacitance CL at node Vout

LwwwLwsp LCrLcrCLcRt 69.038.069.0 2

Assumes step input Vin

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Summary/Key Points

• Wire resistivity gets worse as wires get smaller (reverse scaling, different than device delay)

• Power distribution becomes more difficult due to IR drops and higher current densities

• Lumped wire delay overestimates actual delay (distributed) – Because the entire capacitance is NOT charged through

the full wire resistance• Wire RC delay increases quadratically with line

length as both R and C rise linearly– This has implications on how to reduce RC delay

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How to reduce RC delay

• Since RC delay is quadratic with length, reducing length is key

• Note: 22 = 4 and 1+1 = 2 but 12 + 12 = 2

source sink

source

sink

L = 2 units

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Repeaters

Repeater

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Repeaters Impact

Repeaters are simply large inverters inserted along a global interconnect to reduce the RC delay

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The Elmore Delay

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Penfield-Rubinstein-Horowitz

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Capacitive Crosstalk Noise

• Crosstalk noise high-level description

• Simple lumped model, step through it slowly

• Give results

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Cross-sectional view

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High level view of crosstalk noise

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Noise Pulses can be large

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Simple Noise Model (Rubio)

Model derivation: no line resistance considered, Tr is rise time of aggressor signal, R is the effective driver resistance of the victim (good approx, demonstrate using I-V curves)

xvc

cddnoise e

xCC

CVV

1

1

vcv

r

CCR

Tx

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Linear Resistance Assumption

Slope here is fairly constant with Vgs=Vdd (operating point for NMOS holding output to GND)

Inverse of this slope ~ Reff

Replace the victim driver by a linear resistor

Only problem – if noise gets too big, the approximation becomes worse (R grows)

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How to Battle Capacitive Crosstalk

Substrate (GND)

GND

ShieldinglayerVDD

GND

Shieldingwire

• Avoid parallel wires

• Shielding

Unrealistic – need tight packing to reduce chip area, cost