Lecture 2: Scaled CMOS
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1 Nanoelectronics: Scaled CMOS Lecture 2: Scaled CMOS Contents: Benchmarking: R Chau et al IEEE Nanotech 4, 2005, p 153 ”Benchmarking Nanotechnology for ... Advanced CMOS Design: B Doyle et al IEEE Electron Dev . Lett. 24, 2003, p. 263 ”High-performance Fully-Depleted Tri-gate ... Extremely scaled MOSFETs: B Doris et al IEEE IEDM Tech Digest. 2002, p. 267 ”Extreme Scaling with Ultra-Thin ...” High-k dielectrics on Si: P Lee et al Appl. Phys. Lett.. 82, 2003, p 2419 ”Study of interfacial ....”
Transcript of Lecture 2: Scaled CMOS
1 Nanoelectronics: Scaled CMOS
Lecture 2: Scaled CMOS
Contents:
Benchmarking: R Chau et al IEEE Nanotech 4, 2005, p 153 ”Benchmarking Nanotechnology for ...
Advanced CMOS Design: B Doyle et al IEEE Electron Dev. Lett. 24, 2003, p. 263 ”High-performance Fully-Depleted Tri-gate ...
Extremely scaled MOSFETs:
B Doris et al IEEE IEDM Tech Digest. 2002, p. 267 ”Extreme Scaling with Ultra-Thin ...”
High-k dielectrics on Si: P Lee et al Appl. Phys. Lett.. 82, 2003, p 2419 ”Study of interfacial ....”
2 Nanoelectronics: Scaled CMOS
Four key metrics for logics:
Speed
Intrinsic speed (CV/I)
Switching energy
Energy-delay product (CV/I*CV2)
Scalability
Subthreshold slope vs Lg
Off-state leakage
CV/I vs Ion/Ioff
Transistor evolution:
3 Nanoelectronics: Scaled CMOS
|VDS|=VCC
Vg 2/3 above Vt gives Ion
Vg 1/3 below Vt gives Ioff
Calculate/measure the capacitance
Cylindrical devices:
Method for benchmarking
111 QMCOXCTOTALC
)/2ln(/02 RhrOXC
Normalization by width 2R
Typical nanotube characteristics: Definition of data points:
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Nanoelectronics: Scaled CMOS
Gate Delay
PMOS:
NMOS:
III/V NMOS have better performance!
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Energy-delay product
PMOS:
NMOS:
III/V NMOS have better performance!
6 Nanoelectronics: Scaled CMOS
Scalability and leakage
7 Nanoelectronics: Scaled CMOS
Planar single gate
Double-gate
(fin width one third
of gate length)
Tri-gate
(body thickness
about gate length)
Si body of Tri-gate transistor
Advanced Device Architectures:
8 Nanoelectronics: Scaled CMOS
Performance of 60 nm gate length
Ion=1.14 mA/mm
Ioff=70 nA/mm
SS=68 mV/dec
Ion=0.52 mA/mm
Ioff=24 nA/mm
SS=69.5 mV/dec
Comparable to well-optimized
planar devices!
15 Å oxide thickness
DIBL=41 mV/V DIBL=48 mV/V
DIBL=Vg@Vd=1.3V-Vg@Vd=0.05V/(1.3-0.05)
Vg taken at Id=0.1 mA/mm
9 Nanoelectronics: Scaled CMOS
Planar devices on Si SOI substrates
Reduces parasitics and leakage
Wafer thinning to 6±2 nm Si films!!!
But mobility degrades as the film is thinned down
10 Nanoelectronics: Scaled CMOS
Performance of ultra-thin Si channel MOSFETS
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Performance of 26 nm CMOS circuit
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6 nm pFET: It works!
13 Nanoelectronics: Scaled CMOS
Strong process dependence Deposition techniques
PLD
ALD
Sputtering
Physical effects
Amorphous/crystalline
Amount of oxygen, stochiometry
Annealing
Interface reactions
14 Nanoelectronics: Scaled CMOS
Effects of Interface reactions
CV-technique
MOS capacitor
Effects of traps in the film and at
the interfaces
Frequency response gives time scale
Minority carrier in inversion
Used to determined the charge
Split CV
𝜇𝑒𝑓𝑓 =𝐿
𝑊
𝑔𝑑 𝑉𝑔
𝑞𝑁𝑠 𝑉𝑔
𝑞𝑁𝑠 𝑉𝑔 = 𝐶 𝑉𝑔 𝑑𝑉𝑔
𝑉𝑔
−∞
