Lecture 2 - CMOS and Fab

7/30/2019 Lecture 2 - CMOS and Fab

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Lecture 2: CMOS and

Manufacturing Process


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VLSI

{ Integrated circuits: many transistors on one chip.{ Very Large Scale I nt egrat ion (VLSI): very many{ Com plementary Metal Oxide Sem iconductor

z Fast, cheap, low power transistors{

Today: How to build your own simple CMOS chipz CMOS transistorsz Building logic gates from transistorsz Transistor layout and fabrication

{ Rest of the course: How to build a good CMOSchip


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Class


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Silicon Lattice

{

Transistors are built on a siliconsubstrate{ Silicon is a Group IV material{ Forms crystal lattice with bonds tofour neighbors

Si SiSi

Si SiSi

Si SiSi


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Dopants

{ Silicon is a semiconductor{ Pure silicon has no free carriers and

conducts poorly{ Adding dopants increases the conductivity{ Group V: extra electron (n-type){ Group III: missing electron, called hole

(p-type)

As SiSi

Si SiSi

Si SiSi

B SiSi

Si SiSi

Si SiSi

-

+

+

-


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p-n Junctions

{

A junction between p-type and n-type semiconductor forms a diode.{ Current flows only in one direction

p-type n-type

anode cathode


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MOS Structure


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nMOS Transistor

{ Four terminals: gate, source, drain, body{ Gate oxide body stack looks like a capacitor

z Gate and body are conductorsz SiO2 (oxide) is a very good insulatorz Called metal oxide semiconductor (MOS)capacitorz Even though gate is no longer made of metal

n+

p

GateSource Drain

bulk Si

SiO2

Polysilicon

n+


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nMOS Operation

{ Body is commonly tied to ground (0 V){ When the gate is at a low voltage:

z P-type body is at low voltagez Source-body and drain-body diodes are OFFz No current flows, transistor is OFF

n+

p

GateSource Drain

bulk Si

SiO 2

Polysilicon

n+D

0

S


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nMOS Operation Cont.

{ When the gate is at a high voltage:z Positive charge on gate of MOS capacitorz Negative charge attracted to bodyz Inverts a channel under gate to n-typez Now current can flow through n-type siliconfrom source through channel to drain,

transistor is ON

n+

p

GateSource Drain

bulk Si

SiO2

Polysilicon

n+D

1

S


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pMOS Transistor

{ Similar, but doping and voltages reversedz Body tied to high voltage (V DD)z Gate low: transistor ONz Gate high: transistor OFFz Bubble indicates inverted behavior

SiO 2

n

GateSource Drain

bulk Si

Polysilicon

p+ p+


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Power Supply Voltage

{

GND = 0 V{ In 1980s, V DD = 5V{ VDD has decreased in modern

processesz High VDD would damage modern tiny

transistorsz Lower VDD saves power

{ VDD = 3.3, 2.5, 1.8, 1.5, 1.2, 1.0,


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CMOS Fabrication

{

CMOS transistors are fabricated onsilicon wafer{ Lithography process similar to

printing press{ On each step, different materialsare deposited or etched

{ Easiest to understand by viewingboth top and cross-section of waferin a simplified manufacturing

process


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oxidation

opticalmask

processstep

photoresist coatingphotoresistremoval (ashing)

spin, rinse, dryacid etch

photoresist

stepper exposure

development

Typical operations in a singlephotolithographic cycle (from [Fullman]).

Photo-Lithographic Process

http://it.darden.virginia.edu/explore/content/index_frames.htm


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Circuit Under Design & Layout View

V DD V DD

V in V out

M 1

M 2

M 3

M 4

V out 2


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Inverter Cross-section

{ Typically use p-type substrate fornMOS transistors

{ Requires n-well for body of pMOS

transistors

n+

p substrate

p+

n well

A

YGND VDD

n+ p+

SiO 2

n+ diffusion

p+ diffusion

polysilicon

metal1

nMOS transistor pMOS transistor


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Well and Substrate Taps

{ Substrate must be tied to GND and n-well to V DD{ Metal to lightly-doped semiconductor forms poor

connection called Shottky Diode{ Use heavily doped well and substrate contacts /

taps

n+

p substrate

p+

n well

A

YGND VDD

n+p+

substrate tap well tap

n+ p+


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Inverter Mask Set

{ Transistors and wires are defined by masks { Cross-section taken along dashed line

GND V DD

Y

A

substrate tap well tap

nMOS transistor pMOS transistor


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Detailed Mask Views

{ Six masksz n-wellz Polysiliconz n+ diffusionz p+ diffusionz Contactz Metal

Metal

Polysilicon

Contact

n+ Diffusion

p+ Diffusion

n well


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Fabrication Steps{ Start with blank wafer{ Build inverter from the bottom up{ First step will be to form the n-well

z Cover wafer with protective layer of SiO 2 (oxide)z Remove layer where n-well should be builtz Implant or diffuse n dopants into exposed waferz Strip off SiO2

p substrate


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Oxidation

{ Grow SiO2

on top of Si waferz 900 1200 C with H 2O or O2 in

oxidation furnace

p substrate

SiO 2


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Photoresist

{ Spin on photoresistz Photoresist is a light-sensitive organic

polymerz Softens where exposed to light

p substrate

SiO 2

Photoresist


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Lithography

{ Expose photoresist through n-well mask{ Strip off exposed photoresist

p substrate

SiO 2

Photoresist


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Etch

{ Etch oxide with hydrofluoric acid (HF)z Seeps through skin and eats bone; nasty

stuff!!!{ Only attacks oxide where resist has been

exposed

p substrate

SiO 2

Photoresist


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Strip Photoresist

{ Strip off remaining photoresistz Use mixture of acids called piranah etch

{ Necessary so resist doesnt melt in nextstep

p substrate

SiO 2


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n-well{ n-well is formed with diffusion or ion

implantation{ Diffusion

z Place wafer in furnace with arsenic gasz Heat until As atoms diffuse into exposed Si

{

Ion Implantationz Blast wafer with beam of As ionsz Ions blocked by SiO2, only enter exposed Si

n well

SiO 2


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Strip Oxide

{ Strip off the remaining oxide using HF{ Back to bare wafer with n-well{ Subsequent steps involve similar series of

steps

p substraten well


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Polysilicon

{ Deposit very thin layer of gate oxidez < 20 (6-7 atomic layers)

{ Chemical Vapor Deposition (CVD) of silicon layerz Place wafer in furnace with Silane gas (SiH 4)z Forms many small crystals called polysiliconz Heavily doped to be good conductor

Thin gate oxidePolysilicon

p substraten well


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Polysilicon Patterning{ Use same lithography process to pattern

polysilicon

Polysilicon

p substrate

Thin gate oxidePolysilicon

n well


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Self-Aligned Process

{ Use oxide and masking to expose wheren+ dopants should be diffused orimplanted

{ N-diffusion forms nMOS source, drain,

and n-well contact

p substraten well


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N-diffusion{ Pattern oxide and form n+ regions{ Self- aligned pr ocess where gate blocks diffusion{ Polysilicon is better than metal for self-aligned gates

because it doesnt melt during later processing

p substraten well

n+ Diffusion


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N-diffusion cont.

{ Strip off oxide to completepatterning step

n wellp substrate

n+n+ n+


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Contacts

{ Now we need to wire together the devices{ Cover chip with thick field oxide{ Etch oxide where contact cuts are needed

p substrate

Thick field oxide

n well

n+n+ n+p+p+p+

Contact


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Layout


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Layout{ Chips are specified with set of masks{ Minimum dimensions of masks

determine transistor size (and hencespeed, cost, and power)

{ Feature size improves 30% every 3years or so

{ Normalize for feature size whendescribing design rules


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Transistor Layout

1

2

5

3

Transistor


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Design Rules

{

Interface between designer and processengineer{ Guidelines for constructing process masks{ Unit dimension: Minimum line width

z scalable design rules: lambda parameterz absolute dimensions (micron rules)


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CMOS Process Layers

Layer

Polysilicon

Metal1

Metal2

Contact To PolyContact To Diffusion

Via

Well (p,n)

Active Area (n+,p+)

Color Representation

Yellow

Green

Red

Blue

Magenta

BlackBlack

Black

Select (p+,n+) Green


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Layers in 0.25 m CMOS process


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Intra-Layer Design Rules

Metal24

3

10

90Well

Active3

3

Polysilicon2

2

Different PotentialSame Potential

Metal13

3

2

Contactor Via

Select

2

or6

2Hole


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Vias and Contacts

1

2

1

Via

Metal toPoly ContactMetal to

Active Contact

1

2

5

4

3 2

2


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CMOS Inverter Layout

A A

np-substrate Field

Oxidep+n+

In

Out

GND V DD

(a) Layout

(b) Cross-Section along A-A

A A


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Design tools


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Layout Editor


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Design Rule Checker

poly_not_fet to all_diff minimum spacing = 0.14 um.


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Sticks Diagram

1/1

3/1

In Out

V DD

GND

Stick diagram of inverter

Dimensionless layout entities Only topology is important Final layout generated by

compaction program

Lecture 2 - CMOS and Fab

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