Lecture 11 - University of Colorado...

Power Electronics Lab 1

Lecture 11ECEN 4517/5517

Experiment 4 Part 2

Part II—Closed loop with averaged model:

Demonstrate closed-loop system including op amp feedback circuitry. Plot loop gains etc.

Plot open-loop control characteristicsDamp power stage resonancesDesign compensator and feedback circuitryImplement in LTspice and prove that your design works

Part III—Closed-Loop with switched model:Demonstrate working closed-loop system with switching model. Demonstrate start up transient response.


New Schedule

Part First week Second week

Part 1: open-loop system

March 16-20 March 30 – April 3

Report due April 3

Part 2: closed-loop, averaged model

April 6-10 April 13-17

Report due April 17

Part 3: closed-loop, switching model

April 20-24 April 27 – May 1

Report due May 1


Lecture Topics

Averaged modeling of your converter design in LTspiceModels for Part 2

Design of feedback loop circuitry using averaged modelsPlotting control-to-output transfer functionDamping internal resonances of power stagesDesigning compensator based on averaged transfer functionsDesigning feedback circuitry using op ampsPlotting loop gain in LTspice

What is expected for Part 2


Averaged Model of Converter System

Start with your LTspice model from Exp. 4 Part 1 final result (part 5)Switching model that met startup criteriaRefined design with inductor saturation

Convert to averaged modelReplace PWM model with averaged version: output is analog

continuous signal representing duty cycleNo gate driversReplace transistors and diodes with averaged switch model CCM-

DCM1The reason for this:

Can use LTspice small-signal ac modeling capabilities to plot transfer function and loop gain Bode plots

Simulations run much faster


Component Averaged Models

Start with your LTspice model from Exp. 4 Part 1 final result (part 5)Switching model that met startup criteriaRefined design with inductor saturation

Convert to averaged modelReplace PWM model with averaged version: output is analog

continuous signal representing duty cycleNo gate driversReplace transistors and diodes with averaged switch model CCM-

DCM1The reason for this:

Can use LTspice small-signal ac modeling capabilities to plot transfer function and loop gain Bode plots

Simulations run much faster


average4517.lib

PWMavg CCM-DCM1

Parameters:L=valuefs=value

Parameters:Dmax=valueDmin=0.02Voffset=1VM=2.3


Step 2: DC Sweep

Plot converter output voltage V vs. control input voltage vc.dc source start stop increment

Reduce Dmax so that this curve is monotonic


Step 3: Plot Gvd(s)

Connect voltage source (Vcon) to PWM input pin vcSet dc component of Vcon to set converter quiescent operating point: achieve dc output of 200VAdd ac component of amplitude 1 to Vcon: Vcon x y dc value ac 1Perform ac (phasor) analysis:

.ac dec points start stopThen select output node with voltage probe. LTspice plots transfer function magnitude and phase Bode plot

Converter

Outputv

InputVcon


How LTspice Performs AC Analysis

Find Quiescent Operating PointUsually works for open loop simulationsIt often diverges in closed-loop simulations

Perturb and linearize about quiescent operating pointResult is a linearized small-signal model. Simulation becomes linear.LTspice uses phasor analysis to find transfer function magnitude and phaseThis works with nonlinear elements, but requires time-invariant system. No

switching. Averaged models overcome this.Take advantage of LTspice and averaged modeling

Plot small-signal ac transfer function from any node or element to any otherWith averaged models, run times are very short


Step 4: Damp Internal Resonances


Step 4: Damp Internal Resonances

Example of a damped control-to-

output transfer function


Step 5: Design and Implement Compensator and Feedback Circuits

Voltage divider and op-amp compensator circuitsRegulate output at 200 VAchieve adequate phase marginPlot loop gain


Use Op Amp from LTspice Library

A reasonable choice: LT1498• Rail-to-rail input and

output (common mode range extends to power supply limits)

• Gain-bandwidth product: 10 MHz

• Slew rate: 6V/µs

Power this op amp from PWM: Vcc = vref = 5.1 VVoltages at all pins must not exceed op amp power supply voltage

PI compensator example


Feedback Loop Design

All students must design and implement an analog feedback loop that:• Regulates dc output voltage to 200 V ± 5 V• Has crossover frequency no greater than 20% of switching frequency.

Don’t change your switching frequency.• Has phase margin of at least 50˚

ECEN 4517 students:• No limit on minimum crossover frequency• Any compensator approach (PI, PID, etc.) is acceptable

ECEN 5517 students:• Crossover frequency must be greater than 1 kHz• PID compensator required


Plotting Loop Gain in LTspice

+–

H(s)

+– Z2(s)

Block 1 Block 2

0

Tv(s)

Z1(s) Zs(s)

– +

+

vx(s)

–

vref (s)G1(s)ve(s)

ve(s) G2(s)vx(s) = v(s)

–

vy(s)

+

vzi(s)

Measuring loop gain by voltage injection

Connecting a 1 V ac source between compensator output and PWM control input• Loop gain is

T(s) = -vy /vx


Convergence Problems

• In closed-loop simulations, LTspice often encounters convergence problems and cannot find quiescent operating point

• A solution: provide initial conditions for a few key capacitorvoltages and/or inductor currents• Append “IC=value” to element value• Set initial conditions on output capacitor voltage and compensator integrator

capacitor voltage to their correct steady-state values• Setting initial conditions on the above may be sufficient to get the closed-

loop simulation to run


Step 5 Demonstrations

• Plot loop gain and show that your design meets the requirements

• Run a transient simulation to show that the feedback loop regulates the output voltage to the required dc value• It’s OK for this transient simulation to include the initial conditions you used

to solve convergence problems• The object is to find the steady-state output voltage after all transients have

settled


Exp 4 Part 2 Due Date

Upload your Part 2 Report to Canvas by 5:00 pm on Friday April 17

Lecture 11 - University of Colorado...

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