ECEN 4517 1

Lecture 4ECEN 4517/5517

Step-up dc-dc converter with isolation (flyback)

Feedback controller to regulate HVDC

Experiment 3 weeks 2 and 3: interleaved flyback and feedback loop

Parallel two flybacks with phase-shifted gate drive signals

12 VDC HVDC: 120 - 200 VDC

AC load120 Vrms60 Hz

Battery

DC-ACinverter

H-bridge

DC-DCconverter

Isolatedflyback

+–

d(t)

Feedbackcontroller

Vref Digitalcontroller

d(t)

+

vac(t)

–

ECEN 4517 2

Due dates and goals

Right now:Prelab assignment for Exp. 4 Part 1 (one from every student)

Due within five minutes of beginning of lecture

This week in lab (Feb. 3-5):Final reports for Exps. 1 and 2 due

Begin Exp. 3: construct and debug basic flyback power stage

Next week in lab (Feb. 10-13):Get parallel flyback power stages working at 85 W

Begin simulation of ac transfer functions and feedback loop design

ECEN 4517 3

Goals in upcoming weeksExp. 3: Flyback step-up dc-dc converter

Exp. 3 Part 1:Design and fabrication of flyback transformer

Snubber circuitDemonstrate flyback

converter power stage operating open loop

Exp. 3 Part 2:Construct, debug, and demonstrateparalleled flyback converters producing 85 W

Exp. 3 Part 3:Design feedback loopMeasure loop gain, compare with simulation and theoryDemonstrate closed-loop control of converter output voltage

snubber

PWM Compensator +–

Vref

Vbatt

vHVDC

ECEN 4517 4

Layout of power stage

Identify loops having high di/dt (pulsating currents). Since v = L di/di, stray inductance in these loops leads to voltage spikes and ringing on components (usually the MOSFET) that can exceed their peak voltage ratings.

Minimize the inductance of the critical loops: keep area of loop small, use twisted pairs, add bypass capacitors.

ECEN 4517 4

Effect of transformer leakage inductance

+–

LM

+

v

–Vg

Q1

D11:n

C

Transformer model

iig

R

Ll

+ vl –

+

vT(t)

–

• Leakage inductance Ll is caused by imperfect coupling of primary and secondary windings

• Leakage inductance is effectively in series with transistor Q1

• When MOSFET switches off, it interrupts the current in Ll

• Ll induces a voltage spike across Q1

t

Vg + v/n

vT(t)

iRon

DTs

{Voltage spikecaused by

leakageinductance

If the peak magnitude of the voltage spike exceeds the voltage rating of the MOSFET, then the MOSFET will fail.

ECEN 4517 5

Protection of Q1using a voltage-clamp snubber

+–

+

v

–Vg

Q1

D11:n

C

Flyback transformer

ig

R

+

vT(t)

–

CsRs

–

vs

+

Snubber{ • Snubber provides a place for current in leakage inductance to flow after Q1 has turned off

• Peak transistor voltage is clamped to Vg + vs

• vs > V/n

• Energy stored in leakage inductance (plus more) is transferred to capacitor Cs, then dissipated in RsUsually, Cs is large

Decreasing Rs decreases the peak transistor voltage but increases the snubber power loss

See supplementary flyback notes for an example of estimating Cs and Rs

ECEN 4517 6

Overvoltage on output diode

+–

LM

+

v

–Vg

Q1

D11:n

C

Transformer model

iig

R

Ll1

+ vl –

+

vT(t)

–

Ll2Diode turn-off (reverse recovery) transition:

Transformer leakage inductance causes voltage ringing and overshoot on secondary diode

Leakage inductance plus diode output capacitance form resonant circuit:

tArea– Qr

t

t3t1 t2

vB(t)

iL(t)

–V2

0

0

+–

LiL(t)

vL(t) +

–

+ –

Silicondiodevi(t) CvB(t)

iB(t) diode capacitance

leakage inductance

secondary induced voltage

ECEN 4517 7

Diode snubber

+–

LM

+

v

–Vg

Q1

D1

1:n

C

Transformer model

iig

R

Ll1

+ vl1 –

+

vT(t)

–

Ll2

Diode snubber

– vl2 +

Damp the ringing with R-C snubber network

Snubber capacitance similar in value to diode capacitance

Snubber resistance similar in value to resonant circuit characteristic impedance

More capacitance and/or smaller resistance lower peak voltage, larger snubber loss

ECEN 4517 8

Limits on maximum output powerWeek 1 circuit

• Wiring inductance causes ac

component of iflyback to flow through capacitor C, while the dc component

flows from the battery

• Capacitor rms current must not exceed the rating of 4.42 A

• Decreasing converter efficiency caused by snubber and other losses, along with capacitor current rating, limit the maximum output power

• How much output power can you produce?

ECEN 4517 9

Increasing the output powerWeek 2 circuit

Interleaving of parallel-connected flyback

converters: • AC components of phase-shifted

input current waveforms partially cancel out

• Less rms capacitor current per unit

of output power

Produce 85 W

output power by end of week 2

ECEN 4517 10

Exp. 3 Part 3Regulation of output voltage via feedback

snubber

PWM Compensator +–

Vref

Vbatt

vHVDC

• Model and measure

control-to-output transfer function Gvd(s)

• Design and build feedback loop

• Measure loop gain to

verify phase margin and crossover frequency

• Demonstrate closed-loop regulation of vHVDC

ECEN 4517 11

Negative feedback:a switching regulator system

+–

+

v

–

vg

Switching converterPowerinput

Load–+

Compensator

vref

Referenceinput

HvPulse-widthmodulator

vc

Transistorgate driver

Gc(s)

H(s)

ve

Errorsignal

Sensorgain

iload

ECEN 4517 12

Transfer functions ofsome basic CCM converters

Table 8.2. Salient features of the small-signal CCM transfer functions of some basic dc-dc converters

Converter Gg0 Gd0 0 Q z

buck D VD

1LC

R CL

boost 1D'

VD'

D'LC

D'R CL

D' 2RL

buck-boost – DD '

VD D'2

D'LC

D'R CL

D' 2 RD L

where the transfer functions are written in the standard forms

Gvd(s) = Gd0

1 – sz

1 + sQ 0

+ s0

2

Gvg(s) = Gg01

1 + sQ 0

+ s0

2

Flyback: push L and C to same side of transformer, then use buck-boost equations. DC gains Gg0 and Gd0 have additional factors of n (turns ratio).

ECEN 4517 13

Bode plot: control-to-output transfer functionbuck-boost or flyback converter example

f

0˚

–90˚

–180˚

–270˚

Gvd

Gd0 = 187 V 45.5 dBV

Gvd Gvd

0 dBV

–20 dBV

–40 dBV

20 dBV

40 dBV

60 dBV

80 dBV

Q = 4 12 dB

fz2.6 kHz

RHP Gvd

10-1/2Q f0

101/2Q f0

0˚ 300 Hz

533 Hz

–20 dB/decade

–40 dB/decade

–270˚

fz /10260 Hz

10fz26 kHz

1 MHz10 Hz 100 Hz 1 kHz 10 kHz 100 kHz

f0400 Hz

ECEN 4517 14

The loop gain T(s)

+–

+

v

–

vg

Switching converterPowerinput

Load

–+

Compensator

vref

Referenceinput

HvPulse-widthmodulator

vc

Transistorgate driver

Gc(s)

H(s)

ve

Errorsignal

Sensorgain

iload

Loop gain T(s) = product of gains around the feedback loop

More loop gain ||T|| leads to better regulation of output voltage

T(s) = Gvd(s) H(s) Gc(s) / VM

Gvd(s) = power stage control-to-output transfer function

PWM gain = 1/VM. VM = pk-pk amplitude of PWM sawtooth

ECEN 4517 15

Phase Margin

A test on T(s), to determine stability of the feedback loop

The crossover frequency fc is defined as the frequency where

|| T(j2 fc) || = 1, or 0 dB

The phase margin m is determined from the phase of T(s) at fc , as follows:

m = 180˚ + (T(j2 fc))

If there is exactly one crossover frequency, and if T(s) contains no RHP poles, then

the quantities T(s)/(1+T(s)) and 1/(1+T(s)) contain no RHP poles whenever the phase margin m is positive.

ECEN 4517 16

Example: a loop gain leading toa stable closed-loop system

(T(j2 fc)) = – 112˚

m = 180˚ – 112˚ = + 68˚

fc

Crossoverfrequency

0 dB

–20 dB

–40 dB

20 dB

40 dB

60 dB

f

fp1fz

T

0˚

–90˚

–180˚

–270˚

m

T

T T

1 Hz 10 Hz 100 Hz 1 kHz 10 kHz 100 kHz

ECEN 4517 17

Transient response vs. damping factor

0

0.5

1

1.5

2

0 5 10 15

ct, radians

Q = 10

Q = 50

Q = 4

Q = 2

Q = 1

Q = 0.75

Q = 0.5

Q = 0.3

Q = 0.2

Q = 0.1

Q = 0.05

Q = 0.01

v(t)

ECEN 4517 18

Q vs. m

0 10 20 30 40 50 60 70 80 90

m

Q

Q = 1 0 dB

Q = 0.5 –6 dBm = 52˚

m = 76˚

–20 dB

–15 dB

–10 dB

–5 dB

0 dB

5 dB

10 dB

15 dB

20 dB

Fundamentals of Power Electronics Chapter 8: Converter Transfer Functions94

8.4. Measurement of ac transfer functionsand impedances

Network Analyzer

Injection source Measured inputs

vy

magnitudevz

frequencyvz

outputvz

+ –

input

vx

input+ – + –

vy

vx

vy

vx

Data

17.3 dB

– 134.7˚

Data busto computer

Fundamentals of Power Electronics Chapter 8: Converter Transfer Functions95

Swept sinusoidal measurements

• Injection source produces sinusoid of controllable amplitude andfrequency

• Signal inputs and perform function of narrowband trackingvoltmeter:

Component of input at injection source frequency is measuredNarrowband function is essential: switching harmonics and othernoise components are removed

• Network analyzer measures

vz

vx vy

∠vy

vx

vy

vx

and

Fundamentals of Power Electronics Chapter 8: Converter Transfer Functions96

Measurement of an ac transfer function

Network Analyzer

Injection source Measured inputs

vy

magnitudevz

frequencyvz

outputvz

+ –

input

vx

input+ – + –

vy

vx

vy

vx

Data

–4.7 dB

– 162.8˚

Data busto computer

Deviceunder test

G(s)

inpu

t output

VCC

DCbias

adjust

DCblocking

capacitor

• Potentiometerestablishes correctquiescent operatingpoint

• Injection sinusoidcoupled to deviceinput via dc blockingcapacitor

• Actual device inputand output voltagesare measured asand

• Dynamics of blockingcapacitor are irrelevant

vx

vy

vy(s)

vx(s)= G(s)

Fundamentals of Power Electronics Chapter 9: Controller design64

9.6.1. Voltage injection

• Ac injection source vz is connected between blocks 1 and 2• Dc bias is determined by biasing circuits of the system itself• Injection source does modify loading of block 2 on block 1

+–

H(s)

+–

Z2(s)

Block 1 Block 2

0

Tv(s)

Z1(s) Zs(s)

– +

+

vx(s)

–

vref (s)G1(s)ve(s)

ve(s) G2(s)vx(s) = v(s)

–

vy(s)

+

vzi(s)

ECEN 4517 1

Averaged switch modelingBasic approach (CCM)

Given a switching converteroperating in CCM

Flyback converter example

Separate the switchingelements from theremainder of the converter

Define the terminalvoltages and currents ofthe two-port switchnetwork

+–

LM

+

V

–

Vg

Q1

D11:n

C

+–

LM

+

v

–

vg

Q1 D1

1:n

C

Switch network

i1

i2

– v2 ++

v1

–

ECEN 4517 2

Terminal waveforms of the switch network

v1(t)T

=d′(t)nd(t)

v2(t)T

i2(t)T

=d′(t)nd(t)

i1(t)T

Relationship between averageterminal waveforms:

+–

LM

+

v

–

vg

1:n

C

Switchnetwork

i1

i2

– v2 ++

v1

–

d(t)

iMt

v1(t)

dTs Ts

00

0

vg + v2/n

t

i1(t)

dTs Ts

00

0

iM (t)

⟨v1(t)⟩Ts

⟨i1(t)⟩Ts

t

v2(t)

dTs Ts

00

0

nvg + v

t

i2(t)

dTs Ts

00

0

iM (t)/n

⟨v2(t)⟩Ts

⟨i2(t)⟩Ts

ECEN 4517 3

Averaged model of switch network

Modeling the switch network viaaveraged dependent sources

v1(t)T

=d′(t)nd(t)

v2(t)T

i2(t)T

=d′(t)nd(t)

i1(t)T

From previous slide:

+–

+

⟨v2(t)⟩Ts

–

⟨i1(t)⟩Ts

Averaged switch network

+

⟨v1(t)⟩Ts

–

⟨i2(t)⟩Ts

d′(t)nd(t)

v2(t)T

d′(t)nd(t)

i1(t)T

ECEN 4517 4

PSpice model CCM3

*********************************************************** MODEL: CCM3* Application: two-switch PWM converters,* with (possibly) transformer* Limitations: ideal switches, CCM only*********************************************************** Parameters:* n=transformer turns ratio 1:n (primary:secondary)*********************************************************** Nodes:* 1: transistor positive (drain of an n-channel MOS)* 2: transistor negative (source of an n-channel MOS)* 3: diode cathode* 4: diode anode* 5: duty cycle control input**********************************************************.subckt CCM3 1 2 3 4 5+params: n=1Et 1 2 value={(1-v(5))*v(3,4)/v(5)/n}Gd 4 3 value={(1-v(5))*i(Et)/v(5)/n}.ends*$**********************************************************

Included in the file

Switch.lib

on course website

i2(t) Ts

v2(t) Tsv1(t) Ts

i1(t) Ts

d

+

–

+

–

1

2

3

45

CCM3

ECEN 4517 5

PSPICE simulationOpen-loop simulation of control-to-output transfer function

• Replace flyback converter switches with averaged switch model

• CCM3 and other PSPICE model library elements are linked oncourse web page

• Apply dc voltage (to set steady-state duty cycle) plus ac variation toterminal 5 of CCM3. Plot output voltage magnitude and phase

+–

LM

+

v

–

vg

1:n

C

iM

d

1

2

3

45

CCM3