Lab 4: Register File and Memory 50...

Lab 4 EECE473 Computer Organization & Architecture University of Maine

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Lab 4: Register File and Memory

50 points Instructor: Yifeng Zhu

Due: One week

Objectives:

Build Register File

Build Instruction Memory and Data Memory

1. Overview

A combinational circuit neither contains a periodic clock signal nor has any provisions for

storage. There are no feedbacks involved and the output at all time is dependent on the inputs

provided. The name combinational is derived from the combinations of logic gates used for such

circuits.

A sequential circuit involves feedback and has memory (such as registers and RAM). It also has

a periodic clock signal and hence the output is also a function of time in addition to being a

function of inputs and previous outputs. The name sequential is derived as the output is produced

in sequences as the clock circuit enables and disables the functioning. (A latch is also a

sequential circuit but has no clock signal and hence is a special case. It is also the basic building

block of any sequential circuit.)

Registers have the following key features.

Their current "state" depends on the past sequence of inputs they've seen.

They respond to a "clock" signal, i.e. they only change behavior or state at the instant in

time when the clock signal changes from 0 to 1. This instant is called the "positive edge"

of the clock signal.

In the pipelined processor design, you need to use on-board RAM for instruction memory and data

memory. Note that the instruction memory and data memory are separated. We are following Harvard

Architecture. The following documents on the course website are helpful to access RAM.

RAM Megafunction User Guide

Using the SDRAM Memory on Altera’s DE2 Board with VHDL or Verilog Design

You will instantiate a register and memory components, store values in them, and retrieve those

values in this lab.

2. Register

A register is used to remember a multi-bit value for later use. Each register can remember

exactly one multi-bit value. We call the value currently remembered in the register the register's

“value” or the value “stored” by the register.

The author (Yifeng Zhu) gratefully acknowledges borrowing parts of this homework assignment from

“ENGINEERING 100 (Section 700) Introduction to Computing Systems” ©2006 by Dr. Peter Chen.


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The operation of a register is controlled by four input signals: clock, reset, WriteEnable, and

data_in. The data_in has 4 bits in this lab. A register supports two operations (based on the

values of these signals):

Reset: sets the value of the register to all 0s. A reset operation will occur at the positive

edge of the clock if the value of the reset signal at that time is 1.

WriteEnable changes the value currently stored in the register to equal the value of the

input parameter data_in. For shorthand, we say that we are "writing data_in to the

register". A write will occur at the positive edge of the clock if the value of the write

signal at that time is 1.

The register outputs a multi-bit value, data_out, which is the 4-bit value currently stored in the

register. This value changes immediately after the value stored in the register changes.

A Register

data_in

WriteEnable

reset

clock

data_out

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Figure 1. A simple register that has only 4-bit

Read register.v and identify the operations supported by this component (which is a 4-bit

register). This module introduces two new Verilog constructs:

always @(posedge clock) specifies that the actions in this always block should occur

only at the positive edge of the clock. These are called "edge triggered" always blocks.

// file register.v module register( input wire clock, input wire reset, input wire write, input wire [3:0] data_in, output reg [3:0] data_out); always @(posedge clock) begin if (reset == 1'b1) begin data_out <= 4'h0; end else if (write == 1'b1) begin data_out <= data_in; end else begin data_out <= data_out; end end endmodule


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<= is used as the assignment operator (instead of the normal = operator) within an edge-

triggered always block.

3. Register File

A register file is an array of registers. Like a register, a register file is controlled by the signals

including clock, reset, WriteEnable and data_in. Like a register, a register file outputs a signal

data_out. However, because memory is an array of registers, it needs additional information to

control which element of the array is being operated on. This additional information is called the

memory's address; it is similar to an array index.

For debug purposes, the register file has two extra inputs (read_address_debug, and

clock_debug) and one extra output (data_out_debug). The read_address_debug can be set up by

the switches on the board, and the data_out_debug can be displayed on the 7-segment LEDs or

the LCD. A separate clock_debug allows you to check the value a specific register even when

the processor is not running.

A Register File

(32 Registers)

write_data_in

reset

clock

data_out_2

WriteEnable

32

325

write_address

5read_address_1

5read_address_2

data_out_132

5read_address_debug

data_out_debug32

clock_debug

Figure 2. A register file with 32 registers and each register has 32 bits

The address is stored in an internal register of the memory. To operate on the register file, one

must first write an address to the address port. The current value of the address determines which

register is written to or read from on subsequent access operations.

4. Programming RAM and ROM In the pipelined processor design, you need to use RAM on the DE2 boards for instruction memory and

data memory, respectively. The following documents on the project website are helpful to access RAM.

RAM Megafunction User Guide

Using the SDRAM Memory on Altera’s DE2 Board with VHDL or Verilog Design

4.1 The RAM Interface

The DE2 board provides three types of memory, including 512-Kbyte SRAM, 8-Mbyte SDRAM and 4-

Mbyte Flash memory. The SRAM is organized as 256K×16bits, the SDRAM is organized as


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1M×16bits×4 banks, and the Flash memory is 8-bit data bus. The signals needed to communicate with

this chip are shown in the figure below. All of the signals, except the clock, can be provided by the

SDRAM Controller. The clock signal is provided separately. It has to meet the clock-skew requirements.

Note that some signals are active low, which is denoted by the suffix N.

4.2 Using LPM to Access SDRAM and ROM You can use altsyncram LPM provide in Quartus II to access the RAM on the DE2 board. (Quartus II

also provides lpm_ram_dq and lpm_rom functions, but they are only for backward compatibility. The

altsyncram megafunction is recommended by Altera.) The following briefly summarizes the

procedure of using altsyncram.

The tutorial Using Library Modules in VHDL Designs describes the usage of MegaWizard to

build a desired LPM module.

i. In the Memory Compiler category, you can find RAM: 1-PORT LPM

ii. Select VHDL or Verilog HDL as the type of output file to create

iii. Give the file the name ramlpm.vhd (for VHDL) or ramlpm.v (for verilog)

iv. In the next windows, you can customize the RAM configurations, such as the width,

clock. You can also initiate the values of RAM using a MIF file. The format of MIF

is given in this handout.


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The following notes are copied from Atlera’s RAM Megafunction User Guide.

The RAM: 1-PORT MegaWizard Plug-In Manager allows you to specify either of two

clocking modes: a single clock mode or a dual clock (input/output) mode. In single clock

mode, the read and write operations are synchronous with the same clock. In the Stratix and

Cyclone series of devices, a single clock with a clock enable controls all registers of the

memory block. Dual clock (input/output) mode operates with two independent clocks:

inclock (input clock for write operation) and outclock (output clock for read operation). The

input clock controls all registers related to the data input to the memory block, including data,

address, byte enables, read enables, and write enables. The output clock controls the data

output registers.

Synchronous write operations into the memory block use the address[] and data[] ports,

which are triggered by the rising edge of the inclock while the we (write enable) port is


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enabled. For asynchronous operation, the address[] and data[] signals must be valid at both

edges of the write enable signal. Ideally, the values on the data and address lines should not

be changed while the we port is active.

4.3 Memory Initialization Format (MIF)

The data of the RAM and Rom can be initialized according to an ASCII text file named Memory

Initialization Format (with the extension .mif). The following gives two example MIF files.

Note: If multiple values are specified for the same address, only the last value is used.

5 Lab Instructions and Requirements

Please note the following should be implemented in the same project.

DEPTH = 256; % Memory depth and width are required %

WIDTH = 16; % Enter a decimal number %

ADDRESS _RADIX = HEX; % Address and value radixes are optional %

DATA-RADIX = HEX; % Enter BIN, DEC, HEX, or OCT; unless %

% otherwise specified, radixes = HEX %

-- Specify initial data values for memory, format is address : data

CONTENT BEGIN

[00..FF] : 0000; % Range - Every address from 00 to FF = 0000 %

-- Computer Program for A = B + C

00 : 0210; % LOAD A with MEM(10) %

01 : 0011; % ADD MEM(11) to A %

02 : 0112; % STORE A in MEM(12) %

03 : 0212; % LOAD A with MEM(12) check for new value of FFFF %

04 : 0304; % JUMP to 04 (loop forever) %

10 : AAAA; % Data Value of B %

11 : 5555; % Data Value of C %

12 : 0000; % Data Value of A - should be FFFF after running program $

END;


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5.1 Build the Register File.

a. Implement the simple register shown in Figure 1. Initialize the register value as

0xF0F0F0F0. Verify the correctness of your design via simulation.

b. Implement the register file shown in Figure 2. Initialize the register i with a value of i,

where i = 0,1,…,31. For example, register 11 is initialized as 0x0000000A. Verify the

correctness of your design via simulation.

5.2 Build the Data Memory.

a. You should be able to read and write SDRAM by using RAM: 1-PORT MegaWizard Plug-In

Manager. The output of SDRAM is 32 bits. The SDRAM will be used as the data memory in

the project. Note that we are using 32-bit wide data memory to simplify the design since we

will use load word (lw). As a result, in one cycle, we can get the data out.

b. In MegaWizard, both the input and output can be registered or not registered. First of all,

make both registered and test it on the board. Then make the output not registered and test it

again on the board. Find out the difference between registered and not registered.

c. In MegaWizard, you can use “single clock” or “dual clocks”. The dual clocks have separated

clocks for inputs and outputs. Make the right choice.

d. Initialize the data memory as the following. Please note the data memory address in MIPS

code is in terms of bytes, not words. Test your design on the Altera DE2 board using the

display and control specification given at the end of this handout.

e. Please note that in the MIPS programs, the data segment starts at 0x10000000. Since the

data size of our test programs is small, thus you can ignore the most significant four

bits in the data address.

Address Code

1 0x10000000 0x00000001

2 0x10000004 0x00000002

3 0x10000008 0x00000003

4 0x1000000c 0x00000004

5 0x10000010 0x00000005

6 0x10000014 0x00000006

7 0x10000018 0x00000007

8 0x1000001c 0x00000008

9 0x10000020 0x00000009

10 0x10400024 0x0000000A

11 0x1000002c 0x0000000B

12 0x10000030 0x0000000C

13 0x10000044 0x0000000D

14 0x10000048 0x0000000E

15 0x1000004c 0x0000000F

16 0x10000050 0x00000010


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5.3 Build the Instruction Memory.

a. In the project built in Step 1, add a new component that can read ROM by using ROM: 1-

PORT MegaWizard Plug-In Manager. The output of ROM is 32 bits. The ROM will be used

as the instruction memory in the project.

b. In MegaWizard, both the input and output can be registered or not registered. You need to

make the right choice for both input and output.

c. MegaWizard allow to select “single clock” or “dual clocks”. The dual clocks have separated

clocks for inputs and outputs. Make the right choice.

d. Initialize the instruction memory as the following. Please note the instruction memory

address in MIPS code is in terms of bytes, not words. Test your design on the Altera DE2

board using the display and control specification given at the end of this handout.

e. Please note that in the MIPS programs, the instruction segment starts at 0x00400000. Since

the data size of our test programs is small, thus you can ignore the most significant 12

bits in the data address.

Instruction Address Code

1 add $3, $2, $1 0x00400000 0x00411820

2 addu $3, $2, $1 0x00400004 0x00411821

3 sub $3, $2, $1 0x00400008 0x00411822

4 subu $3, $2, $1 0x0040000c 0x00311823

5 and $3, $2, $1 0x00400010 0x00411824

6 or $3, $2, $1 0x00400014 0x00411825

7 nor $3, $2, $1 0x00400018 0x00411827

8 slt $3, $2, $1 0x0040001c 0x0041182a

9 sll $3, $2, 1 0x00400020 0x00021840

10 srl $3, $2, 1 0x00400024 0x00021842

11 jr $2 0x0040002c 0x00400008

12 nop 0x00400030 0x00000000


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5.4 On Board Display and Control Setup

Register, Instruction

Memory or Data Memory

Address

Program CounterClock Counter

HEX7 HEX6 HEX5 HEX4 HEX4 HEX2 HEX1 HEX0

17 16 1514 13 12 11 10

Toggle swiches

Pushbutton Swiches

3 012

RESET

17 = Clock Control

0: manual clock

1: 1Hz clock

Manual Clock

INSTR=FFFFFFFF

Value = EEEEEEEE

LCD

15,16 = LCD Value

00: Register

01: Data

10: Instruction

9 8 7 6 5

SW[5-9] Data

Memory Address

SW[10-14]

Instruction Memory

Address

04 3 2 1

SW[0-4]

Register Address

The project is reset by the push button 0 (KEY[0]).

The program counter (HEX5 and HEX4) shows the instruction memory address. You might need to

modify your register file to add one address input and one data output.

The clock counter (HEX0-4) shows how many cycles you design has run and it starts from 0.

The LCD has two rows. The first row shows the instruction addressed by the program counter (HEX5

and HEX4). The second row shows the value which is controlled by SW[15-16], which could be a

value pointed by a register address SW[0-4], or a data memory address SW[5-9] or an instruction

memory address SW[10-14]. The actual address should be shown in HEX7 and HEX6. You might

need to modify your memory module to add one address input and one data output.

Your lab should be able to run by using two different clocks: (1) a system 1-Hz clock and (2) a

manual clock. Use the switch SW[17] to switch between these two clocks. (If SW[17] = 0, the system

1Hz clock is used. Otherwise the manual clock is used.) Using the system clock allows your code to


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automatically complete the test programs. The manual clock is generated by the push button 1

(KEY[1]). For each push, generate a HIGH signal for only one second no matter how long the push

button is pressed. Note that the LCD still needs the on-board clock.

You can use other LED lights to monitor your control signals.

Part 2: Show your Results on LCD and LED

Download your code into the DE2 board and dynamically show the Ulam sequence numbers on the LCD screen.

You might need to follow some tutorials of DE2 on our project website or altera.com. You can find LCD

information (HITACHI HD44780 Dot Matrix LCD) and the DE2 PIN assignment documents on the course project

website.

Each digit should stay on the LCD for a sufficient amount of time so that we can read it. For example, you could set

the clock rate to 0.5Hz. Then every 2 seconds, an Ulam number is shown on the LCD. The numbers should be

dynamically shown on the screen, i.e., you cannot just show all numbers together at the first step. Similarly your

results should also be shown on the LED simultaneously. A sample Clock, LED LCD driver will be provided. The

following shows some diagram of some drivers.

LED Controller Push bottom Debounce


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LCD controller Clock Divider

The LCD_Display is used to display static ASCII characters and changing hex values from hardware on a two-line

LCD display panel. Number_Hex_Digits is used to set the size of the Hex_Display_Data input. Each hex digit

displayed requires a 4-bit signal. The reset signal should be active high whenever you want update the LCD display.

Make sure that the pins LCD_ON and LCD_BLON are set as active high. These two pins are not set by the

controller. You can find more information about the LCD controller in the course project website. LCD_E is

actually LCD_EN.

The debounce circuit is used to filter mechanical contact bounce in the DE2’s push buttons. A shift register is used

to filter out the switch contact bounce. The shift register takes several time spaced samples of the push button input

and changes the output only after several sequential samples are the same value. Clock is a clock signal of

approximately 100Hz that is used for the internal 50ms switch debounce filter design. The pb_debounced is the

output. The output will remain Low until the pushbutton is released.


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ECE 473 Lab 4

TA Checkoff Sheet

Total: 50 points

Name: ____________________________

Date: _____________________________

Final Grade: ________________________

TA Signature: _______________________

You need to demo the following three requirements on the DE2 board.

1) Register file works correctly with manual clock and 1Hz clock (20 points)

2) The instruction memory works correctly with manual clock and 1Hz clock (10 points)

3) The data memory works correctly with manual clock and 1Hz clock (10 points)

Lab 4: Register File and Memory 50...

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