Shift Register Based QCA Memory Architecture · Shift Register Based QCA Memory Architecture...

Shift Register Based QCA Memory Architecture

SEMINAR REPORT2009-2011

In partial fulfillment of Requirements inDegree of Master of Technology

InSOFTWARE ENGINEERING

SUBMITTED BY

Bineesh.V

DEPARTMENT OF COMPUTER SCIENCECOCHIN UNIVERSITY OF SCIENCE AND TECHNOLOGY

KOCHI – 682 022

COCHIN UNIVERSITY OF SCIENCE AND TECHNOLOGYKOCHI – 682 022

DEPARTMENT OF COMPUTER SCIENCE

CCEERRTTIIFFIICCAATTEE

This is to certify that the seminar report entitled “Shift Register

Based QCA Memory Architecture ”” is being submitted by Bineesh.V in

partial fulfillment of the requirements for the award of M.Tech in Software

Engineering is a bonafide record of the seminar presented by her during the

academic year 2009.

Dr.Sumam Mary Idicula Prof. Dr.K.Poulose JacobReader DirectorDept. of Computer Science Dept. of Computer Science

ACKNOWLEDGEMENT

I wish to express my deep sense of gratitude to Prof. Dr. K Poulose

Jacob, Director, Department of Computer Science, for providing the

necessary infrastructure and encouragement to present the seminar. I would

like to mark my sincere thanks and indebtedness for Dr. Sumam Mary

Idicula, Reader, Department of Computer Science, for all the guidance

and support, extended to me. In addition, I thank Mr. G. Santhosh Kumar,

and also all the teaching and non-teaching staff of the department and all my

friends for extending their helping hands.

I would also like to thank my parents without whose blessings and

support, achieving this goal would have been an impossibility. Finally, I

thank the Almighty for giving the strength and blessings.

TABLE OF CONTENTS

Sl No. Title Page No.

1 INTRODUCTION1

2 PROBLEM 2

3 SOLUTION 3

4 QUANTUM DOT CELLULAR AUTOMATA 4

5 QCA MEMORY

9

6 A SHIFT REGISTER BASED QCAMEMORY 16

7 CONCLUTION 19

8 REFERENCE20


Department of Computer Science, CUSAT. 1

1.INTRODUCTION

Quantum-dot cellular automata (QCA) is a potentially promising technology as an

alternative to complementary-metal-oxide semiconductor (CMOS) technology for nanoscale

device implementations. The implementation of the QCA technology has been demonstrated

with metal-dot QCA devices at very low (e.g., cryogenic) temperatures. Circuit structures

such as the majority gate, binary wires and fan outs have been fabricated with metal-QCA

dots.

A quantum-dot cellular automata (QCA) design of an nxm-bit, shift-register-based

memory architecture is presented. The architecture maintains data at a stable conformation,

which is contrary to traditional data in-motion concept for QCA architectures. The memory

architecture is based on an existing dual-phase-synchronized, line-based, one-bit QCA

memory cell building block that provides size and latency improvements over other known

one-bit memory cells through its novel clocking scheme. Read/write latencies up to ~2X

lower than the existing tile-based architecture with three-phase, line-based memory cells are

obtained.



2.PROBLEM

As silicon technology is reaching the lower end of nanometer ranges of feature size

(45nm CMOS technology is already in use), as per the International Technology Roadmap

for Semiconductors(ITRS), the 45 nm technology node should refer to the average half-pitch of

a memory cell manufactured at around the 2007–2008 time frame.Matsushita and Intel started

mass producing 45 nm chips in late 2007, and AMD started production of 45 nmchips in late

2008, while IBM, Infineon, Samsung, and Chartered Semiconductor have already completed a

common 45 nm process platform..

The 32 nanometer (32 nm) process (also called 32 nanometer node) is the next step after

The the45 nanometer process in CMOS manufacturing and fabrication

The 22 nanometer (22 nm) node is the CMOS process step following 32 nm. It is expected to be

reached by semiconductor companies in the 2011–2012 timeframe. At that time, the typical half-

pitch for a memory cell would be around 22 nm.

The ITRS 2006 Front End Process Update indicates that equivalent physical oxide

thickness will not scale below 0.5 nm which is the expected value at the 22 nm node. This is an

indication that CMOS scaling in this area has reached a wall at this point.

The continuation of Moore's law-based scaling of silicon technology is now facing

several challenges. The reduced feature size implies a larger number of the transistors on

the unit area of silicon chips which provides both scopes for newer features in our com-

putation capabilities, coupled with the problem of increased defect rates and susceptibility

to transient faults. Since defect rates can go up 10% or more, traditional discarding of silicon

chips based on defects would reduce yields to such low levels that alternative measures of

yield enhancements are imperative. One possible way is to enhance the computing logic

and micro-architectures with defect- and fault-tolerance features that would make

computation robust against such high level of defects and faults, hence increasing yields.



3.SOLUTION

On the other hand, engineers and scientists are now engaged in finding alternatives to

silicon-based computing. One possible way for the microelectronics industry to maintain

growth in device density is to change from the Silicon-based paradigm to one based on

nanostructures

such that nanoscale computation can be realized with molecular dynamics, quantum

effects, and other nontraditional material and computation paradigms. Molecular

transistors, DNA-scaffolding-based computation fabrics, carbon nanotube-based field effect

transistors, carbon nanotube-based PLA type fabrics, and many other technological

advances are happening in various academic and industrial labs.

One nanostructure paradigm, is the“Quantum-Dots” – these are nanostructures created

from standard conductive materials. These structures can be modeled as 3-dimensional quantum

wells.



4 QUANTUM DOT CELLULAR AUTOMATA(QCA)

4.1Quantum Dot and QCA

WHAT ARE QUANTUM DOTS?

A quantum dot is a nanometer sized structure that is capable of trapping electrons in three

dimensions. Quantum dots are made by creating an island of conductive material surrounded by

insulating material. Electrons that enter the quantum dot will be confined because of the high

potential required to escape.

QCA- 4 quantum dot device

The logic unit in QCA is the QCA cell which was proposed by researchers at the University

of Notre Dame. A basic QCA cell consists of four quantum dots in a square array coupled by

tunnel barriers.

Quantum dot

Single QCA cell

Quantum-dot cellular automata (QCA) is a nanoscale technology that is projected to permit

improved operating performances compared to CMOS technologies. Quantum-dot cellular

automata (QCA) is a novel alternative to the transistors, silicon, and CMOS paradigm. Rather

than using charge movement, current, to propagate signals and perform operations, QCA uses

devices as charge holders, using Coulombic repulsion of electrons as the primary computing

force. A QCA cell consists of four quantum dots arranged in a square with two excess electrons

that can occupy the dots. Because the electrons are repelled by each other, they naturally reside

in opposite corners. As a result, the cell has two stable states. The first is an electron in the

bottom left corner and the top right corner. A cell with this conguration has a polarization of +1

and represents logical “1". The second stable state is an electron in the top left corner and the

bottom right corner, a polarization of -1 representing a logical 0 The electrons can tunnel

between the quantum dots allowing them to change congurations.



Figure QCA Cell (a) Polarization and corresponding logic values, (b) Signal propagation in QCA. The cell on the left is polarized, the cell on the right is unpolarized. The cell on the right transitions to assume the polarization of the driving left cell.

4.2 QCA Clocking Scheme

Computation is performed by controlling the tunneling with a four phase clock"signal

Unlike CMOS circuits, the QCA clock is a fundamentally different phenomenon than the data.

The clock raises and lowers the barriers between the dots, alternately prohibiting and allowing

the electrons to tunnel between dots.

The raising and lowering behavior of the clock signal is described by four phases called

-Switchphase,

-Hold phase

-Release phase

-Relax phase.

In the switch phase, the barriers begin low, allowing tunneling, and are raised to prohibit

tunneling. In this phase, the cell transitions from having no value to having a definite value.

The hold phase follows switch in which the barriers are maintained high, preserving the

value assumed during switch.

In the release phase, the barriers are falling, allowing the cell to go from a well defined

state to an undefined state in which the cell has no natural polarization.

Finally, the relax phase maintains low barriers and no polarization



Figure- 4 clock phases

4.3 QCA Devices

4.3.1.Wires

If QCA cells are lined up side by side and clocked appropriately, they act as a wire,

propagating a signal down its length (figure 4.3.a). Cells laid out in this side by side manner are

called 90 degree cells. The alternative is 45 degree cells whichare laid out corner to corner

(figure 4.3.b). In a 45 degree wire, the signal is inverted at each cell. If the first cell holds a “1",

the second cell will hold a “0", followed by a “1" in the third cell, and so on.

Figure 4.3.1. a) 90 digree wire b) 45 digree wire



Below figure 4.3.1.c shows propogation of information through 90 digree wire

Figure 4.2.1.c: Propogation of information through 90 digree wire

4.3.2 Three input Majority Gate

The basic logic gate in QCA is the three input majority gate (figure 1.6a). Three input cells

are arranged on the edges of a center “device cell." The output of the gate is on the fourth edge of

the device cell. The input cells and the device cell share the same clock zone. Because of this and

simple coulombic repulsion, the device cell assumes the value of the majority of the inputs.

When this device cell is frozen in the hold phase, it drives the output cell which then proceeds as

a normal QCA wire .It is notable that the majority gate is a natural, native device in QCA. It

requires nothing more than the QCA cells and clocking already introduced.

figure : majority gate ( input- A, B, and C) and logic Symbol



Truth table

Majority gate implements the majority function of its three inputs A, B and C:

M(A,B,C) = AB+AC+BC.

4.3.3 AND , OR and NOT gate

This majority gate can be converted to either an AND gate or an OR gate by fixing one of the

inputs to be permanently “0" or “1" respectively.

AND gate OR-gate

QCA Inverter or NOT gate



5 QCA MEMORY

Memory design in QCA logic has been a challenge1 due to the locality of computation and

constant propagation of data in cellular automata.:

—Two types of line-topology-based memory cells:

three-phase memory cell presented in Vankamamidi and

dual-phase memory cell presented in Taskin and Hong

—Two memory architectures:

tile-based architecture presented in Vankamamidi and Ottavi and

shift-register-based architecture presented in this article.

The two types of line-based memory cells are similar in topology and design, and

differ from other memory and logic cells in promoting the use of alternative clocking schemes

in addition to the four-phase clocking scheme conventionally used in QCA operation. The

alternative clocking schemes, significant performance improvements in read/write latency (in

the number of clock cycles) and cell area (in the number of clocking zones) are achievable.

For instance, a tile-based nxm bit memory architecture design is presented in

Vankamamidi and Ottavi that uses the three-phase line-based memory cell presented in

Vankamamidi with the unconventional three phase clocking scheme. This tile-based memory

architecture provides conventional memory operation with a denser bit-storage area than

previously offered QCA memory architectures.

The shift-register-based, nxm memory architecture that utilizes dual-phase, line-based

memory cell presented in Taskin and Hong with the unconventional dual-phase clocking

scheme. Similar to the tile-based architecture, the design density is much improved over

previous QCA memory architectures. Furthermore, read/write latency of the proposed

shift-register architecture is up to ~2X lower than the previously proposed tile-based QCA

memory architecture.



5.1 LINE-BASED MEMORY CELLS Line-based memory cells are built on the premise of bidirectional data flow. Note that,

bidirectional data flow is not possible with the conventional four-phase clocking scheme.

By defining additional clock phases, however, some combination (two or more) of clock

zones can create flows in one direction at certain durations of their periodic clocking cycle

whereas the direction can be reversed at other durations. In other words, two adjacent clock

zones that are in hold and switch phases (respectively) at one time can later be observed in

the switch and hold phases, respectively.

The two types of line-based memory, the three-phase and the dual-phase memory, are

reviewed in Sections 3.1 and 3.2, respectively.

5.1.1 Three-Phase Line-Based Memory

The three-phase, line-based memory Figure 5.1.(a), is the first study to exploit

non-standard clocking strategies in QCA operation. This cell consists of three clock zones

C4,C5,C6, where the four conventional clocking zones in the rest of the circuit are labeled Co,

C1, C2, C3. Clock phase C5 is identical to one of the clock phases of the four-phase clocking

scheme, namely C2 in Figure 5.l(b). Thus, unlike C4 and C6, the clock phase C5 does not

require an additional clock source. Consequently, the three-phase clocking scheme requires

two additional clock generator circuits. Clock signals to zones 4,5, and 6 (synchronized by

phases C4, C2 = C5, and C6, respectively) all follow the hold-release-null-switch cycle. The

clock phase of zone 5 is specially designed such that when either zones 4 or 6 is in the hold

phase, zone 5 is in the switch phase, enabling bidirectional data flow—and storage—on the

memory line between Z and Out. The read/write latency of the three-phase cell is equal to

the period 2T of the synchronization scheme (where T is the period of the conventional

four-phase clocking scheme).

The core of this memory is the majority gate structure that consists of QCA cells a, b, c, m,

and d. Depending on the step of operation [see Fig. 5(b) for steps], the inputs to the majority gate

alternates between {a,b,c} and {a,b,d}. With such alteration and proper input sequences, the

stored data moves back and forward between zones 4 and 6 on the QCA line formed between Z

and Out. Inputs A and B constantly drive the majority gate in zone 5, controlling whether a new

data value should be written into the memory cell or the old data value should be preserved.



figure 5.1

Read/Write Circuit

This read/write circuitry can also be used for both three-phase and dual-phase line-based

QCA memory cells.The schematic diagram of this circuit (featuring a line-based memory cell)

Read/write logic



5.2 DUAL PHASE LINE-BASED QCA MEMORY DESIGN

The dual-phase, line-based memory cell is shown in Figure5.2.. This new memory cell

consists of two clock zones and requires two additional clock phases as shown in Fig.5.2 (a). The

two clock phases—C7 and C8 shown in Fig. 5.2(b)—have identical waveforms with phase shifts.

Thus, the additional clock phases are generated by a single (1) clock generator and a phase

shifter, saving design complexity over two (2) additional clock generators of the three-phase

line-based memory cell .

figure 5.2 Two Phase line Based Memory

A two step operation is offered for the proposed dual-phase, line-based QCA memory cell.

In step 1: Zone 7 switches when zone 8 is holding.

In step 2: Zone 8 switches when zone 7 is holding.

With such a mechanism, the stored data moves back and forward on the line (between Z and

Out), constituting the memory storage.



Memory Operation

The control logic computes the values assigned to inputs A and B

Based on the values of A and B, and states of zone 6 and zone 7, the three memory

operations can be performed. In brief, the Read operation is performed from zone 8, through the

output terminal Out.When zone 8 is in the hold phase, the data propagates to the output terminal

Out, regardless of the state of zone 7 and the input patterns at inputs A and B. The Write

operation is performed through Zone 7,through the input terminals A and B. When A = I and B =

I, the majority gate writes the value I onto theline, thus to the memory cell [M(I, I,X) = I.I+I.X

+I.X = I]. The Maintain operation is performed by applying A = 0 and B = 1. This input

combination forms the majority gate {a,b,c,m,d} which preserves the value X stored on the line,

implementing the maintain operation [M(0,1,X) = 0.1+0.X +1.X = X].

The three memory operations with respect to the two-time step operation [Fig. 5.2(b)] are as

follows, with illustrations for each operation shown in Figure 5.3:

1) Writing a new value into the memory. During step 1 in Fig. 5.2(b), zone 8 of the memory

cell is in the hold phase and zone 7 is in the switch phase. The inputs A and B are assigned A =

I1 and B = I1, where I1 is the input data as shown in Fig. 5.3(a). The five QCA cells a, b, c, d, m

form a majority gate, where cells a, b, d become the inputs and c becomes the output of the gate.

Since a = A = I1 and b = B = I1, output evaluates to c = Z = I1 regardless of the value X of d

(which was the original valued stored in the memory cell):

M(I, I,X) = I1.I1+I1.X +I1.X = I1(I1+I1+X) = I1.

Consequently, the data input I1 is written into c (i.e. the memory). This final state is presented in

Fig. 5.3(b) (which is also selected as the initial stage of the maintain operation discussed next.)

2) Maintaining the data value stored in the memory. Following a write operation,

R/W is set to 0 .

a) During step 2 in Fig. 5.3(b), zone 7 is in the hold phase and zone 8 is in the switch

phase.All four QCA cells a, m, b and c hold the value of I1 as the result of the write operationin



operation 1. Therefore zone 8 will switch to the value of I1 during this step, i.e. d = I1and Out =

I1. Note that, due to the placement of clocking zones, the majority gate structure formed by QCA

cells a, m, b, c, d does not implement the majority function. Instead, QCA cells a, m, b, c are

holding their value, while QCA cell d is switching. Such a structure behaves similar to a QCA

wire, transferring the value from QCA cells in hold phase to theQCA cells in switching phase.

Because the QCA cells a, m, b, c all hold the same value (I1),the next-state of QCA cell d

resumes value I1.

b) In the next operation [step 1 again in Fig. 7(b)], zone 8 is in the hold phase; zone 7 is inthe

switch phase. The five QCA cells a, b, c, d, m form a majority gate with a = A = 0, b = B = 1,

and d = I1 as inputs and c are the output cell: M(0,1, I1) = 0.1+0.I1+1.I1 = I1. (2) This operation

is illustrated in Fig. 5.3(c). The data value I1 will be maintained into c at theend of this clock

phase [shown in Fig. 5.3(d) and discussed next].

c) In the next operation, [step 2 again in Fig. 7(b)], zone 7 is in the hold phase and zone 8 is in

the switch phase. QCA cells a, m, b and c hold the values of 0, (stored value) I1, 1 and (stored

value) I1, respectively, following operation 2b. Similar to operation 2a, the five QCA cells do not

implement the majority function. Instead, Coulomb interactions between the holdingcells and

switching cells are computed to determine the next-state value of switching cells.Consequently,

the cells in zone 8 [d through Out] switch to the I1 during this operation.

d) Operations 1 and 2 are repeated and the data is transferred back and forward between

zones7 and 8 until another write operation is executed.

3) Reading the data value stored in the memory. The read operation is performed from

terminal Out when zone 8 is in the hold phase as shown in Fig. 5.3(e). When the QCA cells

placed next to terminal Out next to clock zone 8 are in switching phase, the stored data is read

from the memory. Note that read operation can also be performed in Figures 5.3(a) and 5.3(c)

(i.e. zone 8 is hold), for values X and I1, respectively.



5.3 illustration of read, write and maintain memory operation



6. A Shift-Register-Based QCA Memory Architecture

A quantum-dot cellular automata (QCA) design of an, shift-register-based memory

operated as the name suggested; maintains data at a stable conformation, which is contrary to

traditional data in-motion concept for line based memory QCA architectures. The memory

architecture is based on an existing dual-phase-synchronized, line-based one-bit QCA

memory

The building block of the presented shift-register-based memory architecture is shown in Figure

6(a). The data storage in the building block is established with the dual phase memory cell and the

read/write control is maintained through the AND and NOR gates. The memory architecture is build

similar toa shift register, where data is stored within the bilding blocks and the block are replicated

for a multibit storage mechanism

Fig 6(a).CMOS Equivalent of the building block

Fig. 6(b).Template building block for the shift-register-based memory architecture: the line-based memory cell with control circuitry.



The CMOS equivalent of building block for the shift register based memory architecture

is shone in figure 6(b) .In brief, the dual phase ,line based memory cell maintains data by

applying opposite value to the two inputs(X not equal to Y). In order to write data D into the cell,

identical values are applied to two inputs(X=Y=D). A read/write signal R/W is defined for each

row that permits the read/write operation on the m-bit long, shift register structure (of an nxm

memory).The read/write control circuitry (AND and NOR gates ) drives the input X and Y,

based on the data signal D and a read/write signal R/W:

X = ((R/W)’.D + (R/W)D’) ‘ = (R/W) X-NOR D

Y = D

When the Read/Write (R/W) signal is asserted, new data is written in, while the previously stored data is

read:

X = 1 X-NOR D = D = Y => (X =Y =D, write operation).

The rest of the time (when R/ W = 0), the data remains stored:

X = 0 X-NOR D = D = > ( D Not Equal to Y maintain data).

Fig. 6(c) Block Diagram of a sample nxm memory architecture, where n=4 and m=8



Fiq 6(d) QCA realization of sample n m memory, where n=4 and m=8



7. CONCLUSION

The shift-register-based QCA memory architecture benefits of the dual-phase, line-

based memory cell are observed in the proposed shift-register-based architecture in a dense

implementation with desired regularity in clock zone alignments. The read/write latency is

linear in the number of bits stored per row, which records up to ~2X improvements in

read/write latency over of the tile-based memory architecture (with three-phase, line-based

memory cells). Furthermore, unlike the tile-based memory architecture, shift-register-based

architecture provides constant read/write latency.



8. REFERENCES

(i) A Shift Register based QCA Memory Architecture by B. Taskin ,A.Chiu ,Q.U Salkind , D. Venutolo (Drixel university) ACM journal on Emerging Technologies in Computing systems volume 5, No.1, Article 4 , Pub. Date : January2009 (ii) A Shift Register based QCA Memory Architecture ieeexplore.ieee.org/xpls/abs_all.jsp?arnumber=4400858

(iii) A Line-Based Parallel Memory for QCA Implementation Vamsi Vankamamidi, Marco Ottavi, Member, IEEE ieeexplore.ieee.org/xpls/abs_all.jsp?arnumber=1528473

(iv) Dual-Phase Line-Based QCA Memory Design Baris Taskin and Bo Hong , Drexel University

ieeexplore.ieee.org/xpls/abs_all.jsp?arnumber=4624551

(v) Improving Line-Based QCA Memory Design Through Dual Phase Clocking By Baris Taskin, Member, IEEE and Bo Hong, Member, IEEE (vi) Quantum Dot Cellular Automata

http://en.wikipedia.org/wiki/Quantum_dot_cellular_automaton (Accessed on : 20-10- 09)

(vii) 45 nm technology en.wikipedia.org/wiki/45_nanometer (Accessed on : 28-10- 09)

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