Kavitha Resume
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Kavitha. D [email protected] +91 9629611628 CAREER OBJECTIVE To work for an organization that provides me a chance to exhibit my skills and help me to develop myself and my organization. EDUCATIONAL QUALIFICATIONS Completed B.E(Electronics and Communication Engineering) in Jayaram College of Engineering and Technology with a CGPA of 7.64 in 2013 Completed HSC examination in Sowdaambika matric Higher Secondary School, Thuraiyur with 83.3% in 2009 Completed SSLC examination in Dr.Kalaignar Karunanithi Girls Higher Secondary School, Thuraiyur With 77.4% in 2007 AREA OF INTEREST Microprocessor and controller VLSI COMPUTER PROFICIENCY Operating Systems : Windows Software Package : MS Office Language Known : C, C++, Verilog, VHDL AWARDS AND ACHIEVEMENTS Secured 1 nd PRIZE in SPOT EVENT at Chenduran College of Engineering and Technology, Pudhukottai. Secured 2 rd PRIZE in Paper presentation at Sudharsan Engineering College, Pudukkottai.
Transcript of Kavitha Resume
Kavitha. D
[email protected] +91 9629611628
CAREER OBJECTIVE
To work for an organization that provides me a chance to exhibit my skills and help me to develop myself and my organization.
EDUCATIONAL QUALIFICATIONS
Completed B.E(Electronics and Communication Engineering) in Jayaram College of Engineering and Technology with a CGPA of 7.64 in 2013
Completed HSC examination in Sowdaambika matric Higher Secondary School, Thuraiyur with 83.3% in 2009
Completed SSLC examination in Dr.Kalaignar Karunanithi Girls Higher Secondary School, Thuraiyur With 77.4% in 2007
AREA OF INTEREST
Microprocessor and controller VLSI
COMPUTER PROFICIENCY
Operating Systems : Windows
Software Package : MS Office
Language Known : C, C++, Verilog, VHDL
AWARDS AND ACHIEVEMENTS
Secured 1nd PRIZE in SPOT EVENT at Chenduran College of Engineering and Technology,
Pudhukottai.
Secured 2rd PRIZE in Paper presentation at Sudharsan Engineering College, Pudukkottai.
Secured 3rd PRIZE in Technical marketing event and Technical quiz at K.S.R Engineering College, Thiruchengode.
ACADEMIC PROJECT
Title: A Rotation Based BIST with Self-feedback Logic to Achieve Complete Fault Coverage
In our project, a deterministic BIST technique that can efficiently achieve complete fault
coverage without using any storage devices.
A novel test structure containing a self-feedback logic unit and a circular shift register is
Proposed by which all the required deterministic patterns can be generated on-chip in real time.
Built-In-Self Test (BIST) has become a major design consideration in Design-For-Testability
(DFT) methods. BIST is beneficial in many ways.
Software and Tool : Modelsim-Altra 6.6d
Language used : VHDL
CO-CURRICULAR ACTIVITIES
Presented a paper in National Level Technical Symposium on “ROBOTICS” at Sudharsan Engineering College, Pudukkottai.
Presented a paper in National Level Technical Symposium on “IMAGE PROCESSING” at K.S.R Engineering College, Thiruchengode.
Exhibited a mini project on topic “AUTOMATIC BREAK CONTROL SYSTEM” at Jayaram College of Engineering & Technology, Trichy.
Participated in the Workshop on “PCB designing &Fabrication process and 3D animation” for 2days.
Have Undergone an Implant training at BSNL and AIR, Trichy.
CERTIFICATION AND TRAINING
Completed course on Diploma in Computer Application.
Attended training program in INFOSYS campus connect program.
EXTRA CURRICULAR ACTIVITIES
Acted as the class representative in school.
Participated in NSS health camp.
Participated in March Past in school.
PERSONAL DETAILS
Father’s name : V.Dhandapani
Date of Birth : 30th May, 1992
Languages Known : Tamil, English, and Telugu
Hobbies : Listening soft music
Place:
Date: (D.KAVITHA)
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