k t c i u h o s t l b s c o a r b i c t p n t i e g rn o t u d i s h c n...
33
+ - + - (a) A simple oval presents no opportunity for short circuits + - + - + - (b) A diagonal reversing pass in the oval creates a short circuit (c) A cut in both tracks will remove the short circuit (d) Adding a second cut in both tracks creates an independent “block” ARTICLE 1, Figure 1
Transcript of k t c i u h o s t l b s c o a r b i c t p n t i e g rn o t u d i s h c n...
+ -+-
(a)
A s
impl
e ov
al p
rese
nts
noop
port
unity
for
shor
t circ
uits
+ -+- +-
(b)
A d
iago
nal r
ever
sing
pas
sin
the
oval
cre
ates
a s
hort
circ
uit
(c)
A c
ut in
bot
h tr
acks
will
rem
ove
the
shor
t circ
uit
(d)
Add
ing
a se
cond
cut
in b
oth
trac
ks c
reat
es a
n in
depe
nden
t “bl
ock”
AR
TIC
LE 1
, Fig
ure
1
Blo
ck 1
Blo
ck 2
(a)
Sim
ple
layo
ut d
ivid
ed in
to tw
obl
ocks
for
DC
C c
ontr
ol
Blo
ck 1
Blo
ck 2
Blo
ck 3
Blo
ck 4
Blo
ck 5
Blo
ck 6
Blo
ck 7
Blo
ck 8
Blo
ck 9
Blo
ck 1
0(b
) S
ame
layo
ut d
ivid
ed in
to te
nbl
ocks
for
conv
entio
nal c
ontr
olA
RT
ICLE
1, F
igur
e 2
R1
0 V
olt
R2
+ve
Det
ectio
nO
utpu
t
(a)
Sim
ple
optic
al d
etec
tor
IR L
ED
R1
0 V
olt
R2
+ve
Det
ectio
nO
utpu
t
R3
C1
Pul
sed
sour
ce
(b)
impr
oved
opt
ical
det
ecto
r
+ve
R1
R2
R4
R3 0 V
olt
Det
ectio
nO
utpu
t
Fro
m T
hrot
tle(t
rain
pow
ersu
pply
)
To
reve
rse
switc
h
(c)
sim
ple
load
det
ecto
r A
RT
ICLE
2, F
igur
e 1
Tim
e
Voltage (a)
Ful
l wav
e re
ctifi
ed A
C w
avef
orm
show
ing
RM
S le
vel
Tim
e
Voltage (b)
Hal
f wav
e re
ctifi
ed A
C w
avef
orm
show
ing
RM
S le
vel
Tim
e
Voltage (c)
Pul
se W
idth
Mod
ulat
ion
wav
efor
msh
owin
g R
MS
leve
l
02468
10
12
14
Tim
e
Voltage
(d)
Pul
se W
idth
Mod
ulat
ion
supe
rimpo
sed
on a
pur
e D
C fl
oor
AR
TIC
LE 2
, Fig
ure
2
(a)
In a
sim
ple
circ
uit,
a D
C m
otor
is p
ower
ed fr
om a
DC
vol
tage
sou
rce
(b)
The
cur
rent
whi
ch fl
ows
in th
is s
impl
em
otor
circ
uit w
ill b
e ap
prox
imat
ely
the
sam
e as
if th
e m
otor
was
rep
lace
d by
an
equi
vale
nt r
esis
tanc
e an
d vo
ltage
sou
rce
App
lied
volta
ge(V
)
Arm
atur
ere
sist
ance
(R)
Bac
kE
MF
RE
MF
Bac
kV
I−
≈
App
lied
volta
ge
Sim
ple
DC
Mot
or
AR
TIC
LE 2
, Fig
ure
3
(a)
Unr
ectif
ied
AC
wav
efor
msh
owin
g a
zero
ave
rage
leve
l
Tim
e
Voltage 0 V
olt
(b)
Typ
ical
DC
C w
avef
orm
show
ing
a ze
ro a
vera
ge le
vel
Tim
e
Voltage 0 V
olt
(c)
Typ
ical
DC
C w
avef
orm
show
ing
a po
sitiv
e av
erag
e le
vel
Tim
e
Voltage
0 V
olt
(d)
Typ
ical
DC
C w
avef
orm
show
ing
a ne
gativ
e av
erag
e le
vel
Tim
e
Voltage0
Vol
t
AR
TIC
LE 2
, Fig
ure
4
Tra
in C
ontr
olle
r C
ard
#1
PC
Tra
in C
ontr
olle
r C
ard
#n
PW
M /
DC
Con
trol
ler
#1P
WM
/ D
CC
ontr
olle
r #2
Rel
ayD
river
sP
oint
Mot
orD
river
s
PW
M /
DC
Con
trol
ler
#1P
WM
/ D
CC
ontr
olle
r #2
Rel
ayD
river
sP
oint
Mot
orD
river
s
Tra
in C
ontr
olle
r C
ard
#2
PW
M /
DC
Con
trol
ler
#1P
WM
/ D
CC
ontr
olle
r #2
Rel
ayD
river
sP
oint
Mot
orD
river
s
Ser
ial D
ata
Out
(Eas
t)
Ser
ial D
ata
In(W
est)
1001
1010
100…
.
Wes
t
Wes
t
Wes
t
Eas
t
Eas
t
Eas
t
AR
TIC
LE 3
, Fig
ure
1
0 V
olt
0 V
olt
22k
22k
22k
22k
22k
22k 22k
22k
22k
22k
22k
74 HC 595
4 5 6 7 15 1 2 3
1610
+5
813
74 HC 595
4 5 6 7 15 1 2 3
1610
+5
813
Out
put R
ing
Ser
ial D
ata
Clo
ckO
utp
ut
Clo
ckIn
pu
t
Co
mm
and
Dat
a In
pu
t
Sto
reC
omm
and
14 11 12 9
14 11 12 9
1k0
Vol
t
C2
0.1
uF
C1
0.1
uF
1k 0 V
olt
C4
0.1
uF
C3
0.1
uF
Tria
ngle
wav
efor
m
Tria
ngle
wav
efor
m
Buf
fere
dC
lock
AaD
IC18
IC20
IC14
IC15
IC15
13
46
32
R1
- R
22
R23
- R
44
R45
R48
14
7+5
0 V
olt
-+
1k8
3 2 12 13
1 14
IC19
IC19
4
+18
11-1
2
100R
+8
GS D
Pow
er#1
T3
MJE
3055
T
T1
IRF
951
0
D1
1N 5
397
D2
1N 5
397
+16
V75
R46
R47
-+
T2
2N 3
904
-+
1k8
5 6 10 9
7 8
IC19
IC19
100R
+8
GS D
Pow
er#2
T6
MJE
3055
T
T4
IRF
951
0
D3
1N 5
397
D4
1N 5
397
+16
V75
R49
R50
-+
T5
2N 3
904
TL
074
IC19
IC19
AR
TIC
LE 3
, Fig
ure
2
22k 22k 22k
22k 22k 22k
22k 22k 22k
22k
22k
22k
22k
22k
22k 22k
22k
22k
22k
22k
22k 22k 22k
22k 22k 22k
22k 22k 22k
22k
22k
22k
22k
74 H
C 5
97
2k2
2M2
0.1 uF
2k2
2M2
2k2
2M2
2k2
2M2
2k2
2M2
0.1 uF
0.1 uF
0.1 uF
0.1 uF
GP
Inp
ut
#5G
P In
pu
t #4
GP
Inp
ut
#3G
P In
pu
t #2
GP
Inp
ut
#1
*Cut Out Tripped
*Block #10 Detect
*Block #9 Detect
74 H
C 5
97*Block #8 Detect
*Block #7 Detect
*Block #6 Detect
*Block #5 Detect
*Block #4 Detect
*Block #3 Detect
*Block #2 Detect
*Block #1 Detect
+5
0 V
olt
+5
151
23
45
67
10 16
10 16
56
74
32
115
1411
1312
914
1113
129
Sto
reC
omm
and
Lat
ched
Dat
a In
pu
tL
atch
edD
ata
Ou
tpu
tB
uffe
red
Clo
ck
Lat
ch E
dg
eIn
pu
tL
atch
Ed
ge
Ou
tpu
t
0 V
olt
80
Vol
t
8
bBC
c
IC11
IC9
IC14
IC14
1488
IC15
1489
IC15
IC16
IC16
IC16
54
61
2
3
10 98
108
12,1
311
13 11
4,5
6
Pol
l Com
man
d
Buf
fere
d La
tch
Edg
e
R51
- R
55
R56
- R
60
C5
- C
9
+12
-1214 1
7
AR
TIC
LE 3
, Fig
ure
3
0 V
olt
+5
+18
D11
1 -
D12
01N
400
7
RL1
11 -
RL1
20D
irect
ion
Sel
ect
Rel
ay (
24V
coi
l)
RL1
01 -
RL1
10P
ower
Sel
ect
Rel
ay (
24V
coi
l)P
ower
#2
Pow
er#1
D10
1 -
D11
01N
539
7
22k
10k
33k
0 V
olt
10k 0 V
olt
T10
1 -
T11
02N
390
6(o
r B
C 5
59)
T11
1-
T12
02N
390
4(o
r B
C 5
49)
(Not
e th
at th
is c
ircui
t is
repe
ated
10
times
,on
ce fo
r ea
ch b
lock
)
*Blo
ck #
n D
etec
t
Po
wer
fee
dto
tra
ck s
ecti
on
#n
R10
1 -
R11
0
R11
1 -
R12
0
R13
1 -
R14
0
R14
1-
R15
0
R12
1 -
R13
0
33k
AR
TIC
LE 3
, Fig
ure
4
Not
e: A
sim
plem
ente
d, th
eso
ftwar
e as
sum
esth
at R
L-10
1-R
L110
defa
ult t
o P
ower
#2
whe
n th
e re
lay
isno
t ene
rgis
ed. T
heso
ftwar
e ca
n be
sim
ply
adap
ted
ifyo
u ch
oose
Pow
er#1
as
the
defa
ult
how
ever
, all
trai
nco
ntro
ller
card
s in
a sy
stem
sho
uld
bew
ired
the
sam
ew
ay
8
0 V
olt
8
0 V
olt
8
0 V
olt
8
0 V
olt
8
0 V
olt
8
0 V
olt
99
99
99
ULN
200
3
Section 1, SupplySection 1, DirectionSection 2, SupplySection 2, DirectionSection 3, SupplySection 3, DirectionSection 4, Supply
ULN
200
3
Point 1, SetPoint 1, ResetPoint 2, SetPoint 2, ResetPoint 3, SetPoint 3, ResetNot Connected
ULN
200
3
Section 4, DirectionSection 5, SupplySection 5, DirectionSection 6, SupplySection 6, DirectionSection 7, SupplyNot Connected
ULN
200
3
Point 4, SetPoint 4, ResetPoint 5, SetPoint 5, ResetPoint 6, SetPoint 6, ResetPoint 7, Set
ULN
200
3
Section 7, DirectionSection 8, SupplySection 8, DirectionSection 9, SupplySection 9, DirectionSection 10, SupplySection 10, Direction
ULN
200
3
Point 7, ResetPoint 8, SetPoint 8, ResetPoint 9, SetPoint 9, ResetPoint 10, SetPoint 10, Reset
74 H
C 5
9574
HC
595
74 H
C 5
9574
HC
595
74 H
C 5
95
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
1
2
3
4
5
6
7
16
15
14
13
12
11
10
1
2
3
4
5
6
7
16
15
14
13
12
11
10
1
2
3
4
5
6
7
16
15
14
13
12
11
10
1
2
3
4
5
6
7
16
15
14
13
12
11
10
1
2
3
4
5
6
7
16
15
14
13
12
11
10
1
2
3
4
5
6
7
16
15
14
13
12
11
10
1
2
3
4
5
6
7
8
9
10
11
12
13
15
16
17
18
19
20
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
+5
16 10
+5
16 10
+5
16 10
+5
16 10
+5
16 10
0 V
olt
814
1112
98
1411
129
814
1112
98
1411
129
1313
1313
138
1411
129
76
54
32
115
76
54
32
115
76
54
32
115
76
54
32
115
76
54
32
115
+24
Vol
t
Poi
nts
Sup
ply
+24
Vol
t
Poi
nts
Sup
ply
+24
Vol
t
Poi
nts
Sup
ply
Buf
fere
dC
lock
Sto
reC
omm
and
Out
put R
ing
Ser
ial D
ata
Co
mm
and
Dat
a O
utp
ut
14
21
d
IC1
IC2
IC3
IC4
IC5
IC6
IC7
IC8
IC10
IC12
IC13
IC14
9,10 8
AR
TIC
LE 3
, Fig
ure
5
Res
et
Poi
nts
0 V
olt
D20
1 -
D22
01N
400
7
Poi
nt n
Set
/ R
eset
Poi
nts
Sup
ply
100R
10k
T20
1 -
T22
0M
JE29
55T
(Not
e th
at th
is c
ircui
t is
repe
ated
20
times
,on
ce fo
r ea
ch p
oint
mot
or s
olen
oid)
R22
1 -
R24
0
R20
1 -
R22
0
Poi
nt M
otor
Sol
enoi
d
AR
TIC
LE 4
, Fig
ure
1
+
C14
1000
uF
25V
LM 3
17In
3k0Adj
Out
220R
C11
47 u
F25
V+18
0 V
olt
C10
0.1
uF
+24V
Inp
ut
0 V
olt
Inp
ut
+24
+
+5
LM 3
17In
Adj
Out
220R
C13
1000
uF
25V+
16V
75
+
LM 3
17In
1k2Adj
Out
220R
+8
T7
2N 3
906
(or
BC
559
)
T9
2N 3
904
(or
BC
549
)
+C
1210
uF
5V
10k
Pow
er o
verlo
adre
set s
witc
h (N
C)
1k8
22k 10k 0 V
olt
1k
2R 5W
LED
1
D5
1N 5
397
0 V
olt
2k7
10k
D6
1N 4
148
*Cut
Out
Trip
ped
T8
IRF
951
0
+12V
Inp
ut
-12V
Inp
ut
-12
+5V
Inp
ut
+5
PC
po
wer
sup
ply
wit
h 2
4V
+12
R62
R61
R73
R72
R75
R74
R66
R68
R65
R64
R69
R63
VR
1
IC25
IC22
IC23
100R
R67
GS D
E
g
+
C15
2500
uF
25VG
Poi
nts
Sup
ply C16
10,0
00 u
F35
V
0 V
olt
Poi
nts
0 V
olt
F
LM 3
17In
Adj
Out
IC24
D7
1N 5
397
2k2
LED
2
R70
2R 1W
R71
D8
1N 4
007
ef
ncnc
+D
91N
400
7
AR
TIC
LE 4
, Fig
ure
2
AR
TIC
LE 4
, Fig
ure
3
-+10 9
80
Vol
tIC
17
-+5 6
70
Vol
tIC
174
+12
11
-12
12
-+27
0k
3 21
C17
0.1
uF
10k 8k2
33k
6k8
-+13
14
+5
0 V
olt
0 V
olt
Tria
ngle
wav
efor
m
0.2
Vol
t
5.2
Vol
t f=45
Hz
IC17
IC17
TL
074
R76
R77
R78
R79
R80
+5
IC1611
14
7
0 V
olt74
HC
00
13 12+
5
74H
C12
3
IC21
0 V
olt
16
8
+5 S
tore
Com
man
d
Res
et
C18
47 u
F
+14 2
3
13 4
R81
470k
15
110
74H
C12
3
IC21
0 V
olt
+5
6
11
5 12
7
9
“Wes
t”d
ata
po
rt
“Eas
t”d
ata
po
rt
D0
(pin
2)
IC30
02
3
D1
(pin
3)
12,1
311
D2
(pin
4)
4,5
6
S3
(pin
15)
31
S4
(pin
13)
64
S5
(pin
12)
1113
S6
(pin
10)
810
D3
(pin
5)
9,10
8
d c b a D C B A
1kR
300
1kR
301
1kR
302
100R
R30
3
100R
R30
4
100R
R30
5
100R
R30
6
1kR
307
D6
(pin
8)
680R
R30
8LE
D30
0
D7
(pin
9)
680R
R30
9LE
D30
1
0 V
olt
GN
D (
pins
18-
25)
PC
pri
nte
rp
ort
co
nn
ecto
r(m
ale
DB
25)
+5
G
D5
(pin
7)
g
78L0
5In
Com
Out
0 V
olt
IC30
2
C30
00.
1 uF
+12
D30
01N
400
7
T30
0IR
F 9
510
GS D
10k
T30
12N
390
4(o
r B
C 5
49)
e
10k
R31
1
R31
0
Enc
IC30
1
IC30
1
IC30
0
IC30
014
88IC
301
1489
14 7+5
0 V
olt
14 1+12 -12
70
Vol
t
Fnc
f-1
2
AR
TIC
LE 4
, Fig
ure
4
Res
isto
rla
dder
s(D
to A
)
Dire
ctio
nR
elay
10
Dire
ctio
nR
elay
9
Dire
ctio
nR
elay
8
Dire
ctio
nR
elay
7
Dire
ctio
nR
elay
6
Dire
ctio
nR
elay
5
Dire
ctio
nR
elay
4
Dire
ctio
nR
elay
3
Dire
ctio
nR
elay
2
Dire
ctio
nR
elay
1
Sup
p R
ly 1
0
Sup
p R
ly 9
Sup
p R
ly 8
Sup
p R
ly 7
Sup
p R
ly 6
Sup
p R
ly 5
Sup
p R
ly 4
Sup
p R
ly 3
Sup
p R
ly 2
Sup
p R
ly 1
Block Detect circuits
ULN2003 ULN2003 ULN2003 ULN2003 ULN2003 ULN2003
74HC595 74HC595 74HC595 74HC597 74HC595 74HC595
74HC595 TL074 TL074 74HC00
Track and points connectors
Vol
tage
cont
rol
com
pone
nts
(FE
Ts,
tran
sist
ors)
Oscillatorcomponents
Pow
er In
put
Con
nect
ors
Poi
nts
Sup
ply
16.7
5 V
olt
Reg
ulat
or
8 V
olt
Reg
ulat
or
“East” Data
“West” Data
Res
isto
rla
dder
s(D
to A
)
74HC597
74HC595
IC1
IC2
IC3
IC4
IC5
IC6
IC7
IC8
IC9
IC10
IC11
IC12
IC13
IC16
IC17
IC18
IC19
IC20
Ove
rload
Cut
Out
Circ
uit
18 V
olt
Reg
ulat
or
1489
IC15 1488
IC14
AR
TIC
LE 5
, Fig
ure
1
74HC123
IC21
Wires from PCparallel port
1488
IC30
0
1489
IC30
1
Ser
ies
resi
stor
s
LED
300
LED
301
Pow
ersu
pply
com
pone
nts
“East” Data
“West” DataA
RT
ICLE
5, F
igur
e 2
2N 3
904
(BC
549
)E
B
C
2N 3
906
(BC
559
)E
B
C
LM31
7
Adj
Out
In
MJE
3055
B
C
E
IRF
9510
IRF
9530
G
D
S
MJE
2955
B
C
E
AR
TIC
LE 5
, Fig
ure
3
Unk
now
nT
rans
isto
r?
?
?
+-
Unk
now
nT
rans
isto
r?
?
?
-+
Unk
now
nT
rans
isto
r?
?
?
+-
Unk
now
nT
rans
isto
r?
?
?
-+
Unk
now
nT
rans
isto
r?
?
?
+-
Unk
now
nT
rans
isto
r?
?
?
-+
Unk
now
nT
rans
isto
r?
B
?
In th
is c
ase,
the
unkn
own
tran
sist
oris
an
NP
N ty
pe
AR
TIC
LE 5
, Fig
ure
4
AR
TIC
LE 5
, Fig
ure
5
Gai
n te
stin
g ci
rcui
t
+9 0 V
olt
220R
10k
220R
+9
0 V
olt
Mea
sure
V
Mea
sure
V270R270R 10k
Par
alle
l Por
t Ada
pter
card
Com
man
dD
ata
Out
put
Com
man
dD
ata
Inpu
t
Latc
hed
Dat
aO
utpu
t
Latc
hed
Dat
aIn
put
Latc
hE
dge
Out
put
Latc
hE
dge
Inpu
t
Clo
ckIn
put
Clo
ckO
utpu
t
Low
er c
ase
pins
(Eas
t)U
pper
cas
e pi
ns(W
est)
To
PC
’s p
aral
lel p
ort
AR
TIC
LE 6
, Fig
ure
1
Par
alle
l Por
t Ada
pter
card
Tra
inC
ontr
olle
r#1
Tra
inC
ontr
olle
r #
n
Com
man
dD
ata
Out
put
Com
man
dD
ata
Inpu
t
Com
man
dD
ata
Out
put
Com
man
dD
ata
Inpu
t
Com
man
dD
ata
Inpu
t
Com
man
dD
ata
Out
put
Latc
hed
Dat
aO
utpu
t
Latc
hed
Dat
aIn
put
Latc
hed
Dat
aIn
put
Latc
hed
Dat
aO
utpu
t
Latc
hed
Dat
aO
utpu
t
Latc
hed
Dat
aIn
put
Latc
hE
dge
Out
put
Latc
hE
dge
Inpu
t
Latc
hE
dge
Out
put
Latc
hE
dge
Inpu
t
Latc
hE
dge
Inpu
t
Latc
hE
dge
Out
put
Clo
ckIn
put
Clo
ckIn
put
Clo
ckIn
put
Clo
ckO
utpu
t
Clo
ckO
utpu
t
Clo
ckO
utpu
t
Low
er c
ase
pins
(Eas
t)
Low
er c
ase
pins
(Eas
t)
Low
er c
ase
pins
(Eas
t)
Upp
er c
ase
pins
(Wes
t)
Upp
er c
ase
pins
(Wes
t)
Upp
er c
ase
pins
(Wes
t)
To
PC
’s p
aral
lel p
ort
AR
TIC
LE 6
, Fig
ure
2
Buf
fere
d C
lock
Buf
fere
dLa
tch
Edg
e
Latc
h R
elay
/ P
oint
Mot
orst
ates
on
risin
g ed
ge o
fB
uffe
red
Latc
h E
dge
(Buf
fere
d C
lock
low
)
Pol
l sta
tus
inpu
ts o
n fa
lling
edge
of B
uffe
red
Latc
h E
dge
(Buf
fere
d C
lock
hig
h)
Shi
ft bo
th in
put a
nd o
utpu
tda
ta th
roug
h th
e sh
ift r
egis
ters
on r
isin
g ed
ge o
f Buf
fere
d C
lock
(Buf
fere
d La
tch
Edg
e lo
w)
AR
TIC
LE 6
, Fig
ure
3
Blo
ck 1
Blo
ck 2
Blo
ck 3
Blo
ck 4
Blo
ck 5
Blo
ck 6
Blo
ck 7
Blo
ck 8
Blo
ck 9
Blo
ck 1
0
Poi
nt 1
Poi
nt 2
Poi
nt 3
Poi
nt 4
Poi
nt 5
Poi
nt 6
Poi
nt 7
AR
TIC
LE 7
, Fig
ure
1
“Cen
tre”
of b
lock
“Cen
tre”
of b
lock
“Cen
tre”
of b
lock
Blo
ck b
ound
arie
s
Blo
ck b
ound
arie
sB
lock
bou
ndar
ies
Blo
ck b
ound
ary
AR
TIC
LE 7
, Fig
ure
2
AR
TIC
LE 7
, Fig
ure
3
Thi
s pr
esen
ce o
f thi
s se
t of p
oint
s w
ould
cau
se th
is b
lock
to h
ave
two
“cen
tres
” an
d is
not
sup
port
ed b
y th
e ex
ampl
e so
ftwar
e.
But
this
arr
ange
men
t of t
rack
can
be
supp
orte
d if
an a
dditi
onal
bloc
k bo
unda
ry is
cut
at t
his
posi
tion,
cre
atin
g tw
o in
depe
nden
t blo
cks
Cen
tre
“A”
Cen
tre
“B”
Bou
ndar
y to
“Blo
ck 8
”
AR
TIC
LE 7
, Fig
ure
4
“Cen
tre”
of “
Blo
ck 5
”
Bou
ndar
y to
“Blo
ck 1
”B
ound
ary
to“B
lock
2”
Bou
ndar
y to
“Blo
ck 3
”B
ound
ary
to“B
lock
4”
Bou
ndar
y to
“Blo
ck 6
”
Bou
ndar
y to
“Blo
ck 7
”
Poi
nt 1
Poi
nt 2
Poi
nt 3
Poi
nt 4
Poi
nt 5
Par
alle
l Por
t Ada
pter
card
Wes
t(U
pper
cas
e pi
ns)
Eas
t(L
ower
cas
e pi
ns)
To
PC
’s p
aral
lel p
ort
AR
TIC
LE 8
, Fig
ure
1
Dat
a flo
ws
Clo
ck fl
owD
ata
flow
sC
lock
flow
Wes
t
Wes
t
Eas
tE
ast
Tra
inC
ontr
olle
r#1
Tra
inC
ontr
olle
r#2
Tra
ck B
lock
s: 1
- 1
0P
oint
s: 1
- 1
0P
ower
Sup
plie
s: 1
- 2
Ove
rload
indi
cato
r: 1
GP
Inpu
ts: 1
- 5
Tra
ck B
lock
s: 1
1 -
20P
oint
s: 1
1 -
20P
ower
Sup
plie
s: 3
- 4
Ove
rload
indi
cato
r: 2
GP
Inpu
ts: 6
- 1
0
Wes
t
Eas
t
Tra
inC
ontr
olle
r#3
Tra
ck B
lock
s: 2
1 -
30P
oint
s: 2
1 -
30P
ower
Sup
plie
s: 5
- 6
Ove
rload
indi
cato
r: 3
GP
Inpu
ts: 1
1 -
15
AR
TIC
LE 8
, Fig
ure
2
The
lead
ing
and
trai
ling
axle
s sh
ould
be
fitte
d w
ith a
res
isto
r so
that
the
carr
iage
can
be e
asily
det
ecte
d by
the
softw
are.
Glu
e a
surf
ace
mou
nt r
esis
tor
(app
rox
10-2
0k)
to th
e ax
le o
f a M
etal
Whe
el c
ar
Dra
w tr
aces
of c
ondu
ctiv
e in
k be
twee
nth
e re
sist
or a
nd th
e m
etal
ic p
arts
of e
ach
whe
el.
Par
alle
l Por
tC
omm
unic
atio
nM
anag
emen
t
Tra
inC
ontr
olT
rain
Con
trol
Tra
inC
ontr
olE
ngin
eC
ontr
ol
Infr
astr
uctu
reM
anag
emen
t
Par
alle
l Por
t & T
rain
Con
trol
ler
Car
ds
Tim
ekee
per
Ser
ial d
river
s,co
mm
and
disp
atch
,st
atus
sca
nnin
g
Poi
nts,
pow
er s
uppl
ies,
trac
k bl
ocks
One
con
trol
ler
per
trai
n
AR
TIC
LE 9
, Fig
ure
1
Por
t Driv
erP
roce
ss
Par
alle
l Por
t
Sta
tus
Sca
nner
Pro
cess
Dis
patc
her
Pro
cess
Req
uest
sca
nnin
gof
the
inpu
t rin
g,LE
D s
tate
msg
s
Sca
nned
inpu
t rin
gva
lues
New
sta
teof
the
outp
ut r
ing,
LED
sta
te m
sgs
Mas
ter
Con
trol
ler
Pro
cess
Poi
nts
Pro
cess
Poi
nts
Pro
cess
Poi
nts
Pro
cess
Poi
nts
Pro
cess
Pow
er P
roce
ssP
ower
Pro
cess
Pow
er P
roce
ssP
ower
Pro
cess
Poi
nt s
ettin
gre
ques
tsP
ower
setti
ngre
ques
ts
Blo
ck o
wne
rshi
pre
ques
ts &
conf
irmat
ions
Pow
er P
roce
ssP
ower
Pro
cess
Pow
er P
roce
ssE
ngin
eer
Pro
cess
Tim
eK
eepe
r
Poi
nts
setti
ngre
ques
ts
Pow
er s
ettin
gre
ques
ts &
ack
s
Blo
ck s
tate
chan
geno
tific
atio
ns
The
mes
sage
logg
er is
link
edto
eve
ry p
roce
ss
Message Logger Process
AR
TIC
LE 9
, Fig
ure
2
Pro
gra
mm
able
Po
wer
Su
pp
ly O
utp
ut
02468101214
0
2
4
6
8
10
12
14
16
18
20
22
24
26
28
Sp
eed
Set
ting
Average Driving Voltage
AR
TIC
LE 9
, Fig
ure
3
02468
10
12
14
Tim
e
Voltage
AR
TIC
LE 9
, Fig
ure
4
