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Transcript of Janusz Rajski Nilanjan Mukherjee Mentor Graphics Corporation Janusz Rajski Nilanjan Mukherjee Mentor...
Janusz RajskiJanusz Rajski
Nilanjan MukherjeeNilanjan MukherjeeMentor Graphics CorporationMentor Graphics Corporation
Janusz RajskiJanusz Rajski
Nilanjan MukherjeeNilanjan MukherjeeMentor Graphics CorporationMentor Graphics Corporation
Presenters: Janusz Rajski Nilanjan Mukherjee
Mentor Graphics [email protected]
Co-author: Jerzy Tyszer Poznan Univ. of Technology
Presenters: Janusz Rajski Nilanjan Mukherjee
Mentor Graphics [email protected]
Co-author: Jerzy Tyszer Poznan Univ. of Technology
Presenters and authorsPresenters and authors
Tutorial ground rulesTutorial ground rules
Definition: Embedded Test refers to design-for-testability techniques where testing is accomplished entirely or partially through on-chip hardware.
Disclaimer:
This tutorial is not intended to endorse or discredit any commercial technology or product.
AudienceAudience
Designers of complex integrated circuits IP core providers and integrators Test engineers EDA tools developers EDA tools users Researchers Project managers
Designers of complex integrated circuits IP core providers and integrators Test engineers EDA tools developers EDA tools users Researchers Project managers
Everybody interested in state-of-the-art embedded test technology, to reduce the cost of manufacturing test
In particular:
Everybody interested in state-of-the-art embedded test technology, to reduce the cost of manufacturing test
In particular:
Tutorial objectivesTutorial objectives
To present: Compelling reasons for ET adoption Common barriers for ET adoption State-of-the-art ET fundamentals and practice Architectures for logic and memory BIST Embedded deterministic techniques At-speed ET
• multiple-clock domain designs• multi-frequency designs
Tools for BIST synthesis automation Application examples and case studies
OutlineOutline
Introduction Embedded stimuli generators Compactors of test responses Logic BIST Deterministic forms of embedded test Embedded at-speed test Comparison of scan/ATPG, logic BIST and
embedded forms of deterministic test BIST schemes for embedded memory arrays Summary of embedded test
Design characteristicsDesign characteristics
CPU coreCPU core
MemoryMemory
ASICASIC
ASICASIC
ASICASIC
PLLPLL
IP coreIP core
DSP coreDSP core
MemoryMemory
IP coreIP core
MemoryMemory
MemoryMemory
MemoryMemory
ASICASIC
AnalogAnalogI / 0I / 0
System on Chip characteristicsSystem on Chip characteristics
CPU coreCPU core
MemoryMemory
ASICASIC
ASICASIC
ASICASIC
PLLPLL
IP coreIP core
DSP coreDSP core
MemoryMemory
IP coreIP core
MemorMemoryy
MemoryMemory
MemoryMemory
ASICASIC
AnalogAnalogI / 0I / 0
System architecture Microprocessors, DSP cores Buses, peripherals, memory ASIC portion
Structures: Logic, memory, analog Multiple embedded memories:
DRAM, Flash, CAM Analog and mixed signal: PLLs,
clock recovery Field programmable logic RF cores: wireless receivers IP cores and reusable blocks
available from multiple vendors Design efficiency achieved by
hierarchical core-based design style
New defectsNew defects
Geometries shrink at 30% every three years Defect sizes do not shrink in proportion Increase of wiring levels from 6 to 9 Interconnect delays dominate Gate delays reduced Bridging faults
[Sematech, 1998]
Sematech S-121Sematech S-121
“Test Method Evaluation –Key Findings & Conclusions”
Objective: Evaluate various test methodologies
• Large sample size• Extensive data collection & analysis
Sematech S-121Sematech S-121
Device 116K equivalent gates 0.45 µm L effective (0.8 µm drawn) 50 MHz operating speed 249 signal I/Os 3 metal levels Full LSSD Scan plus JTAG boundary scan
• 8 Chains, 5,280 master/slave LSSD latches (10,560 total latches)
Sample size 20,000 units Test methods:
• Stuck-at faults, Functional tests, Transition delay faults & IDDQ
Sematech S-121Sematech S-121
SAF - 99.5% coverage (8300 patterns)
FUNC - 52% SAF coverage (532K cycles)
IDDQ - >96% pseudo SAF coverage(195 patterns)
Delay - 90% Transition coverage (15232 patterns)
IDDQ1463
FUNC6
78
1 1251
13
SAF6
0 52
Delay 14
34
36
FUNC
IDDQ
1
Package test results (pre Burn-in)
S-121 ConclusionsS-121 Conclusions
All test methods detected unique defects Near 100% SAF coverage missed many defects Large defect coverage overlap between SAF & Delay
• SAF are a subset of Transition faults IDDQ threshold setting significantly affects yield
• 98% of the IDDQ fails survived burn-in Many (bridging) defects detected only by IDDQ
• But diminishing IDDQ effectiveness in DSM Some Functional tests are still required Opportunity to optimize test coverage levels & capital
BridgeM1-2
Bridge M2
Bridge M4Break trans
Bridge Poly M2
Bridge M3Bridge M1-3
Bridge poly M1
Bridge M3-4
Open PolyOpen Contact
Bridge M1
Unknown BrBreak M3
Bridge Poly M2
Break M2
Bridge M3-4
Break M1Bridge Poly M4
Bridge Poly
Unknown
Via break
Defect Pareto 350 nm
Al4-5 Levels
OxideDielectric
W Plugs
350 nm Process 5 million Transistors
A Transistor
Process Shrinks vs. Defect TypesProcess Shrinks vs. Defect Types
Defect distribution change with process
100 nm Process -- 250 million transistors
A Transistor
Cu (8 Levels)
Low-KDielectric
CuPlugs
Unknown
Defect Pareto 100 nm
??
Process Shrinks vs. Defect TypesProcess Shrinks vs. Defect Types
Defects vs. Fault CoverageDefects vs. Fault Coverage
[M. Rodgers , et. al. DAC 2000]
1 10 100 1000 K-Ohms
.18 um
.25 um
Test chip FA results
Increasing defect populations causingmore VDD, Temp, & freq sensitive device fails
Bridge Defect Observed Resistance
Wired “AND” & “OR” models are not sufficient
Speed limiting defects Frequency of bridging defects
is increasing Need to drive ATE & modeling
requirements from the defects to be detected
Will drive need for more scan vectors
Quality requirementsQuality requirements
YY 1 - Y1 - Y
pp
1 - p1 - p
shipment
shipment
FaultsFaultsdetecteddetected
Escapes
Quality requirementsQuality requirements
0
0.001
0.002
0.003
0.004
0.005
0.006
0.007
0.008
0.009
0.01
0.990 0.991 0.992 0.993 0.994 0.995 0.996 0.997 0.998 0.999 1.000pp
Yield = 0.1Yield = 0.1
Yield = 0.9Yield = 0.9
Escapes = (1 - Y)(1 - p)Escapes = (1 - Y)(1 - p)
Fault modelsFault models
Stuck-at-0 and stuck-at-1 Transitions Path delay Multiple detects VDD
Very high test qualityVery high test quality
Very high fault coverage Wide range of fault models
• stuck-at • transition• path delay• at-speed testing • multiple detects• bridging• defect based• cross-talk effects• ... fading IDDQ
CoverageCoverage
EscapesEscapes
High-performance MPU/ASIC gate countHigh-performance MPU/ASIC gate count
0
50
100
150
200
250
300
2001 2002 2003 2004 2005 2006 2007
ITRS Roadmap 2001ITRS Roadmap 2001
Gate countGate count
Scan chainsScan chains
The pattern count for transition faults may reach 20,000
Scan testScan test
ATEATE
Sca
n in
put
Sca
n in
put
chan
nels
chan
nels
Primary outputsPrimary outputs
Sca
n ou
tput
Sca
n ou
tput
chan
nels
chan
nels
Primary inputsPrimary inputs
ATE costATE cost
Tester cost = b + Tester cost = b + m p m p
b - base cost (zero pins)b - base cost (zero pins)
m - incremental cost per pinm - incremental cost per pin
p - number of pinsp - number of pins
High performanceHigh performanceASIC / MPUASIC / MPU
DFT testerDFT tester
Low performanceLow performanceMicrocontrollerMicrocontroller
250 - 400250 - 400
100 - 350100 - 350
200 - 350200 - 350
2700 - 60002700 - 6000
150 - 650150 - 650
1200 - 25001200 - 2500
512512
512 - 2500512 - 2500
256 - 1024256 - 1024
b [ K$ ]b [ K$ ] m [ $ ]m [ $ ] pp
Test cost can be Test cost can be
$0.05/second$0.05/second
Volume of scan test dataVolume of scan test data
Test cyclesTest cycles = = PatternsPatternsScan cellsScan cells
Scan chainsScan chains
......
Scan test timeScan test time
Test timeTest time = =Scan cellsScan cells
Scan chainsScan chains
......
FrequencyFrequencyPatternsPatterns
Scan test costScan test cost
Shift frequencyShift frequency 20 MHz20 MHz
Gate countGate count 10M10M
Scan chainsScan chains 3232
Padding ratioPadding ratio 1.41.4
Scan patternsScan patterns 20K20K
Vector memoryVector memory 64MV64MV
Reload penaltyReload penalty 2s2s
InsertionsInsertions 44
Tester rateTester rate 0.05$0.05$
Scan cellsScan cells500,000500,000
Cells per scanCells per scan15,62515,625
Longest scan chainLongest scan chain21,87521,875
CyclesCycles437.5M437.5M
Scan test timeScan test time21.9s21.9s
PassesPasses66
Reload timeReload time12.0s12.0s
Time pre deviceTime pre device87.5s87.5s
Cost per deviceCost per device4.4$4.4$
MoreMoreMoreMore
High-performance MPU/ASICHigh-performance MPU/ASIC
0
2
4
6
8
10
12
2001 2002 2003 2004 2005 2006 2007
32 channels32 channels
20,000 patterns20,000 patterns
Required ATE memoryRequired ATE memory
Gigabits/channel Gigabits/channel
High-performance MPU/ASICHigh-performance MPU/ASIC
0
20
40
60
80
100
120
2001 2002 2003 2004 2005 2006 2007
100 MHz scan shift100 MHz scan shift
Scan test timeScan test time
seconds seconds
ATE accuracy vs. device speedATE accuracy vs. device speed Tester accuracy will improve from 200 ps to 175 ps by 2012 Tester accuracy will improve from 200 ps to 175 ps by 2012 Clock period will decrease to 330 psClock period will decrease to 330 ps Margin of error for ATE approaches 50% clock periodMargin of error for ATE approaches 50% clock period
0
100
200
300
400
500
600
2001 2002 2003 2004 2005 2006 2007
Device periodDevice period
ATE accuracyATE accuracy
AccuracyAccuracyrequiredrequired
Requirements for Embedded TestRequirements for Embedded Test
Increasing device complexity, operating speed, Increasing device complexity, operating speed, and new fault models stress conventional scan and new fault models stress conventional scan based test:based test:
• Exploding volume of test dataExploding volume of test data• Increasing scan test time, andIncreasing scan test time, and• Escalating scan test costEscalating scan test cost
Embedded Test is required to:Embedded Test is required to:• Generate most of the test data on-chipGenerate most of the test data on-chip• Compacting test responses on-chip, andCompacting test responses on-chip, and• Providing on-chip control for at-speed testProviding on-chip control for at-speed test
Very low costVery low cost
Dramatically reduced volume of test data (10-100X) Dramatically reduced scan test time (10-400X)
ATE Memory [Mvectors]
0
5
10
15
20
25
30
35
0 1 2 3 4 5 6 7
1010XX
10X10X
Scan test time[s]Scan test time[s]
2M gates2M gatesScan/ATPGScan/ATPG
16 scan chains16 scan chains5k vectors5k vectors2s handler/index time2s handler/index time1 test 1 test 10MHz scan shift10MHz scan shift
Long term scalabilityLong term scalability
0.1
1
10
100
0 1.5 3 4.5 6 7.5 9 10.5
100X increase in 10 years!
Volume in conventional DFT
yearsyears
0.1
1
10
100
0 1.5 3 4.5 6 7.5 9 10.5
Radical compression is required!Radical compression is required!
Immediate 5-10X compression
Compression ahead of volume for 10 years Volume in Volume in
conventional DFTconventional DFT
Compression factorCompression factor
yearsyears
0.1
1
10
100
0 1.5 3 4.5 6 7.5 9 10.5
Radical compression is requiredRadical compression is required
Compression should be ahead of Moore’s law for 10 years! Volume in Volume in
conventional DFTconventional DFT
Compression factorCompression factor
Compressed Compressed volumevolume
yearsyears