ISSCC 2007 SESSION 28/1IMAGE SENSORS 28 - Stanford University
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ISSCC 2007 / SESSION 28/1IMAGE SENSORS / 28.3 28.3 A Per-Pixel Pulse-FM Background Subtraction reduces sensitivity to power supply noise. To achieve high lineari- Circuit with 175ppm Accuracy for Imaging ty in the subtracted current, only the pulse frequency is varied, Applications with the pulse width and bias current held constant. An alternate current path through M3 is provided when M2 is off to steer the Ml current to node VB, reducing transients on Ml's drain. While VB Sam: Kavusil 2, Kunal Ghoshl, Abbas El Gamnall should normally be held at the detector node voltage, it is connect- ed to GND instead so that M2 operates in subthreshold, thereby 'Stanford University, Stanford, CA adding a leakage current of around lpA to emulate the high IR 'Robert Bosch Research and Technology Center, Palo Alto, CA detector dark current. As is common in IR readout circuits, the integrator is a capacitive trans-impedance amplifier (CTIA) imple- In many imaging applications the target is obscured by a large mented with a single-stage telescopic cascode amplifier. Fig. 28.3.3 background signal. For example, in infrared (IR) imaging, scenes depicts relevant timing diagrams with the corresponding integra- often have small temperature variations around a much higher tor output. background temperature [1]. In noninvasive in vivo fluorescence imaging, scenes have high background levels due to tissue autoflu- The minimum current subtracted, around 1.3pA, is limited by the orescence caused by the excitation source [2]. Accurately resolving spatial variations of the emulated dark current and corresponds to small-signal variations in the presence of a large background sig- only one pulse in a 23ms integration time. The maximum current nal imposes stringent requirements on the readout circuit, such as subtracted, around lIpA (Ml bias current), is limited by the CTIA necessitating high dynamic range and fine quantization of the total bias. Minimizing GBW variations of the CTIA is critical to reduc- signal. Existing imaging systems mitigate these adverse effects by ing subtracted current variations. Although the BW required of the performing multiple digital read-and-accumulate operations pixel amplifiers is relaxed as in continuous-time AL schemes, GBW which, as pixel count increases, result in lower sensitivity and variation causes a variation of the pedestal charge of M2, which is longer readout times than the background-limited integration designed to be below 1%. time. Addressing these limitations requires a significant increase in pixel readout area [3]. The prototype has been tested and characterized. Fig. 28.3.6 sum- marizes chip characteristics and compares performance with and An alternative approach that overcomes these shortcomings is to without background subtraction. Fig. 28.3.4 compares measured perform analog signal subtraction during integration. Since stan- outputs for pixels with and without background subtraction. The dard AC coupling or differential readout techniques used in other output of the pixel after subtracting 6nA from 6.24nA exhibits a types of sensor interface circuits cannot be used in image sensors, sawtooth pattern due to the periodic charge packet subtraction. several authors have proposed schemes for per-pixel analog back- Fig. 28.3.5 provides histograms of measured noise and nonlineari- ground subtraction [4-8]. The idea is to estimate the background ty before and after background subtraction for the pixel array with photocurrent every few frames and subtract a large fraction of it 200pA background photocurrent incremented by twenty 65fA from each pixel's photocurrent during integration. The functions steps. Subtracting 194pA enables the circuit to resolve a signal hid- needed to estimate the background signal can be readily imple- den within the background with an accuracy of 175ppm at mented as part of the standard camera control module (see Fig. 43frames/sec with a 30-fold increase in effective well capacity. 28.3.1). To implement per-pixel subtraction, a current source Linearity improvement is less than the theoretically achievable biased slightly below the background current is added. This cur- value of 4fA due to the integrator INL, since the signal of interest rent is subtracted from the input photocurrent and the residue is now spans the entire range of the integrator. Furthermore, meas- integrated. Such background subtraction relaxes sensor dynamic urement accuracy is also limited by the light source nonlinearity. range requirements, making it possible to reduce the integrating Measured peak spatial subtracted current variation over the array capacitor size and thus pixel area. It can also reduce the ADC res- is 3%. Temporal and spatial variations reported are at least 17 and olution and frame rate requirements, and improve sensitivity and 5 times lower, respectively, than that obtained by subtracting the linearity. While the shot noise of the subtracted current is added to background by controlling the Ml bias current as in [6]. Since vari- the photocurrent shot noise, the SNR is improved since the integra- ations in the PFM pulse-width directly affect the charge packet tion time can be increased without saturating the capacitor. It can size, linearity and current variations can be further improved by be shown that background subtraction improves well capacity, SNR generating the PFM signal on chip (instead of externally as in this and linearity by factors of up to (1 - cc)-i, (1 - (c')-' and (1 - cc), respec- work). The paper described a 1-D array design. Given the low pixel tively, where 0 < cx < 1 is the fraction of photocurrent subtracted. overhead of our scheme, a 2-D array can be readily designed. The major drawback of current subtraction schemes, however, is high spatial and temporal variations in subtracted current (in the Acknowledgements: 1s 1s rr ~~~~~~~~The authors thank B. Fowler and K. Fife for valuable insights pA to nA range) due to noise and Vt variations. and National Semiconductor for chip fabrication. The work is partially supported by DARPA Grant: N66001-02-1-8940. To surmount these inherent limitations, we propose a per-pixel pulse frequency modulation (PFM) based scheme where charge References: packets controlled by a PFM signal are subtracted from each pixel's [1] G. C. Holst, Electro-optical Imaging System Performance, 2nd Ed., JCD integrator. To validate this scheme, we designed a lx16 pixel array and SPIE, 2000. targeted for bump-bonding with medium and long wave IR HgCdTe [2] J. Mansfield et. alt, "Autofluorescence Removal, Multiplexing, and diodes (see Fig. 28,3,7), The output of each pixel is connected to a Automated Analysis Methods for In Vivo Fluorescence Imaging," J. of S/H circuit, consisting of a dynamically biased PMOS source follow- Biomsedical Optics, vol. 10, issue 4, 41207, pp. 1-9, July/August, 2005. [31 S. Kang, D,. Woo and H Lee, "Multiple Integration Method for High er whose output is connected to a CMOS pass gate and sampling Signal-to-Noise Ratio Readout Integrated Circuit," IEEE Proc. CICC, pp. capacitor, followed by an NMOS source follower compensated for 299-302, Sept., 2004. its body effect (see Fig. 28.3.2). The S/H allows the output of a pixel [41 G. Yang et al., "A High Dynamic-Range, Low-Noise Focal Plane Readout with and without background subtraction to be compared in each for VLWIR Applications Implemented with Current Mode Background frame. The array periphery includes bias and timing circuitry and Subtraction," Proc. SPIE, vol. 3360, pp. 42-51, April, 1998. output drivers. The prototype is fabricated in a 0.18pim CMOS [51 S. Kleinfelder, A. Hottes and R.F.W. Pease, "Focal Plane Array Readout 2P5M process and 3.3V thick gate-oxide transistors are used for Integrated Circuit with Per-Pixel Analog-to-Digital and Digital-to-Analog pixel circuitry. Conversion," Proc. SPIE, vol. 4028, 2000. [61 D.H. Woo, S.G. Kang and H.C. Lee, "Current Mode Background Suppression for 2-D LWIR Applications," IEE Elect. Letters, Vol. 41, No. 5, Each pixel consists of a 3Onmx3Otm NWELL/PSUB diode (used to pp. 221-222, Mar,, 2005. simplify characterizationL) and currenLt source Ml1 conLnected to an [71 C, Hsitch et; al., "High-Performance CMOS Buffered Cate Modulat;ion inltegrator via switch M2 that is conrlLlolled by the PFM signal. The Input (BCMI) Readout Circuits for IR FPA," IEEE J. Solid-Stntte Circui[ts, bias cuLrrent of Ml anLd the PFM signLal pulse-width control the sub- Vol. 33, pp. 1188-1198, Aug., 1998, tracted charge packet size. By selecting a short pulse-width, Ml [SI M, Tepegoz and T, Akin, "A Readout Circuit; for QWIP Infralred Detectzor carL b bise ata rlaivey hghlevl. tslonLg chanLnel lenLgth nzot A3rrayss Using Current Mirroring Inltegrationl," Proc. ESSCIRC, pp. 133- only allows operatioln in strong inversion, which reduces the spatial ' , variations over the array caused by Vt mismatches, but also 504 1 2007 IEEE International Solid-State Circuits Conferenc 1-4244-0852-0/07/$25.00 ©2007 IEEE. Authorized licensed use limited to: Stanford University. Downloaded on March 02,2010 at 14:44:26 EST from IEEE Xplore. Restrictions apply.
Transcript of ISSCC 2007 SESSION 28/1IMAGE SENSORS 28 - Stanford University
ISSCC 2007 / SESSION 28/1IMAGE SENSORS /28.3
28.3 A Per-Pixel Pulse-FM Background Subtraction reduces sensitivity to power supply noise. To achieve high lineari-Circuit with 175ppm Accuracy for Imaging ty in the subtracted current, only the pulse frequency is varied,Applications with the pulse width and bias current held constant. An alternatecurrent path through M3 is provided when M2 is off to steer the Ml
current to node VB, reducing transients on Ml's drain. While VBSam: Kavusil 2, Kunal Ghoshl, Abbas El Gamnall should normally be held at the detector node voltage, it is connect-
ed to GND instead so that M2 operates in subthreshold, thereby'Stanford University, Stanford, CA adding a leakage current of around lpA to emulate the high IR'Robert Bosch Research and Technology Center, Palo Alto, CA detector dark current. As is common in IR readout circuits, the
integrator is a capacitive trans-impedance amplifier (CTIA) imple-In many imaging applications the target is obscured by a large mented with a single-stage telescopic cascode amplifier. Fig. 28.3.3background signal. For example, in infrared (IR) imaging, scenes depicts relevant timing diagrams with the corresponding integra-often have small temperature variations around a much higher tor output.background temperature [1]. In noninvasive in vivo fluorescenceimaging, scenes have high background levels due to tissue autoflu- The minimum current subtracted, around 1.3pA, is limited by theorescence caused by the excitation source [2]. Accurately resolving spatial variations of the emulated dark current and corresponds tosmall-signal variations in the presence of a large background sig- only one pulse in a 23ms integration time. The maximum currentnal imposes stringent requirements on the readout circuit, such as subtracted, around lIpA (Ml bias current), is limited by the CTIAnecessitating high dynamic range and fine quantization of the total bias. Minimizing GBW variations of the CTIA is critical to reduc-signal. Existing imaging systems mitigate these adverse effects by ing subtracted current variations. Although the BW required of theperforming multiple digital read-and-accumulate operations pixel amplifiers is relaxed as in continuous-time AL schemes, GBWwhich, as pixel count increases, result in lower sensitivity and variation causes a variation of the pedestal charge of M2, which islonger readout times than the background-limited integration designed to be below 1%.time. Addressing these limitations requires a significant increasein pixel readout area [3]. The prototype has been tested and characterized. Fig. 28.3.6 sum-
marizes chip characteristics and compares performance with andAn alternative approach that overcomes these shortcomings is to without background subtraction. Fig. 28.3.4 compares measuredperform analog signal subtraction during integration. Since stan- outputs for pixels with and without background subtraction. Thedard AC coupling or differential readout techniques used in other output of the pixel after subtracting 6nA from 6.24nA exhibits atypes of sensor interface circuits cannot be used in image sensors, sawtooth pattern due to the periodic charge packet subtraction.several authors have proposed schemes for per-pixel analog back- Fig. 28.3.5 provides histograms of measured noise and nonlineari-ground subtraction [4-8]. The idea is to estimate the background ty before and after background subtraction for the pixel array withphotocurrent every few frames and subtract a large fraction of it 200pA background photocurrent incremented by twenty 65fAfrom each pixel's photocurrent during integration. The functions steps. Subtracting 194pA enables the circuit to resolve a signal hid-needed to estimate the background signal can be readily imple- den within the background with an accuracy of 175ppm atmented as part of the standard camera control module (see Fig. 43frames/sec with a 30-fold increase in effective well capacity.28.3.1). To implement per-pixel subtraction, a current source Linearity improvement is less than the theoretically achievablebiased slightly below the background current is added. This cur- value of 4fA due to the integrator INL, since the signal of interestrent is subtracted from the input photocurrent and the residue is now spans the entire range of the integrator. Furthermore, meas-integrated. Such background subtraction relaxes sensor dynamic urement accuracy is also limited by the light source nonlinearity.range requirements, making it possible to reduce the integrating Measured peak spatial subtracted current variation over the arraycapacitor size and thus pixel area. It can also reduce the ADC res- is 3%. Temporal and spatial variations reported are at least 17 andolution and frame rate requirements, and improve sensitivity and 5 times lower, respectively, than that obtained by subtracting thelinearity. While the shot noise of the subtracted current is added to background by controlling the Ml bias current as in [6]. Since vari-the photocurrent shot noise, the SNR is improved since the integra- ations in the PFM pulse-width directly affect the charge packettion time can be increased without saturating the capacitor. It can size, linearity and current variations can be further improved bybe shown that background subtraction improves well capacity, SNR generating the PFM signal on chip (instead of externally as in thisand linearity by factors of up to (1 - cc)-i, (1 - (c')-' and (1 - cc), respec- work). The paper described a 1-D array design. Given the low pixeltively, where 0 < cx < 1 is the fraction of photocurrent subtracted. overhead of our scheme, a 2-D array can be readily designed.The major drawback of current subtraction schemes, however, ishigh spatial and temporal variations in subtracted current (in the Acknowledgements:
1s 1s rr ~~~~~~~~Theauthors thank B. Fowler and K. Fife for valuable insightspA to nA range) due to noise and Vt variations. and National Semiconductor for chip fabrication. The work is partially
supported by DARPA Grant: N66001-02-1-8940.To surmount these inherent limitations, we propose a per-pixelpulse frequency modulation (PFM) based scheme where charge References:packets controlled by a PFM signal are subtracted from each pixel's [1] G. C. Holst, Electro-optical Imaging System Performance, 2nd Ed., JCDintegrator. To validate this scheme, we designed a lx16 pixel array and SPIE, 2000.targeted for bump-bonding with medium and long wave IR HgCdTe [2] J. Mansfield et. alt, "Autofluorescence Removal, Multiplexing, anddiodes (see Fig. 28,3,7), The output of each pixel is connected to a Automated Analysis Methods for In Vivo Fluorescence Imaging," J. ofS/H circuit, consisting of a dynamically biased PMOS source follow- Biomsedical Optics, vol. 10, issue 4, 41207, pp. 1-9, July/August, 2005.
[31 S. Kang, D,. Woo and H Lee, "Multiple Integration Method for Higher whose output is connected to a CMOS pass gate and sampling Signal-to-Noise Ratio Readout Integrated Circuit," IEEE Proc. CICC, pp.capacitor, followed by an NMOS source follower compensated for 299-302, Sept., 2004.its body effect (see Fig. 28.3.2). The S/H allows the output of a pixel [41 G. Yang et al., "A High Dynamic-Range, Low-Noise Focal Plane Readoutwith and without background subtraction to be compared in each for VLWIR Applications Implemented with Current Mode Backgroundframe. The array periphery includes bias and timing circuitry and Subtraction," Proc. SPIE, vol. 3360, pp. 42-51, April, 1998.output drivers. The prototype is fabricated in a 0.18pim CMOS [51 S. Kleinfelder, A. Hottes and R.F.W. Pease, "Focal Plane Array Readout2P5M process and 3.3V thick gate-oxide transistors are used for Integrated Circuit with Per-Pixel Analog-to-Digital and Digital-to-Analogpixel circuitry. Conversion," Proc. SPIE, vol. 4028, 2000.[61 D.H. Woo, S.G. Kang and H.C. Lee, "Current Mode Background
Suppression for 2-D LWIR Applications," IEE Elect. Letters, Vol. 41, No. 5,Each pixel consists of a 3Onmx3Otm NWELL/PSUB diode (used to pp. 221-222, Mar,, 2005.simplify characterizationL) and currenLt source Ml1 conLnected to an [71 C, Hsitch et; al., "High-Performance CMOS Buffered Cate Modulat;ioninltegrator via switch M2 that is conrlLlolled by the PFM signal. The Input (BCMI) Readout Circuits for IR FPA," IEEE J. Solid-Stntte Circui[ts,bias cuLrrent ofMl anLd the PFM signLal pulse-width control the sub- Vol. 33, pp. 1188-1198, Aug., 1998,tracted charge packet size. By selecting a short pulse-width, Ml [SI M, Tepegoz and T, Akin, "A Readout Circuit; for QWIP Infralred Detectzor
carL b bise ata rlaivey hghlevl. tslonLg chanLnel lenLgth nzot A3rrayss Using Current Mirroring Inltegrationl," Proc. ESSCIRC, pp. 133-only allows operatioln in strong inversion, which reduces the spatial ' ,variations over the array caused by Vt mismatches, but also
504 1 2007 IEEE International Solid-State Circuits Conferenc 1-4244-0852-0/07/$25.00 ©2007 IEEE.Authorized licensed use limited to: Stanford University. Downloaded on March 02,2010 at 14:44:26 EST from IEEE Xplore. Restrictions apply.
ISSCC 2007 / February 14, 2007 / 2:30 PM
Pixel Circuit VDD Reset
| I ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~VBIAS O1 M
l ' l Driver M j2Im S/H, Reaou
CTan,OfstRLR
| 3{ T TC =| X LH, II I I PFMV(t ) j~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~PFjVt
' p 0 F / ~~~~~~~ ~~~~~~~~~~SHO-Oi,,p A/D . ... .. l..........BackgroundEstimation
l ' 2 0 0 i < | (D | , l | g :SLs~~~~~~~~~~~~~~~~~~~~Bis S/HSlct
Image Sensor C(alibration Raw Output E34E'',V(t)t T n Slxt 10 Out,D
ID~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Figure 28.3.1: Imaging system with background subtraction. Figure 28.3.2: Pixel schiematic for PFMI background subtraction scheme.
Reset I_ fl I Up8 tr h
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~m lfe /, Reaou
PixeltB1 s t edS B
|PFM T [ 1 1 1 [lUOniWdiv l) 5LiUmO
Calibration Raw Output ConventionalOpixelut
S HJ7J7___ _ _ _ _~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~H Sc
ias --1--''1 -------------------------- -------
V(t) ackground
+-~~~~~~~~~~~~~~~~~~~~~~~bi
0 ~ ~ ~~~ ~~~~~~~~~~~~~~~~~~~~*Xj |j OLIn /dif jI_ 4UU.S212;g77 R .43S
I A, = ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~R-(41=-80l.89251 V2--- UU- 00.93 p. 3.615
Figure 28.3.3: Timing diagram and corresponding integrator output. Figure 28.3.4: Plot of outputs for pixels witlh and without background subtraction.
Chip characteristics1060 Technology 0.1 8Fm CMOS
L dll 2 | A ~~~~~~~~~~Arraysize 16xlp ,l1111, j | | ~~~~~~~~~~~Pixelcircuit area 900Ftm2
r |gil|||lL r | ~~~~~~~NWELL/PSUB diode area 900Ftm2
o 0~~~~~~~~~~~~~~~~~~~~~~N
o |||11 11 Emulated dark current lpAk 11111111||g1|g j *1|11 X ~~~Minimum integration time 4ts
0 Ea||l ll|l ||l lllaaaa.3 X l ii | aa,Integrator capacitance 100fF
-00 0 700 -00 0 200 CTIA gain 69dBTemipofal noise (fA) Nlonlnear ty (fA) Readout DNL 0.15%o
Pixel power consumption 19FtW5000 ii90II
F ....1Performance comparison Conventional Background subtractedt gl q ll A ~~~~~~~~~~~~Effectivewell capacity 937,500 e ~ 28,218,750 e~
3 P 11 2 = .11 ~~~~~~~~~~Integration time 766Fts 23ms
O 111. 2 v 11 1~ Maximum photocurrent 200pA 6pA (a=0.97)" |lS q llg ~~~~~~~~~~Subtracted current 0 194pA0 ll X t 11ll ~~~~~~~~PeakSNR 60dB 75dBt |g1 1 o M1||glk ~~~~~~~~Temporal noise standard deviation 176fA 35fA
0: 70 -200 0 200 Maximum nonlinearity 104fA 54fATemipofa noise fA) NIon nearrty (fA4 Background subtraction spatial N/A 30% peak
variationFigure 28.3.5: Histograms of measured noise and nonlnearity for th,e pixel array withconventional readout (top) and with background subtraction (bottom). Figure 28.3.6: Chip characteristics and measured performance comparison.
Conztinlued onz Patge 618
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ISSCC 2007 PAPER CONTINUATIONS
Figure 28.3.7: Chip micrograph.
61 07IE Intentoa Soi-tt icut ofrne 2405-/0/20 20 IEEE
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