PRESS KIT - Columbia University · 2007-12-12 · table of contents isscc 2005 – executive...
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Transcript of PRESS KIT - Columbia University · 2007-12-12 · table of contents isscc 2005 – executive...
2005
PRESS KIT
ISSCC.ORG
Produced by: S3 Digital Publishing, Inc.
Lisbon Falls, Maine USA
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TTABLE OF CONTENTSABLE OF CONTENTS
ISSCC 2005 – EXECUTIVE SUMMARY............................................................................1
ACTIVITIES AT ISSCC 2005 ..........................................................................................................3
CONFERENCE THEME..................................................................................................................4
SIGNIFICANT RESULTS ................................................................................................................6
ISSCC 2005 – CONFERENCE OVERVIEW....................................................................9
EVENTS ........................................................................................................................................11
PAPER STATISTICS ....................................................................................................................12
PLENARY SESSION ....................................................................................................................13
TECHNICAL HIGHLIGHTS ..........................................................................................................15
DISCUSSION SESSIONS ............................................................................................................19
Short Course ................................................................................................................................20
Tutorials ........................................................................................................................................21
CIRCUIT DESIGN FORUMS
CLOCK AND FREQUENCY GENERATION FOR WIRELINE AND WIRELESS APLLICATIONS
ADVANCED DYNAMIC MEMORY DESIGN ....................................................................................22
CHARACTERIZATION OF SOLID-STATE IMAGE SENSORS
ROBUST DESIGN SOLUTIONS FOR NANOSCALE CIRCUITS:
FROM DFM THROUGH END-OF-LIFE ......................................................................................23
ATAC: AUTOMOTIVE TECHNOLOGY AND CIRCUITS ....................................................................24
ISSCC 2005 – ANALOG ............................................................................................................25
OVERVIEW ..................................................................................................................................27
FEATURED PAPERS....................................................................................................................28
Panel WHAT PAPERS WILL BE (AND WILL NOT BE) AT ISSCC 2010? ..............32
Tutorial INTEGRATED POWER MANAGEMENT ......................................................39
ISSCC 2005 – DIGITAL..............................................................................................................35
OVERVIEW ..................................................................................................................................37
FEATURED PAPERS....................................................................................................................39
Special-Topic Session WHEN PROCESSORS HIT THE POWER WALL
OR "WHEN THE CPU HITS THE FAN") ..........................................54
Tutorial INTRODUCTION TO I/O DESIGN FOR DIGITAL SYSTEMS ......................56
Forum ROBUST DESIGN SOLUTIONS FOR NANOSCALE CIRCUITS:
FROM DFM THROUGH END-OF-LIFE......................................................57
TREND CHARTS ..........................................................................................................................58
ISSCC 2005 – IMAGERS, DISPLAYS AND MEMS ................................................61
OVERVIEW ..................................................................................................................................63
FEATURED PAPERS....................................................................................................................64
Panel MOBILE IMAGING: PARADIGM SHIFT OR TECHNOLOGY BUBBLE? ......69
Tutorial RF MEMS: DEVICES, CIRCUITS, AND PACKAGING ..................................70
Forum CHARACTERIZATION OF SOLID-STATE IMAGE SENSORS ....................71
ISSCC 2005 – MEMORY ..........................................................................................................73
OVERVIEW ..................................................................................................................................75
FEATURED PAPERS....................................................................................................................76
Special-Topic Session SRAM DESIGN IN THE NANOSCALE ERA? ........................................82
Tutorial PHASE-CHANGE MEMORY ..................................................................84
Forum ADVANCED DYNAMIC-MEMORY DESIGN ..........................................85
ISSCC 2005 – SIGNAL PROCESSING ..........................................................................87
OVERVIEW ..................................................................................................................................89
FEATURED PAPERS....................................................................................................................90
Panel DRIVING MISS UBIQUITY:
WHAT APPLICATIONS WILL FILL TOMORROW'S FABS? ......................93
Tutorial DSP CIRCUIT TECHNOLOGIES FOR THE NANO-SCALE ERA ................94
ISSCC 2005 – TECHNOLOGY DIRECTIONS ............................................................95
OVERVIEW ..................................................................................................................................97
FEATURED PAPERS....................................................................................................................99
Special-Topic Session INTEGRATION IN THE 3RD DIMENSION:
OPPORTUNITIES AND CHALLENGES ......................................105
Tutorial NANOTECHNOLOGY 101 ..............................................................107
ISSCC 2005 – WIRELESS COMMUNICATIONS ....................................................109
OVERVIEW..................................................................................................................................111
FEATURED PAPERS ..................................................................................................................112
Panel RF MEMS: FACT OR STICTION? ..............................................................121
Tutorial POLAR MODULATORS FOR LINEAR WIRELESS TRANSMITTERS........122
Forum GIRAFE Forum: CLOCK AND FREQUENCY GENERATION FOR
WIRELINE AND WIRELESS APPLICATIONS..................123
ISSCC 2005 – WIRELINE COMMUNICATIONS ......................................................125
OVERVIEW ................................................................................................................................127
FEATURED PAPERS..................................................................................................................129
Special-Topic Session POWERLINE LAN: IS THERE A CONCRETE WALL
DIVIDING WIRELESS FROM WIRELINE? ........................................134
Tutorial HIGH-SPEED ELECTRICAL INTERFACES:
STANDARDS AND CIRCUITS ............................................................136
Forum ATAC: AUTOMOTIVE TECHNOLOGY AND CIRCUITS ....................137
ISSCC 2005 – PRESS-RELEASE SESSION OVERVIEWS ..........................139
CONDITIONS OF PUBLICATION ..............................................................................................140
SESSION OVERVIEWS..............................................................................................................141
ISSCC 2005 – PRESS-COPY MATERIALS ................................................................173
CONDITIONS OF PUBLICATION ..............................................................................................174
PRESS COPY ............................................................................................................................175
ISSCC 2005 – ISSCC GLOSSARY ..................................................................................211
ACRONYM LISTING ..................................................................................................................213
PREFIXES AND UNIT ABBREVIATIONS ..................................................................................216
ISSCC 2005 – CONTACT INFORMATION ..................................................................217
TECHNICAL EXPERTS ..............................................................................................................219
GENERAL CONTACTS ..............................................................................................................220
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WIRELINE COMMUNICATIONS
" Overview
" Featured Papers
" Special-Topic Session
" Tutorial
" Forum
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Sessions: 3, 8, 12, 18, 22 [AP20, 32, 40, 54, 64] WIRELINE
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Subcommittee Chair: Franz Dielacher, Infineon, Villach, Austria
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MOST-SIGNIFICANT RESULTS
" 6.4Gb/s CMOS SerDes Core with Feed-Forward and Decision-Feedback Equalization [3.2]
" 6.25Gb/s Binary Adaptive Decision-Feedback Equalizer with First Post-Cursor Tap Cancellation [3.5]
" Circuit Techniques for a 40Gb/s Transmitter in 0.13$m CMOS [8.1]
" 3V 10.7Gb/s Differential Laser-Diode Driver with Active Back-Termination Output Stage [12.1]
" 20Gb/s VCSEL Driver and Regulated Output Impedance in 0.13$m CMOS [12.2]
" RF/Baseband FDMA-Interconnect Transceiver for Reconfigurable Multiple Access in Chip-to-Chip
Communication [18.6]
" 0.94ps-rms-jitter 2.5GHz Multiphase Generator PLL for 10Gb/s Serial Links [22.1]
" 101dBc/Hz at 1MHz, 44GHz Differentially-Tuned VCO with 4GHz Tuning Range in 0.12$m SOI
CMOS [22.4]
APPLICATIONS AND ECONOMIC IMPACT
" Further improvements on equalization techniques in the receiver allow higher data rates for legacy
backplane connections. [3.2, 3.5, 18.1]
" Demonstration of a 40Gb/s CMOS transmitter and MUX/DEMUX circuits accelerate efforts toward
implementing 40Gb/s transceiver and logic circuits in CMOS. [8.1, 8.2]
" Spread-spectrum clock generators with both low EMI and low jitter, can be used for the reliable
chip implementation of SATA and other serial-link standards. [8.6, 8.7]
" Optical communications benefit from low-power and low-voltage laser drivers and high-speed and
low-power burst mode receivers. [12.1, 12.2, 12.4, 12.5]
" Advanced technology and new circuit techniques are used to lower power and jitter and to increase
the speed of the basic building blocks such as VCO, DCXO and PLL. [22.1, 22.2, 22.4, 22.5,]
" Shrinking CMOS linewidths enable increasingly complex and integrated transceivers.
" CMOS is taking over more and more from BiCMOS, SiGe, and GaAs, for the electrical and optical interconnections between chips, over backplanes, and between systems.
" The increase in transmission speed from 6.25 Gb/s to 40 Gb/s makes it possible to transfer the content of a whole DVD within less than 1 second. Such chips will be used in the backbone of the Internet, and will significantly contribute to faster access and download for the individual user of Internet services.
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Sessions: 3, 8, 12, 18, 22 [AP20, 32, 40, 54, 64] WIRELINE
SPECIAL-TOPIC SESSION
Powerline LAN : Is There a Concrete Wall Dividing Wireless from Wireline? [SE1]
TUTORIAL
High-Speed Electrical Interfaces: Standards and Circuits [T8]
FORUM
ATAC: Automotive Technology and Circuits [F5]
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Session: 3 [AP20] WIRELINE FEATURE
BBAACCKKPPLLAANNEE TTRRAANNSSCCEEIIVVEERRSS
A 6.4Gb/s CMOS SerDes Core with Feedforward and Decision-Feedback Equalization [3.2] IBM
A 6.25Gb/s Binary Adaptive Decision Feedback Equalizer with First Post-Cursor Tap Cancellation for Serial Backplane Communications [3.5] Texas Instruments
PRESENT STATE OF THE ART (THE PROBLEM)
" Need to enable recovery of data-eye fully-closed from channel losses and crosstalk at 5Gb/s and above,in CMOS
" Legacy 1 to 3Gb/s backplane channels require transmit and receive equalization techniques at 5 Gb/s and above, but they are power hungry
" Bit-error-rate (BER) requirement of 10-15 or better mandates a holistic approach to transceiver design with full link-jitter modeling and verification
NOVEL CONTRIBUTIONS
" 2-tap VGA and peaking amplifier [3.2], and direct feedback of 1st tap [3.5] in receiver to cancel ISI
" Adaptation of equalizer coefficients to channel characteristics [3.2, 3.5]
" 2-path VGA design in receiver enables linear operation up to 1.2V p-p differential input signals
[3.2]
CURRENT AND PROJECTED SIGNIFICANCE
" Doubles bit rate from existing 3Gb/s (XAUI) to 6Gb/s (Optical Internetworking Forum /CEI-CEI-
6G+) backplanes [3.2, 3.5]
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Session: 3 [AP32] WIRELINE FEATURE
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Circuit Techniques for a 40Gb/s Transmitter
in 0.13$m CMOS [8.1] Seoul National University
PRESENT STATE OF THE ART (THE PROBLEM)
" At 40Gb/s, integration level of CMOS is limited to small circuits such as 4:1 MUX
" Waveform degradation due to bandwidth limitation still a problem
" Power reduction required
NOVEL CONTRIBUTIONS
" Single-chip 40Gb/s transmitter with 20GHz PLL, 16:1 MUX, and PRBS generator [8.1]
" Judicious use of circuit techniques enables 40Gb/s transmitter with 0.13µm CMOS [8.1]
" Power consumption of 2.8W achieved [8.1]
CURRENT AND PROJECTED SIGNIFICANCE
" CMOS offers low-cost single-chip solution for up to 40Gb/s [8.1]
" More integration effort expected toward 40Gb/s CMOS receiver circuits [8.1]
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Session: 12 [AP40] WIRELINE FEATURE
OOPPTTIICCAALL CCOOMMMMUUNNCCAATTIIOONNSS
A 20Gb/s VCSEL Driver with Pre-Emphasis and
Regulated Output Impedance in 0.13$m CMOS [12.2] IBM; Cornell University; Agilent Technologies
1.25Gb/s Burst-Mode Receiver ICs with Quick Response for PON Systems [12.4] NTT
A 12.5Mb/s to 2.7Gb/sContinuous Rate CDR with Automatic Frequency Acquisition and Data-Rate Readback [12.6] Analog Devices
PRESENT STATE OF THE ART (THE PROBLEM)
" Limited capability to handle different data rates and formats
" System interconnect now is limited to 1Gb/s and is bulky (large size) and uses expensive copper cables
" 10Mb/s Cable modem or ADSL
NOVEL CONTRIBUTIONS
" High-speed (20Gb/s) parallel optics and small light-weight low-cost cable [12.2]
" Burst receiver enables PON [12.4]
" Data rate is automatically detected and used [12.6]
CURRENT AND PROJECTED SIGNIFICANCE
" Low-cost high-speed computer systems [12.2]
" PON is low cost for very high data rates (1G) to home [12.4]
" Low-cost metro-networks with the ability to transport any data formats already in use [12.6]
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Session: 18 [AP54] WIRELINE FEATURE
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An RF/Baseband FDMA-Interconnect Transceiver for Reconfigurable Multiple Access in Chip-to-Chip Communication [18.6] SST Communications
PRESENT STATE OF THE ART (THE PROBLEM)
" Chip-to-Chip connections are fixed at design time, limiting system flexibility
" Coordinating multiple-access buses requires coordination between everyone on the bus; only one pair of chips can communicate at any one time.
" Transmission media can cause severe distortion at multi-Gb/s data rates.
NOVEL CONTRIBUTIONS
" High-bit-rate is accomplished by transmitting data at multiple frequencies. Each channel runs
slower and is easier to design. [18.6]
" Unlike CDMA, rake filters are not needed. [18.6]
" No bus contention. [18.6]
" Connections become reconfigurable; any pair of chips can
communicate uninterrupted. [18.6]
CURRENT AND PROJECTED SIGNIFICANCE
" More-robust backplane transmission. [18.6]
" Allow smaller more-functional cheaper boards. [18.6]
" Alternative to ever-faster conventional serial transmission. [18.6]!!
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Session: 22 [AP20] WIRELINE FEATURE
!
A 0.94ps-rms-Jitter 0.016mm2 2.5GHz Multi-Phase- Generator PLL with 360º Digitally-Programmable Phase- Shift Capability for 10Gb/s Serial Links [22.1] IBM; Miromico
A 15mW 3.125GHz PLL for Serial Backplane Transceivers in 0.13µm-CMOS [22.2] Synopsys
PRESENT STATE OF THE ART (THE PROBLEM)
" Multi-Gigabit data transmission needs very-low-jitter clocks for low-BER operation.
" The cross-talk-rich environment of high-speed serial links makes clock requirement still more stringent.
NOVEL CONTRIBUTIONS
" A multiple-clock-phase PLL with dedicated phase detectors permits sub-ps rms tracking jitter at 10Gb/s. [22.1]
" Special circuit techniques and attention to loop dynamics enable a lower-power small-area PLL
with 1.3ps rms-jitter at 3.125GHz. [22.2]
CURRENT AND PROJECTED SIGNIFICANCE
" Near-ideal multi-Gb/s clocks permit higher data rates over both new and existing links, , and
enable greater transmission distances [22.1, 22.2]
!
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Special: SE1 [AP12] WIRELINE
SSPPEECCIIAALL--TTOOPPIICC SSEESSSSIIOONN
PPoowweerrlliinnee LLAANN:: IIss TThheerree aa CCoonnccrreettee WWaallll DDiivviiddiinngg
WWiirreelleessss ffrroomm WWiirreelliinnee?? Organizer: Mark Ingels, STMicroelectronics Belgium N.V., Zaventem, Belgium
Chair: Michael Green, Dept. of EECS, University of California, Irvine, CA
OVERVIEW
" Powerline Communication (PLC) is an emerging technology that allows data transfer at high rates over existing power lines.
" The significance of PLC systems in practical situations will be highlighted
" Various existing chipsets with a potential data-transfer rate up to hundreds of megabits per se will be presented
OBJECTIVE
" To understand the significance of PLC for real-life and high-speed data communication within the home
" To present the major PLC solutions that are available today
" To investigate future technical and economic growth potential of PLC
CHALLENGE
" What is the use of PLC? Why is it viable? What is the future?
" How does PLC compete with Wireless LAN?
" How does PLC complete Wireless LAN?
" What type of data encoding should be used for high-speed communication on existing power wires?
" How to cope with emission?
" How to limit radiation?
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Special: SE1 [AP12] WIRELINE
STRUCTURE
" The first talk will provide a broad overview of PLC and will clarify its use and advantages. The following two presentations will present chipsets with data rates up to 14Mbps, and with a potential up to several hundreds of megabits. The final talk will present a narrowband system that is being deployed for remote control via power line.
" Speakers and specialties:
" Haniph A. Latchman, University of Florida: “Broadband Powerline Multimedia Home
Networking % Advantages and Challenges”
" Jim Petranovich, Conexant Systems, Inc.:“OFDM for Power Line Communications”
" In OFDM-based chipset, including challenges for practical implementation.
" Vincent Buchoux, LEA SA: “Performance Analysis of a CDMA Chipset for InHouse BroadBand Powerline Communications”
" A new CDMA-based chipset, including performance and radiation issues
" Claudio Cantoro, Dora: “Remote Control via Powerline”
" A narrowband system that is useful for (long-range) remote control.
RECAP
" To clarify what is PLC?
" To highlight its advantages and demonstrate its use in practical situations.
" To present various existing systems that enable real PLC transmission.
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Tutorial: T8 [AP7] WIRELINE
TTuuttoorriiaall
HHIIGGHH--SSPPEEEEDD EELLEECCTTRRIICCAALL IINNTTEERRFFAACCEESS:: SSTTAANNDDAARRDDSS AANNDD CCIIRRCCUUIITTSS Yuriy M.Greshishchev, PMC Sierra Inc, Ottawa, Canada
OVERVIEW
The tutorial will review the physical level standard specification space (including standards under development), and the challenges in the multi-gigabit-range high-speed electrical-interface area, such as XFI, CEI , XAUI, Fiber-Channel, SAS, SATA, and others. Jitter requirements, signal amplitude, impedance, S-parameter specifications, and transmission-channel representation, along with equalization techniques, will be studied. Block diagrams and circuit solutions will also be discussed. This tutorial will assist attendees to understand IC design parameters, their link to standard specifications, and current and future challenges in wireline IC design of electrical interfaces for the multi-gigabit range.
SPEAKER BIOGRAPHY
Yuriy M.Greshishchev, PMC Sierra Inc, Ottawa, Canada, is a Technical Advisor on high-speed circuit design for wireline communications. His design experience is in multi-gigabit-rate CMOS, SiGe, and III-V circuits for telecom and datacom applications. He has been involved in XFI, Fiber Channel, SAS, RIO physical-level standards technical groups. He has been a member of the ISSCC Technical Program Committee for five consecutive years. He presented an ISSCC Tutorial on front-end circuit design for optical communications in 2001. He has coauthored two books and numerous technical papers in the area of high-speed communication-circuit design and data converters. He received his Ph. D. degree in Electrical and Computer Engineering from V.M. Glushkov Institute of Cybernetics, Microelectronics Division, Kiev, Ukraine, in 1984.
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Forum: F4 [AP90] WIRELINE
FFOORRUUMM
ATAC: Automotive Technology and Circuits
Objective This all-day forum is dedicated to automotive electronics, encompassing the associated high-voltage and high-power technologies, complex system developments, and robust circuit design required for automotive applications.
Attendance is limited, and pre-registration is required. This all-day forum encourages open interchange in a closed form.
Audience The targetted participants are circuit designers working on the advanced development and design of automotive systems and chips, who want to learn about the latest developments in technology, system and circuit design for automotive applications.
Scope While the automotive market has long been driven by innovations and improvements in the mechanical, hydraulic, and pneumatic systems of the car, this situation has changed, and the majority of innovations in cars is currently driven by electronics. Electronics will become even more pervasive for the foreseeable future, with a shift from separate electronic modules to fully- interconnected intelligent systems e.g. drive-by-wire. This evolution, together with the growing use of high-performance sensors, requires increasingly complex and accurate electronic hardware and software in the car. At the same time, the stringent safety requirements are increasingly tightened while the harsh automotive-environment demands are further increased. This forum discusses selected topics in automotive high-voltage and high-power technologies, complex system developments, and robust circuit design.
Program The Forum will begin with a comprehensive overview of automotive electronic systems and market
trends. Patrick Leteinturier, from Infineon, will discuss the challenges, and demonstrate the key elements needed, for the ongoing evolution/revolution of automotive electronics. The next two papers will discuss semiconductor technologies for automotive applications from the
viewpoints of the car manufacturer and the semiconductor industry. First, Masayuki Hattori, from Toyota, will describe how several very-different semiconductor technologies are needed for their new generation of hybrid cars, including high-performance CPUs, complex high-voltage mixed-signal LSIs, and high-
speed/low-saturation voltage IGBTs. In the second paper, Hak-Yam Tsoi from Freescale, will show
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Forum: F4 [AP90] WIRELINE !
FFOORRUUMM
ATAC: Automotive Technology and Circuits (continued) Program (continued) how high-power high-performance analog and complex digital circuits are combined in their SMARTMOS technology. In the fourth and fifth papers, complex system-design issues and trade-offs for in-vehicle image
processing and data communication, in the harsh automotive environment, will be discussed. Shorin Kyo, from NEC, will focus on architectural and system-design choices for image processing for driver- assistant systems, where a high computational requirement has to be balanced against a high
power efficiency and system flexibility. Stefan Poledna, from TTTech, will then discuss the various requirements for in-vehicle data communication. Dependability of the communication channel is of major concern for the very different types of in-vehicle communications, such as interaction with smart sensors and actuators, data exchange for closed-loop control, diagnostic and repair information, multimedia and telematics. The last three papers will focus on robust-circuit-design aspects for different automotive applications.
Koen Appeltans, from AMIS, will first present the physical layer of a LIN (Local Interconnect Network) transceiver. He will pay attention to the non-standard aspects of integrated-circuit design for the harsh automotive environment, such as deeply-negative voltages, system ESD events, low electromagnetic emission, and high electromagnetic immunity. Gunther Leising, from LUMITECH, will then discuss the latest developments in high-luminous-flux and high-efficiency LED-packages and present current and future solutions for the thermal management and light-output shaping
requirements. Dirk Hammerschmidt, from Infineon, will deal with the influence of automotive applications and micro-system technology on the system and circuit design of integrated magnetic- field and surface micro machined pressure sensors. These sensors have to be compatible with the IC technology on the one hand, while they require extensive signal processing to remove the sensor non-idealities, on the other. At the end of the afternoon, all speakers will assemble in a panel format, for an open discussion with the audience, on the challenges in all aspects of automotive electronics.
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CONDITIONS OF PUBLICACONDITIONS OF PUBLICATIONTION
PREAMBLE
• The Session Overviews to follow serve to capture the context,highlights, and potential impact, of the papers to be presented ineach Session at ISSCC 2005 in February in San Francisco.
• OBTAINING COPYRIGHT to ISSCC press material is EASY !
•• You are welcome to use this material, copyright- and royalty-free,with the following understanding:
" That you will maintain at least one reference to ISSCC 2005 inthe body of your text, ideally retaining the date and location.For detail, see the FOOTNOTE below.
" That you will provide a courtesy FAX of your excerpted presspiece and particulars of its placement, to 416-971-2286,Attention ISSCC Press Relations.
FOOTNOTE
• From ISSCC’s point of view, the phraseology included in the boxbelow captures what we at ISSCC would like your readership toknow about this, the 52nd appearance of ISSCC, on February 6th to10th, in San Francisco.
This and other related topics will be discussed at length at ISSCC 2005, theforemost global forum for new developments in the integrated-circuit industry.ISSCC, the International Solid-State Circuits Conference, will be held onFebruary 6-10, 2005, at the San Francisco Marriott Hotel.
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© COPYRIGHT 2004 ISSCC–DO NOT REPRODUCE WITHOUT PERMISSION
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Non-Volatile Memory
Chair: Yair Sofer, Saifun Semiconductors, Netanya IsraelAssociate Chair: Yukihito Oowaki, Toshiba, Kawasaki Japan
Consumer-electronic applications such as cellular phones and digital cameras are driving a need for higher-performance and lower-cost-memory solutions. This year's Conference by is marked a strong showof non-volatile memories. In the Flash memory arena, we are seeing major breakthroughs in density, per-formance and cutting-edge lithography. We have seen a sprinkling of multi-level Flash papers since 1995.This year, multi-level Flash makes up the majority of the non-volatile memory presentations that report onnew design approaches. Designs utilizing multi-level techniques have historically been lower-performance.With design and technology breakthroughs, we are seeing high-performance read and write times combinedwith multi-level storage.
This session will also look into new circuit techniques to achieve much-faster lower-power flash program-ming. As well, recent advancements in the area of emerging nonvolatile technologies will be reported.
In Papers 2.1 and 2.2 exhibit the highest-density Flash memories ever reported (,(8Gb) (,fabricated inadvanced 70nm and 63nm technologies and using a multi-level approach and NAND structure. Write per-formance is dramatically improved to reach a level comparable with single-bit-per-cell memories.
A 1.8V 64Mb phase-change RAM (PRAM) fabricated in a 0.12'm technology is described in Paper 2.3. Thepaper presents techniques to improve write distribution and read margins.
An in-package inductor and capacitor are utilized for the first time to implement a hybrid voltage multiplier toimprove write performance, power efficiency, and to save area, in a NOR Flash product. This scheme isdescribed in Paper 2.4.
A 256Mb NOR Flash featuring an innovative sensing concept, based on a fast gate-voltage-ramp, whichoperates the cells at constant current is discussed in Paper 2.5. It overcomes the main drawbacks of multi-level NOR scaling.
A 512Mb 90nm NOR Flash, presented in Paper 2.6, has the fastest synchronous-read frequency and pro-gramming throughput ever reported.
Finally, the first 4Gb multi-level AG-AND Flash to achieve 10MB/s write throughput is reported in Paper 2.7.
Session: 2 [AP18] SESSION OVERVIEWMemory
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Backplane Transceivers
Chair: Mehmet Soyuer, IBM, Yorktown Heights, NYAssociate Chair: Muneo Fukaishi, NEC, Kanagawa, Japan
The increasing clock rates of processing cores accompanying continuing advances in silicon technologydrive the need to push electrical interconnect speeds higher. As industry-standard data rates pass 3Gb/sand approach the 5 to 12Gb/s realm, degradations from channel effects such as bandwidth loss, reflections,and crosstalk, can distort the signal to such an extent that robust data recovery requires equalizer-basedbackplane transceiver designs. Legacy 1 to 3Gb/s backplane channels rely on power-efficient NRZ transmit-and receive-side equalization techniques with adaptation. New signaling schemes, with better spectral effi-ciency, such as PAM4 and duobinary signaling, are of interest for data rates exceeding 10Gb/s. Anotherdesign challenge is the low bit-error-rate (BER) requirement of 10-15 or less.
As highlighted by the first five papers in this session, these requirements are currently being addressed bytransceiver designs using NRZ signaling in 0.13'm CMOS, targeting data rates from 5Gb/s to approximately10Gb/s. Overall, the transceivers described in Papers 3.1 through 3.5 employ feedforward equalization anddecision-feedback equalization techniques. This combination helps to optimally compensate for bandwidthlosses, providing with improved immunity to inter-symbol interference (ISI) and crosstalk.
A 5Gb/s NRZ transceiver with a 2-tap pre-emphasis network in the transmitter, along with a 1-tap FFE and3-tap DFE in the receiver, is featured in Paper 3.1. It achieves a BER of less than 10-15 over 4 pairs of 1mPCB traces, in the presence of crosstalk.
A 4.9 to 6.4Gb/s transceiver core is described in Paper 3.2. The use of a 4-tap FFE, a 2-path VGA, and apeaking amplifier followed by a 5-tap DFE, enables operation on ISI channels with over 30dB loss at3.2GHz. It achieves a power efficiency of 45mW/Gb/s.
A transceiver core operating from 0.6 to 9.6Gb/s using adaptive receive equalization with a 1-tap DFE fol-lowed by a linear equalizer, is described in Paper 3.3. The core dissipates only 150mW at 6.25Gb/s.
The 6.25Gb/s transceiver described in companion Papers 3.4 and 3.5 highlights a 4-tap DFE architecturethat uses direct feedback of the first-tap output to cancel post-cursor ISI. It operates at a BER less than 10-16 over legacy 1Gb/s backplane channels.
The last two presentations of this session describe a 90nm CMOS 12Gb/s duobinary transceiver and a90nm SOI 25Gb/s PAM4 transmitter. Duobinary signaling, with a 10-tap 2x-oversampled equalizer used toachieve 12Gb/s over a 75cm low-k PCB trace, is employed in Paper 3.6. The measured eye height is 3dBlarger than for NRZ signaling. The PAM4 transmitter in Paper 3.7 targets short-range chip-to-chip intercon-nects. It features a 4-tap FIR filter, and achieves a power dissipation of 100mW at 25Gb/s.
Session: 3 [AP20] SESSION OVERVIEWWireline
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Session: 4 [AP22] SESSION OVERVIEW
Mixed-Domain Systems
Chair: Kerry Bernstein, IBM, Essex Junction, VTAssociate Chair: Siva Narendra, Intel, Hillsboro, Oregon
Hybrid interdisciplinary technologies enable an exciting and powerful new integration direction. Developmentof monolithic mixed-domain structures (such as DRAMs embedded in high-performance logic chips), so far,have focused on co-optimizing MOSFET, bipolar, and other silicon-based devices. Dimension scaling hasbrought CMOS to a size regime where it is now possible to exchange data with living neurons; to sense thestate of individual atoms; and ultimately to reproduce human sensory function in a biological form factor.These advances are made possible by the convergence of VLSI with improvements in ancillary technologies, such as micromechanical machining, optics, and thin films. Mixed-domain systems promise toreduce latency, extend resource utilization, and increase transaction rate. Additionally, new capabilities areenabled and existing functions are realized with lower power and cost, by such mixed-domain systems.
Electrochemical as well as magnetic interaction with living tissue is explored in Papers 4.1 and 4.3. Newwork exploring neuro-electronic junctions is described in Paper 4.1. The interfacing between electronic andionic systems must be examined at the ion channel, nerve cell, and extended-network/brain-tissue level inorder to facilitate interchangeable signal processing, and this paper describes the unique approaches initiated to achieve these milestones. The magnetic tags, described in Paper 4.3, enable the use of CMOSlogic to manipulate cells attached to these tags in a medium layered immediately above the logic. The potential impact of such a technique is readily apparent.
Direct stimulation of auditory nerves using a processor in a bionic ear is described in Paper 4.2. Much morethan improving conventional hearing-aid techniques, this device maps its logarithmic-spectral-filter output toa set of topographic stimulation electrodes. By accessing the cochlea directly, the technology can emulatethe fundamental biological hearing process.
The synchronous digital state machine is one of a number of architectural paradigms that are realized with current fabrication capabilities. Atomistic and, more recently, quantum-mechanical limitations arising from continued scaling require increasing timing margin and tolerance; these concerns make theanalog-computer/math-co-processor advocated in Paper 4.4 very interesting and timely.
The final three papers in this session explore the integration of CMOS with MEMS and optics technologiesto bring new functions on-chip. An on-chip MEMS-based low-power atomic clock is described in Paper 4.5.This chip is more than 700x smaller in volume than the state-of-the-art commercially-available atomic clocks,while delivering comparable precision. MEMS is also an enabler for realizing gyroscopes in CVD SiGe filmsdeposited on conventional CMOS. Robust outputs are developed from larger capacitive-coupled signals, as shown in Paper 4.7. The observed improvements in signal-distribution precision in processors, and thelatency-reduction realized in hardware, is presented in Paper 4.6. These improvements are achieved by the integration of optical interconnects with conventional CMOS. For the first time, less than 1ps of measuredrms jitter is reported.
Technology Directions
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WLAN Transceivers
Chair: Arya Behzad, Broadcom, San Diego, CAAssociate Chair: Mototsugu Hamada, Toshiba, Kawasaki, Japan
Mass-consumer-market wireless applications set strict requirements on cost, dynamic range, power con-sumption, and the number of external components used in the system. These constraints have already beenapplied to Bluetooth chips, and the resultant chips have been reported at previous ISSCCs. This year, wesee these trends being applied to WLAN ICs, and similar levels of integration being demonstrated in WLANSoCs. As such, many of the most-integrated solutions are implemented in deep-submicron CMOS tech-nologies which allow the full integration of the MAC and the PHY layers on the same die. These highly inte-grated low-cost low-power ICs open the door for the application of WLAN ICs to many new embedded andnon-embedded applications, and ultimately to a seamlessly connected world.
A I/Q self-calibrating super-heterodyne CMOS 802.11g transceiver is presented in Paper 5.1. As a result ofthe calibration scheme, 1° phase mismatch and 0.1dB amplitude mismatch is achieved. There is only a 5%die-area penalty for implementing this calibration scheme. The die occupies an area of 10.2mm2.
The authors present the most-integrated 802.11g SoC published to date in Paper 5.2. The chip utilizes asliding-IF super-heterodyne architecture, and includes the RF, analog, MAC and PHY functions in a singleCMOS die. The receiver achieves a sensitivity of -73dBm and -95dBm at 54Mb/s and 1Mb/s, respectively.The transmitter is capable of transmitting +4dBm. The die occupies an area of 41mm2.
A fully-integrated direct-conversion CMOS 802.11b SoC is presented in Paper 5.3. This SoC integrates allof the radio building blocks, including the PA, loop filter, and the antenna switch, along with the analog anddigital PHY and MAC blocks. The receiver achieves a sensitivity of -88dBm at 11Mb/s. The transmitter iscapable of transmitting a nominal output power of +13dBm. The die occupies an area of 32.2mm2.
A dual-band direct-conversion CMOS 802.11a/b/g transceiver is described in Paper 5.4. It achieves an RXNF of 5dB and a TX EVM of -31dB while transmitting 1dBm at 5GHz. The chip occupies only 6mm2.
Another CMOS direct-conversion 802.11a/b/g transceiver is reported in Paper 5.5. It achieves an RX NF of4.2dB and a sensitivity of -94dBm at 6Mb/s and 5GHz. The die occupies 17.2mm2.
A BiCMOS SoC for bidirectional point-to-multipoint wireless digital-audio applications is described in Paper5.6. It utilizes the 863 and 915MHz bands. It achieves an RX current consumption of 3.8dB and a sensi-tivity of -94dBm for the U.S. 918 kb/s mode.
A dual-band frequency synthesizer for 802.11a/b/g with a fractional-spur averaging technique is describedin Paper 5.7. It achieves a 10kHz to 10MHz integrated phase noise lower than 1.25° rms for any of the syn-thesized channels.
A fully-integrated transformer-based RF front-end which integrates matching and T/R switch functions on theCMOS chip is reported in Paper 5.8. An example of the application of the technique to a Bluetooth IC isdemonstrated. It achieves a receiver sensitivity of -90dBm and a transmitter power of +2dBm.
Session: 5 [AP24] SESSION OVERVIEWWireless
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High-Speed and Oversampled DACs
Chair: Robert Neff, Agilent Technologies, Palo Alto, CAAssociate Chair: Zhongyuan Chang, IDT-Newave Technology, Shanghai, China
This session highlights the state-of-the-art in high-speed and oversampled DACs, including high-accuracysignal synthesis beyond 1GHz, and the doubling of sample rates for 6b-resolution DACs to 22GS/s. An over-sampled ADC/DAC-based power amplifier and an RF power detector are also presented.
Signal resampling is a common technique for improving accuracy in DACs, resulting in an RTZ waveform.In baseband DACs, resampling results in unwanted signal content above the Nyquist frequency. Severalrefinements to resampling techniques are presented. The authors of Paper 6.1 employ two identical time-interleaved RTZ 15b DACs, resulting in an NRZ waveform with exceptional signal accuracy. An RTZ DACwith wideband performance, generating waveforms in the second and third Nyquist bands and allowingdirect synthesis of RF waveforms up to 2GHz, is presented in Paper 6.2. In this DAC, the RTZ signal is adesirable resampling artifact, resulting in less sin(x)/x distortion.
These GS/s high-resolution DACs require expensive data sources with high-speed memory and/or digitalsignal processing and high-speed high-power data I/O. The circuit described in Paper 6.3 solves this exter-nal computation and I/O problem by integrating direct-digital frequency synthesis on-chip with a 1.7GS/sDAC.
A minimum-complexity circuit-design approach, demonstrating that a state-of-the-art high-accuracy 500MS/s CMOS DAC can be implemented with a conventional architecture, is presented in Paper 6.4.
An oversampled RTZ DAC, presented in Paper 6.5, demonstrates that two time-interleaved DACs with twophase-adjusted data interpolators can synthesize 11.9b-accurate signals in a 29MHz bandwidth. Thesearchitectural innovations are primarily in the digital domain, and improve total DAC performance.
It is a challenge to simultaneously achieve both high accuracy and high efficiency in audio power amplifiers.The implementation in Paper 6.6 uses a )* modulator to create a bitstream to drive a class-D amplifier.Directly applying this bitstream would result in switching the amplifier at speeds up to 3MHz, which wouldresult in low power efficiency. A technique to reduce the maximum frequency component to around 450kHz,and meeting both design goals, is introduced.
A 22GS/s 6b SiGe BiCMOS DAC, presented in Paper 6.7, is over twice as fast as any 6b design previously published.
The power detector presented in Paper 6.8 improves on the state-of-the-art in offset control for RF-power-detector applications, demonstrating performance that is even superior to laser-trimmed parts. It uses achopping technique previously seen in precision amplifiers and mixers.
Session: 6 [AP26] SESSION OVERVIEWAnalog
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Multimedia Processing
Chair: Lee-Sup Kim, KAIST, Daejeon, KoreaAssociate Chair: Masafumi Takahashi, Toshiba, Kawasaki, Japan
The demand to meet new standards within a tight power budget in emerging multimedia applicationsrequires highly integrated and power-optimized solutions.This session presents a variety of subsystems withadvanced multi-media features such as an H.264/AVC single-chip encoder for high-definition (HD) video, alow-power MPEG-4 advanced-simple-profile (ASP) audio/visual CODEC for HD applications, anH.264/MPEG-4 audio/visual CODEC for mobile applications, a stream processing unit of the CELL proces-sor, a triple-CPU mobile-application processor, a multimedia-applications processor for wireless devices,and an analog CMOS auditory filter bank, for speech recognition.
Paper 7.1 implements the first H.264/AVC encoder IC. A four-stage pipelined architecture and 1.3TOPSmotion estimators are used to achieve 720p HD video encoding (1280x720 @ 30 frames/s). The encodedvideo quality is competitive with reference software requiring 3.6 TOPS on a general-purpose processor-based platform.
An MPEG-4 video/audio CODEC for 720p HD mobile applications is presented in Paper 7.2. This is the firstimplementation to support MPEG-4 ASP, including B-VOPs. High-performance and cost-effective architectures are proposed.
Paper 7.3 presents an H.264/MPEG-4 video/audio CODEC LSI for mobile applications. This LSI adopts module-wise dynamic voltage/frequency scaling for the first time. It operates even during the voltage/frequency transition with no performance overhead, by using a dynamic de-skewing system and anon-chip voltage regulator with slew-rate control.
The micro-architecture of a 4-way SIMD stream-processing unit of the CELL processor is described in Paper7.4. It minimizes instruction latency and provides fine-grain clock control to reduce power. Software con-trols data movement and instruction flow, and improves data bandwidth and pipeline utilization.
In Paper 7.5, three CPUs, a DSP, and several accelerators are integrated into a single chip for digital TV,web browser, and 3D graphics applications. Several techniques to increase memory bandwidth and toreduce power consumption are also described.
A new generation of multimedia-application processors is presented in Paper 7.6. An efficient set of leakage-reduction techniques, including power gating, voltage scaling, and dual Vt are adopted to reducethe standby current.
Paper 7.7 presents an ASIC that emulates the inner ear using a bank of 100 exponentially distributed asym-metric band-pass filters. Output is encoded into an auditory-nerve-like pulsed format available at a digitalport.
Session: 7 [AP28] SESSION OVERVIEWSignal Processing
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Session: 8 [AP32] SESSION OVERVIEW
Circuits for High-Speed Links and Clock Generators
Chair: Hirotaka Tamura, Fujitsu Laboratories, Kanagawa, Japan Associate Chair: Sung Min Park, Ewha Womans University, Seoul, Korea
The scaling of transistor expands the territory of CMOS high-speed links toward consumer electronics, andhigh-end communication applications. The data rate has already reached 10Gb/s, and is approaching40Gb/s. The keys to this technology trend are the continuous improvement in performance of component-level circuits and their integration. The papers in this session present progress in the performance and inte-gration levels of key components like MUXes, DEMUXes and clock generators.
The authors of Paper 8.1 present a 0.13'm CMOS 40Gb/s transmitter that is composed of a 16-to-1 MUX,and clock, and a PRBS generator. Shunt-and-double series-inductive peaking, and negative feedback, areused to enhance the bandwidth of the MUX. The 38.4Gb/s (231-1) PRBS transmitted eye has a differentialvoltage swing of 549mVpp, rise time of 14ps, and clock jitter of 0.65psrms, and 4.9pspp. A 4-to-1 MUX and a1-to-4 DEMUX in 90nm CMOS are described in Paper 8.2. The MUX and DEMUX operate from a 1.2V sin-gle supply, and draw 110mA and 52mA, respectively.
Distributed amplifier topologies realize the wide bandwidth that is needed to amplify high-speed serial sig-nals. In Papers 8.3 and 8.4, CMOS distributed amplifiers are described. An 80GHz distributed amplifier in90nm CMOS is featured in Paper 8.3. The amplifier exhibits 7.4dB gain with a 3dB bandwidth of 80GHz,using both a capacitor-coupled gate and low-loss coplanar waveguide. In Paper 8.4, a non-uniform down-sized distributed amplifier using 0.18µm CMOS transistors is discussed. The amplifier achieves a differen-tial forward gain of 7.8dB over a 25GHz bandwidth, and exhibits an IIP3 of +4.7dBm while drawing 30mAfrom a 1.8V supply.
High-speed serial links mandate reliable clock generation; the focus of Paper 8.5 is a 1V 24GHz PLL in0.18µm CMOS. The PLL uses transformer-feedback and a stacked frequency divider. The PLL provides anin-band phase noise of 106.3dBc/Hz at 100kHz offset, and an out-of-band phase noise of 119.1dBc/Hz at10MHz offset, while consuming 17.5mW and occupying an area of 0.55mm2.
The authors of Papers 8.6 and 8.7 present spread-spectrum clock generators for serial ATA that currentlysupports 3Gb/s serial transfer. Paper 8.6 describes a 0.15'm CMOS spread-spectrum clock generator thatuses a fractional PLL controlled by the )* modulator. The clock generator achieves a peak spurious reduc-tion level of 20.3dB, and a random jitter of 8.1ps in 250-cycle averaging period. A technique that uses 10multi-phase clocks and a )*,modulator is discussed in Paper 8.7.The deterministic jitter due to spread spec-trum is 25ps, and the amount of spreading exactly conforms to the serial ATA specification.
Wireline
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Session: 9 [AP34] SESSION OVERVIEW
Switched-Capacitor Delta-Sigma Modulators
Chair: Willy Sansen, Katholieke Universiteit, Leuven, BelgiumAssociate Chair: Andrea Baschirotto, University of Lecce, Italy
In this session, several advances are presented in the design and realization of A/D converters, based on a)* modulator -)*M) implemented with switched-capacitor techniques.
The major developments are the implementation of low-voltage (0.6V) circuits, the use of 90nm CMOS tech-nology, the realization of wideband )*Ms, and the realization of two audio )*Ms (DR>100dB) in a 20kHzbandwidth.
The switched-RC integrator technique, which enables the operation of the )*M at 0.6V without any clock-boosting, bootstrapping, or switched-opamp techniques, is introduced in Paper 9.1. In addition, low-voltageoperation is enabled by the use of a feedforward topology to reduce the dynamic range at the integrator out-put node. These techniques are applied to a 2-2 MASH )*M that achieves 82dB DR in the audio band, with1mW power consumption.
In the next two papers, the authors report the implementation of two )*Ms in 90nm technology. The mainissue addressed in Paper 9.2 is that a large power reduction is achieved in a 2nd-order multibit )*M by trun-cating the quantizer output while digitally shaping and cancelling the relative error. The target of 58dB DR ina 2MHz bandwidth is achieved with good capacitor matching, which does not require the implementation ofany DEM circuitry. The second )*M in 90nm CMOS technology (Paper 9.3) reduces the power consump-tion by using a single-amplifier double-sampling 2nd-order 5b topology. The typical drawback of double-sam-pled structures is the path mismatch effects, which are alleviated by a proposed single-capacitor technique.This gives a 66dB DR in a 1.94MHz bandwidth, with1.2mW power consumption.
Wideband )*Ms with significant DR performance are reported in the next two papers. In Paper 9.4, a 2-2-0MASH structure (with a 3b last stage) is proposed to achieve a 100dB SNR in a 1MHz bandwidth.The powerconsumption of the complete ADC (including )*M core, input buffer, reference voltages, and decimator fil-ter) is 475mW from a dual supply (2.5V/5V).
In Paper 9.5, several background digital linearization and noise-cancellation algorithms are introduced toimprove the analog performance (in particular SNDR and SFDR) over a very large bandwidth. A 2-0 MASHstructure is used, where the 1st stage uses a 4b quantizer (with DEM linearization) and the 2nd stage uses a9b pipeline. The structure operates with an 80MHz sampling frequency, and achieves 75dB DR, and morethan 87dB SFDR, in a 10MHz bandwidth. The digital algorithms are demonstrated to not degrade the ana-log performance.
Finally, the same overall architecture, but with different implementations, is used in the last two papers. Theycouple an input continuous-time stage with a switched-capacitor 2nd stage, and a 17-level quantizer toreduce clock jitter, which affects DAC feedback in continuous-time systems.
A fully-differential structure is described in Paper 9.6. It focuses on a hybrid tuning circuit to keep the RCproduct constant across process, supply, and sampling-rate variations. In addition, the feedback DAC ISI iseliminated by an RTZ scheme applied on the error current of the CT integrator. This allows a significant106dB DR with 18mW power consumption (including decimator filter) in a 0.35'm CMOS technology.
An interesting solution for achieving high DR and high linearity with a single-ended input is proposed inPaper 9.7. The input stage includes an accurate CM control and a chopper structure. In this way, a 102dBSNR is achieved in the audio band with about 38mW power consumption in a 0.18'm CMOS technology.
Analog
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Session: 10 [AP36] SESSION OVERVIEW
Microprocessors and Signal Processing
Chair: Georgios Konstadinidis, SUN Microsystems, Sunnyvale, CAAssociate Chair: Sung Bae Park, Samsung, Yongin-City, Korea
Microprocessor-frequency scaling is coming up against fundamental barriers that have the potential to limit future performance gains for traditional single-processor systems. In this session, new designs are pre-sented that incorporate extensive parallelism, or multiple processing units, to enhance overall chip performance, without the difficulties associated with higher clock frequencies. This trend is clearly illustrat-ed in this session, where all eight papers describe chips containing multiple processor cores of varioustypes. One of the most significant performance-limiting barriers is power consumption. Overheating andpower issues have plagued recent processors, causing frequency reductions or product cancellations. Newapproaches to exploiting one of the most promising techniques for power reduction, namely dynamic volt-age and frequency scaling, are discussed in this session.
Implementation of a next-generation Itanium® processor is described in Paper 10.1. It is comprised of twodual-threaded cores integrated on the same die with a 26.5MB cache in a 90nm. In addition to performanceimprovements, this design reduces susceptibility to soft errors, and improves power efficiency through low-power techniques and active power management.
The first-generation multi-core SoC CELL processor, described in Paper 10.2, combines eight streamingprocessors on a chip providing a high-performance platform for multimedia and streaming workloads Theseprocessors are designed with features specifically targeted for certain applications, saving power and areaby this narrower application focus. Implemented in a 90nm SOI process, the chip incorporates extensivepower- and thermal-management techniques.
The processor described in Paper 10.3 also follows the dual-core approach to improving performancethrough parallelism. This fourth-generation SPARC® processor combines two enhanced third-generationcores with expanded caches and an on-chip 2MB L2 cache. Fabricated in a 90nm technology, it operates at1.8GHz from a 1.1V supply.
Another approach described in Paper 10.4 (BlueGene/L) uses low-cost small power-efficient processors ina massively-parallel fashion. This complex SoC ASIC includes two processor cores, embedded DRAM,SRAM and custom logic, achieving a high-power/cost-performance trade-off, suited to its role as a buildingblock of IBM's BlueGene/L supercomputer.
Graphics and multimedia processing for portable and consumer applications are addressed in Papers 10.5and 10.6. An SoC targeting systems such as game consoles, digital television, and next-generation DVDplayers, is described in Paper 10.5. The 50mm2 chip, containing 17.9M transistors, is fabricated in 0.13'mCMOS. It integrates an ARM11 RISC processor with a dedicated 3D graphics pipeline, and supports analog-video outputs.
An IC that supports high-resolution graphics for mobile multimedia applications is discussed in Paper 10.6.This chip combines a RISC core with an SIMD graphics engine. Power-management techniques enablegraphics performance of 50Mvertices/s and 200Mtexels/s while dissipating 155mW in 0.18'm CMOS.
The trend toward single-chip multiprocessors for media applications is continued in Paper 10.7. It describesthe integration of four 8-way VLIW processors in a 122mm2 chip fabricated in 90nm CMOS.
Lastly, in Paper 10.8, multiple reconfigurable logic blocks are integrated with a VLIW RISC processor andreconfigurable I/Os to improve performance and power efficiency.
Digital
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Ultra Wideband Solutions
Chair: Ali Hajimiri, California Institute of Technology, Pasadena, CAAssociate Chair: Tom Schiltz, Linear Technology, Colorado Springs, CO
The last decade has seen an exponential increase in the demand for higher bit rates for existing and emerg-ing applications. Until recently, this has been addressed by the gradual migration from low-speed dial-up tohigher-speed Ethernet and fiber. Unfortunately, these broadband solutions require a wired connection thatlimits users' mobility. Emergence of broadband high-quality video and audio applications as well as high-speed home and enterprise networking makes it highly desirable to achieve similar bit rates in a wirelessfashion. This has led to many efforts toward wireless networking solutions, e.g., 802.11x. Although they pro-vide wireless connectivity, most are limited to bandwidths of several tens of Mb/s. However, instantaneousbit rates as high as 1Gb/s are desirable in many applications. Such an increase in data-handling capacitynecessitates substantially more-aggressive approaches to signaling method, system design, and circuitdesign. Several approaches have been proposed to increase bit rates using broader bandwidths (e.g., 3 to10GHz) and/or moving to higher frequencies (e.g., 24GHz and 60GHz). Recently FCC's blessing of two newUWB standards, and the availability of several higher frequency ISM bands, will likely reinvigorate newefforts in the UWB arena. This session explores the most-recent developments in UWB, and offers a broadset of solutions, ranging from OFDM-based systems operating in the 3-10GHz band, to high-frequency mul-tiple-antenna systems taking advantage of the higher bandwidth and array gain.
The receiver chain and the frequency-generation block of an integrated UWB radio in SiGe BiCMOS are pre-sented in the first two papers. A wideband LNA, a mixer, and the IF blocks, with an overall NF of 7.5dB, arefeatured in Paper 11.1. The frequency-synthesis block is presented in Paper 11.2. Frequency hopping isachieved using two PLLs and a single-sideband mixer with a fast switching time of 1ns.
A broadband CMOS frequency synthesizer capable of switching between different frequencies from 3 to8GHz with 1ns settling time is described in Paper 11.3. A semi-dynamic regenerative frequency divider forOFDM-based UWB systems is featured in Paper 11.4.
A direct-conversion UWB receiver in SiGe BiCMOS that operates from 3.1 to 8.1GHz is reported in Paper11.5. It has a peak conversion gain of 52dB with a NF between 3.3 and 4.1dB. The receiver has an on-chipfrequency synthesizer generating the LO from 3.4 to 7.9GHz.
Multiple-antenna systems promise many performance improvements for broadband systems. The next twopapers explore the numerous possibilities for higher speed using multiple antennas. A 5GHz multiple-anten-na receiver implemented in 90nm CMOS is described in Paper 11.6. It can be used to extend the range ofexisting multiple-antenna systems. It has full 360° coverage, and achieves 6dB SNR improvement due to thearray gain.
A fully-integrated four-element 24GHz phased-array transmitter in 0.18'm CMOS with integrated PAs, is fea-tured in Paper 11.7. With a peak-to-null power ratio of 23dB and an effective isotropic radiated power (EIRP)close to 1W, it supports bit rates in excess of 500Mb/s, bringing us closer to a wireless gigabit Ethernet solu-tion.
The final two presentations demonstrate integrated UWB transceivers in CMOS. The DSSS UWB trans-ceiver in Paper 11.8 covers the 3.1 to 5GHz band with a programmable pulse-shaping circuit on the trans-mit side and a NF of 4dB in 0.18'm CMOS. Finally, a 0.13'm CMOS transceiver is presented, in Paper 11.9,that achieves a NF in the range of 5.5 to 8.4dB across the three UWB sub-bands.
Session: 11 [AP38] SESSION OVERVIEWWireless
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Session: 12 [AP40] SESSION OVERVIEW
Optical Communications
Chair: Larry DeVito, Analog Devices, Wilmington, MA Associate Chair: Yusuke Ohtomo, NTT, Kanagawa, Japan
Communication using light signals over optical fiber holds great promise to lower costs for all data transportover both short and long distances. The huge bandwidth and favorable physical characteristics of opticalfiber beg to be exploited: In telecom networks, transmitting high-data-rate signals over long distancesbecomes practical; In computer systems, high-capacity interconnect, free from electromagnetic interferenceand awkward bulky copper cables, is enabled by parallel optics. But, of course, practical details limit cost-effective commercial solutions. In this session, several advances in the practical art of sending and receiv-ing optical signals, are presented. Inevitably, such advances will lead to exciting new cost-effective telecomservices and higher-performance computer systems.
A 10Gb/s laser driver with impedance-matched electrical output is presented in Paper 12.1. It enables theuse of a low-cost TO-can package for the laser. Previously, the hostile electrical characteristics of such alow-cost package have impaired the optical eye of the transmitted optical signal due to reflections of theelectrical-drive signal.
A step towards short-distance high-capacity interconnections within a single computer system, using paral-lel optical fibers assembled in a ribbon format, is addressed in Paper 12.2. A backplane comprising 48 par-allel channels, each operating at a data rate of 20Gb/s, is the goal of this laser driver. A low-cost vertical-cavity surface-emitting laser (VCSEL) has speed limitations that are overcome in this circuit by using pre-emphasis on the electrical-drive signal.
An astonishing new idea for long-haul telecom applications is described in Paper 12.3. Two optical carriersin quadrature are combined to compensate chromatic dispersion in the fiber: each optical carrier is modu-lated with a predistorted duobinary signal. This paper demonstrates the practicality of the high-speed signalprocessing needed for this system to transmit 10Gb/s data over 400km of fiber.
In Papers 12.4 and 12.5, a significant increase in the data rate of burst-mode communication for passiveoptical networks (PONs)is reported. This holds the promise of delivering high-data-rate connections to thehome. A 1.25Gb/s optical front end is demonstrated in Paper 12.4. It tolerates bursts of widely differentamplitudes and settles in 20 unit intervals(UIs). The first monolithic 10Gb/s burst-mode CDR with a lock timeof 5UIs is presented in Paper 12.5. These circuits both represent enabling technologies for low-cost PONimplementation.
A continuous-tuning CDR for the range of 12.5Mb/s to 2.7Gb/s is presented in Paper 12.6. Unaided acqui-sition of any data rate provides unprecedented flexibility in the provisioning of metropolitan-area networks.Alien data rates can now be transported over the public network without first being translated into a telecomstandard format. This, of course, will lower the cost for end users.
The final two papers in this session are short papers. A new peak-detector circuit idea that enables imple-mentation of very-fast offset compensation in a 3.125Gb/s optical-receiver limiting amplifier is introduced inPaper 12.7. The peak detector, implemented in 0.18'm CMOS, dramatically improves the trade-off betweensettling time and data-dependent jitter.
A positive-feedback boot-strap circuit to compensate the deleterious effects of both photodiode and ESDparasitic capacitances in a 2.5Gb/s fiber-optic transimpedance amplifier is shown in Paper 12.8. Inclusion ofESD protection provides more robust circuits, tolerant of real-world abuses.
Wireline
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Session: 13 [AP42] SESSION OVERVIEW
Sensors
Chair: Euisik Yoon, KAIST, Daejeon, KoreaAssociate Chair: Navakanta Bhat, IISc, Bangalore, India
This session highlights recent advances in a variety of sensors that interface the electronics world with the natural world. Natural signals are converted into electrical signals using integrated sensing elementswith on-chip signal-conditioning electronics. System-on-a-chip mixed-signal integration enables on-chip calibration to achieve advances in higher accuracy, as well as to enable a significant amount of digital processing for intelligent decision making.
The papers in this session illustrate this process: How sensing elements can be realized in conventionalCMOS technologies for magnetic sensing, for finger-print sensing, for environmental sensing, for tempera-ture sensing and for inertial sensing.
There are multiple examples presented of the power of integrating a sensor with electronics: The first paper(13.1) realizes a smart CMOS temperature sensor with a 3+ inaccuracy of ±0.1oC. Advances in sensordesign combined with dynamic element matching and a low-offset ADC, lead to increased precision. InPaper 13.3 on a magnetic sensor, the ability to add coils along with an analog front end, enables a new ref-erence modulation and demodulation technique leads to in-situ calibration of the magnetic sensor element,to compensate for aging. In Paper 13.5, fully-integrated electronic calibration combined with four orthogo-nally coupled, 8-direction spinning-current Hall-plates, allows a solid-state compass. As described in Paper13.2, a single-chip CMOS magnetic rotary encoder integrates a split-drain MAGFET sensor array with on-chip mixed-signal electronics. As described in Paper 13.6, combining MEMS structures with )* closed-loopcircuitry enables a high-resolution accelerometer.
A prime example of the powerful consequence of combining sensor elements with electronics is provided inPaper 13.4, which describes a microsystem which is able to perform trace environmental monitoring ofheavy-metal contaminates such as lead, down to the level of 0.8 ppb.
Finally, there are two papers (13.7 and 13.8) that carry out on-chip image-enhancement preprocessing ona capacitive fingerprint-recognition sensor. In Paper 13.7, this is accomplished through the use of reconfig-urable column-parallel digital processors for adaptive filter operations; in Paper 13.8, the same task is donethrough an embedded 32-bit RISC micro-controller.
Imagers, MEMS, Displays
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Low-Power Wireless and Advanced Integration
Chair: Robert Mertens, IMEC, Leuven, BelgiumAssociate Chair: Francis Jeung, Brand in Chip, San Jose, Ca
Low-power wireless technologies and advanced integration continue to open up new opportunities in a vari-ety of applications. In the field of low-power wireless technologies the main challenges are the further reduc-tion of the power and the continued system miniaturization. This session illustrates that innovative new con-cepts such as low power SoCs, on-chip antenna integration and more efficient rectifier ICs strongly con-tribute to meet these requirements. Additional challenges in the nano era include design for manufactura-bility of such miniaturized systems while maintaining the signal integrity. As we enter the era of ambient intel-ligence more electronic systems will be integrated on mechanically flexible substrates such as plastic andtherefore new integration technologies need to be developed.
A rectifier IC for wireless power transmission with low-input RF power is reported in Paper 14.1. The ICachieves a 950MHz signal rectification at -14dBm input power corresponding to a 10m-distance communi-cation. In Paper 14.2 a wireless SoC, integrating a dual 433/868MHz transceiver a RISC micro-controller,an SRAM, a sensor ADC and a power management unit is presented.
In Paper 14.3, the polysilicon gated-nanowires integrated into a CMOS process are reported. Memory cellsbased on this concept are among the very few reported functional hybrid CMOS-nanowire cells working atroom temperature, with very low energy consumption (tens of pWs) and excellent scalability.
Three-dimensional integration schemes are proposed in Papers 14.4, and 14.5. In Paper 14.4 a new 3D inte-gration scheme is proposed utilizing local wireless interconnect (LWI) and global wireless interconnect(GWI). LWI transfers pulses utilizing resonant coupling of spiral inductors, with 1Gb/s, 0.5ns delay and sev-eral mW power dissipation while GWI realizes over 10GHz clock with electromagnetic waves using inte-grated antennas through stacked chips. In paper 14.5 a wireless interface by inductive coupling is proposedthat achieves an aggregate data rate of 195Gb/s among 4 stacked chips in a package with a power dissi-pation of 1.2W.
The substrate coupling in a 90nm CMOS technology is analyzed for frequencies above 1 GHz. The impor-tant result is that combined device-level and circuit-level analysis is required for substrate integrity beyond1GHz.
In paper 14.7, a novel design for manufacturability method is presented to create manufacturable-by-con-struction designs. Silicon results show 3 to 12% improvement in the yield using this design method as com-pared to a traditional design flow.
An RF CMOS down-converter with integrated on-chip antennas communicating over free space up to 5mseparation is demonstrated in Paper 14.8.
Finally an 8b asynchronous microprocessor fabricated using 32,000 low-temperature-processed poly-siliconthin-film transistors, transferred onto a plastic substrate is described in Paper 14.9. It draws 180'A from a5V supply while operating at 500KHz. The power consumption is 30% of the synchronous counterpartaccording to the simulation.
Session: 14 [AP44] SESSION OVERVIEWTechnology Directions
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Analog
ADCs, DC References, and Converters
Chair: Klaas Bult, Broadcom CorporationAssociate Chair: Venu Gopinathan, Texas Instruments
Power efficiency is a major concern for embedded ADCs in sub-micron CMOS technologies. The bulk of thissession highlights the progress made in addressing this problem in a wide range of Nyquist-rate ADCs. Thespeed of the ADCs presented in this session ranges from 1MS/s to 200MS/s, while their resolution rangesfrom 16b to 8b. The set of ADC papers is followed by a paper on a precision voltage reference with a largeprogrammable range and a low temperature coefficient. The session concludes with the presentation of aDC-DC converter having pseudo-continuous output regulation.
In Paper 15.1, a new ADC architecture enabling continuous digital background self-calibration, withoutinjecting a training signal or interrupting the signal path, is described. For a 16b 1MS/s cyclic-ADC, this algo-rithm reduces the required number of conversion cycles for self-calibration by 3 to 5 orders of magnitude.This is achieved without any additional analog circuitry.
The low-voltage operation required in 90nm CMOS technology is addressed by Paper 15.2, using switchedopamps and switched input buffers. Operating from a 1.2V supply, this ADC achieves a peak SNDR of52.6dB, while consuming 3.3mW of power. This performance is obtained without the use of boosted volt-ages.
A pipelined ADC with a power consumption that adapts automatically to the sample-rate is described inPaper 15.3. The power dissipation scales with the sampling rate by over 3 orders of magnitude, while main-taining a constant SNDR of 54 to 56dB over the full range. This is achieved by rapidly powering on and offthe opamps.
A judicious choice of the first-stage architecture of a pipelined ADC enables very good power efficiency, aspresented in Paper 15.4. A 10b 125MS/s ADC is demonstrated in 0.18'm CMOS technology, consumingjust 40mW of power.
In the final ADC paper of this session, Paper 15.5, a power-reduction technique is described. The reductionis achieved by shutting down the second-stage of a 2-stage opamp. The power efficiency is enhanced by anew rapid-recovery arrangement. This 8b 200MS/s ADC achieves state-of-the-art high-frequency perform-ance consuming just 30mW.
A precision voltage reference based on a floating-gate technology is presented in Paper 15.6. The referencehas a temperature coefficient of <1ppm/°C and an initial accuracy of 200'V. Unlike classical reference gen-erators, this circuit can output any voltage from 0.5V to 5V without loss in precision.
This session is concluded by Paper 15.7, where a regulated switched-capacitor DC-DC converter is pre-sented. A pseudo-continuous control enables continuous output regulation in all clock phases. This createsan attractive alternative to inductor-based DC-DC converters for low current applications, since thisapproach can be integrated on-chip.
Session: 15 [AP46] SESSION OVERVIEW
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Clock Distribution and Power Management
Chair: Hoi-Jun Yoo, KAIST, Daejeon, KoreaAssociate Chair: Sohichi Miyata, Sharp, Chiba, Japan
Clock Distribution is an essential component of synchronous digital design. Papers in this session addresstechniques for the distribution of low-jitter high-quality clocks across large digital systems on a chip. The priority of power reduction in current processor designs is well-known. Power management, including methods to measure power and temperature on-chip.
Clock distribution in advanced SoCs is a major theme of the first three papers. Clock distribution and clock-frequency control of the 90nm Itanium® processor are discussed in Papers 16.1 and 16.2, respectively. A clocking scheme for on-chip interconnections is presented in Paper 16.3.
A region-based active-de-skewing clocking system to reduce PVT-related skew is described in Paper 16.1.It utilizes clock verniers to allow up to 10% clock-cycle adjustment, and supports a continuously-updatingfrequency with <10ps of skew across PVT changes. A clock-generator system generating fixed- and variable-frequency clocks for adaptive power control is reported in Paper 16.2. Its frequency synthesizersdivide the fixed-frequency PLL clock in 1/64th cycle steps to track supply-voltage transients, resulting in a10% improvement in CPU performance.
Periodically-all-in-phase clocking and a deterministic synchronous bus wrapper for synchronized data trans-fer among different frequency cores are introduced in Paper 16.3. It supports dynamic voltage and frequen-cy scaling to obtain a maximum of 60% power reduction and 1.5 to 2X throughput increase in MPEG-4decoding.
Advanced power-management schemes such as power switching, dynamic voltage-and-frequency control,and voltage-domain stacking are discussed in the final four papers. An interesting circuit scheme, enablingthe stacked domains to operate at multiples of the supply voltage without a voltage down-converter, is pro-posed in Paper 16.4. Operation at 3.6V is demonstrated in the 0.18'm CMOS circuit with 93% energy effi-ciency.
In the chip presented in Paper 16.5, the dynamic range of voltage scaling is extended below 300mV by including sub-threshold operation in a 90nm CMOS chip. This ultra-dynamic voltage scaling leads to a 9-times energy saving over an ideal shutdown scheme. Fine-grained power-switch circuits to reduce stand-by power by a factor of 5500 with a 5% speed penalty, are presented in Paper 16.6. A double-switch schemeavoids power-on glitches and reduces current spikes by 38%.
An embedded feedback-control system on a 90nm Itanium® processor is described in Paper 16.7. It inte-grates a small microcontroller, firmware, ADC, and thermal sensors to measure power and temperature. Inaddition, it modulates voltage and frequency to meet the given constraints.
Session: 16 [AP48] SESSION OVERVIEWDigital
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RF Cellular ICs
Chair: David Su, Atheros Communications, Sunnyvale, CaliforniaAssociate Chair: Charles Chien, SST Communications, Santa Monica, California
At the current growth rate, the number of worldwide subscribers of cellular services is expected to exceed1.5 billion by 2007. Today, cellular services for voice communications are primarily based on 2G systems,such as GSM and CDMA. However, with the rising demand for data services, the emerging 2.5G and 3Gsystems such as EDGE/GPRS and UMTS/CDMA2000, will play an increasingly important role in enablingmultimedia services with feature-rich handsets. To support the enhanced functions in these handsets, RFcellular ICs must provide small-form-factor low-power solutions, while meeting stringent system-level com-patibility requirements.
The nine presentations in this session represent a snapshot of the recent advances in cellular integrated cir-cuits, ranging from highly-efficient power amplifiers to fully-integrated transceivers. It is shown in thesepapers that the continued scaling of silicon technologies can enable increased levels of integration andenhanced performance, while reducing overall system cost.
The first single-chip GPS receiver, that integrates both the baseband and RF functionalities in an advanced90nm CMOS technology, is presented in the Paper 17.1. As discussed in this paper, GPS functionality canbe integrated into a large digital system-on-a-chip solution.
RF buildings blocks for GSM are described in the next three papers. A very high-power GSM amplifier with36dBm output and 54% PAE in a 0.23'm silicon LDMOS technology is presented in Paper 17.2. A 0.18'mpolar-modulated CMOS GSM/EDGE power amplifier is featured in Paper 17.3. As an EDGE transmitter, thisPA can deliver 23.8 dBm with 22% PAE. A unique loop bandwidth-calibration technique for a fractional-Nsynthesizer is showcased in Paper 17.4. The calibration technique achieves better than 2 degrees rmsphase error.
The session continues with integrated transmitters and receivers. An all-digital GSM/EDGE transmitter inan advanced 90nm CMOS technology is demonstrated in Paper 17.5. This 1.2V 42mA polar transmitterconsists of a digitally-controlled oscillator with digital amplitude modulation. It meets the EDGE spectralmask with an EVM of 3.5%. As in Paper 17.1, the viability of scaling RF circuits in 90 nm CMOS technolo-gy is also demonstrated in Paper 17.5.
The first-published fully-integrated GSM/GPRS transceiver in a 0.18'm CMOS technology is presented inPaper 17.6. The quad-band transceiver features a low-IF topology with no external SAW filter. A 5th-ordercontinuous-time GmC filter with in-situ calibration, to achieve 2% tuning accuracy, is described in a com-panion paper (17.8).
Two direct-conversion receiver presentations round out this session. A 0.18'm CMOS direct-conversionUTMS down converter is presented in Paper 17.7. The down converter uses an LC filter to achieve a highIIP2 of 78dBm. A fully-integrated direct-conversion CDMA receiver in 0.25'm CMOS is described in Paper17.9. This receiver has a linearized LNA that enables a high IIP2 of 75dBm.
Session: 17 [AP50] SESSION OVERVIEWWireless
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Session: 18 [AP54] SESSION OVERVIEW
High-Speed Interconnects and Building Blocks
Chair: Vadim Gutnik, Impinj, Inc., Newport Beach, CAAssociate Chair: Michael Green, University of California, Irvine, CA
The demand for speed and performance in broadband systems continues to increase. Circuit designers arerising to the task by designing high-speed high-performance ICs, even in standard CMOS or BiCMOSprocesses. Moreover, there is a strong motivation in the market to use the existing infrastructures (e.g., FR4-dielectric boards, multi-mode fiber, legacy connectors, etc.), even as bit rates continue to increase. Thus,more pressure mounts to overcome the non-idealities of the transmission channels. In this session, a num-ber of papers address this challenge: equalization circuits are presented in two papers, one for copper, onefor multi-mode fiber. Methods in which frequency modulation is employed to overcome speed limitations inthe silicon are described in two other papers. Challenges associated with testing state-of-the-art trans-ceivers, generating high-speed (PRBS), and measuring the data eye on-chip, are addressed in anotherthree papers.
Equalization methods used in 10Gb/s receivers are presented in Papers 18.1 and 18.2. The authors ofPaper 18.1 describe a 0.13'm CMOS implementation of an analog adaptive equalizer that can compensatefor the loss in up to 30 inches of transmission line on an FR4 board, while dissipating only 25mW. A 0.12'mCMOS implementation of a 7-tap FIR equalizer compensates for the dispersion in up to 600m of a multi-mode optical fiber. This circuit dissipates 325mW.
The 0.13'm CMOS 10Gb/s eye-opening monitor in Paper 18.3 operates from 1Gb/s to 12.5Gb/s, consum-ing 330mW from a 1.2V supply. This circuit maps the input eye to a 2-dimensional bit-error diagram with68dB mask-error dynamic range.
The authors of Paper 18.4 present an 80nm CMOS quad optical transceiver that transmits 10Gb/s per chan-nel over multi-mode optical fiber. Each driver consumes 2mW from a 0.8V supply, and a VCSEL requires7mA from a 2.4V supply. The receiver, excluding the output buffer, consumes 6mW from a 1.1V supply perchannel, and features a transimpedance gain of 10.1k
In Papers 18.5 and 18.6, wireless-circuit architectures are borrowed that are based on modulation tech-niques for enhanced broadband performance. Paper 18.5 uses frequency interleaving to provide less sen-sitivity to clock jitter in an interleaved-sampling architecture. This circuit, realized in a 0.25'm CMOSprocess, occupies 4mm2 and dissipates 1W. Paper 18.6 describes a technique in which the transmitted datasignal is modulated to create two independent high-speed channels. This circuit, realized in a 0.18'mCMOS, achieves an aggregate data rate of up to 3.6Gb/s per pin, and dissipates 92mW.
A 40Gb/s 27-1 PRBS generator using a SiGe BiCMOS process, is described in Paper 18.7. This designmakes use of a low-voltage logic family that allows 2.5V supply, and dissipates 550mW. Paper 18.8 pres-ents a 72Gb/s 231-1 PRBS generator using a SiGe process with a 3.3V supply. This circuit dissipates 9.28W.
Wireless
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Session: 19 [AP56] SESSION OVERVIEW
Imagers
Chair: Abbas El Gamal, Stanford University, Stanford, CaliforniaAssociate Chair: Hirofumi Sumi, SONY Corp., Japan
This session highlights recent advancements in image sensors. Papers cover not only improvements inmainstream photographic and video applications, but also continue to demonstrate the extended range ofapplications that custom imagers can address.
Smaller pixels with good imaging characteristics are required for the mass markets of DSCs, camcorders,and camera phones. A CCD that contains the smallest pixel yet announced (1.56'm) and is optimized formobile still-image and video operation is described in Paper 19.1. The smallest pixel size for CMOS imagers(2.0'm) and a new approach for color filters that uses amorphous silicon to create interference-stack filtersis presented in Paper 19.2.
Three different high-dynamic-range techniques are presented in three papers from three different groups. A19.5b dynamic sensor that combines high-speed readout and multiple exposure times is presented in Paper19.3. A 100dB wide-dynamic-range sensor that uses one additional capacitor and one additional transistorper pixel to integrate the electrons that overflow during integration is described in Paper 19.4. In contrast,the sensor described in Paper 19.5 uses the leakage characteristics of the transfer gate during integrationto create a signal that is linear up to a threshold, and then logarithmic.
A 3D fabricated 1024x1024 sensor is described in Paper 19.6. It is created by combining the readout arrayon one wafer of SOI, with a 100%-fill-factor photodiode array through the use of a 2'mx2'm 3D via per pixel.This approach disconnects the sensing technology from the readout technology, and is an interesting direc-tion if it proves viable. A CMOS HDTV sensor, that uses a tapered reset technique to achieve low readoutnoise by design, is presented in Paper 19.7.
Three custom sensors have been developed for three different applications by three different groups, asdescribed in the final three papers of the session. The sensor described in Paper 19.8 was developed toaddress automatic target tracking and ROI extraction. The sensor consists of both an active pixel array forimaging, and a distributed horizontal and vertical passive pixel array for locating the target. A temporal-change threshold detector is presented in Paper 19.9 for use in low-power low-bandwidth surveillance-net-work applications. An array of single-photon avalanche diodes (SPAD), combined with a micro-scannerpackage, create an imaging system with an enhanced resolution of 64x64, as described in Paper 19.10. Itis used in a time-of-flight range finding application.
Imagers, MEMs, Displays
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Session: 20 [AP60] SESSION OVERVIEW
Processor Building Blocks
Chair: Atila Alvandpour, Linköping University, Linköping, SwedenAssociate Chair: Fumio Arakawa, Hitachi, Tokyo, Japan
CMOS technology shows every sign of sustaining the capability of providing functional and reliable transis-tors far below 70nm channel length. However, utilizing this capability for higher integration levels and largerchips requires solutions to a number of challenges, including increased power consumption, increased sub-threshold and gate leakage currents, and increased interconnect RC delay. This session includes sevenpapers describing low-power high-performance circuit techniques for processor building blocks. Blocks thatare discussed include multipliers, adders, and register-file storage arrays. Intra-chip communication is alsoa critical component in leveraging the speed and performance of these functional units. The final paper ofthe session proposes a differential-signaling scheme as an alternative to classic repeater-based wiring.
The first three papers present efficient multipliers, always a high priority in microprocessor design. Theauthors of Paper 20.1 describe an 8GHz floating-point multiplier utilizing a limited-switch dynamic logic withpower consumption from 150mW to 1.8W for 2 to 8GHz operation. A 2's-complement multiplier fabricatedin 90nm dual-Vt CMOS is presented in Paper 20.2. The multiplier delivers 110GOPS/W at 1.3V with single-cycle operation at 1GHz. The design utilizes PMOS sleep transistors enabling ultra-low stand-bypower of 75'W. A double-precision multiplier for the 90nm SOI CELL processor presented in Session 10,is presented in Paper 20.3. The multiplier employs static partial-product compression utilizing replicated bitsfor 4.4GHz operation. In addition, an efficient clock-gating technique has been used to reduce the activepower.
In Paper 20.4, a 32b parallel prefix adder in 90nm CMOS is described, demonstrating the leakage-current-reduction capabilities of skewed CMOS logic, where high-Vt and thick-gate-oxide devices have been utilizedin performance-non-critical devices. The adder achieves sub-100nA device-leakage current and includes asingle-cycle-activation-from-standby mode. In addition, the adder data path includes improved sense-amplifier-based flip-flops and adapted latches.
The authors of Paper 20.5 present a dual-thread 18-port 128w x 82b FPU register file and a 22-port 128wx 65b integer register file on a dual-core Itanium® processor, utilizing embedded parity to provide soft-errordetection capability. In addition, the design integrates a charge-compensated thread switch and power-saving features, to operate at 1.1V and 400mW.
A method for copying memory cells to reduce the size of a 32b 64w 9-read- and 7-write-port pseudo dual-bank register file in 100nm CMOS is the focus of Paper 20.6. This has reduced the number of transistors in a memory cell by 70%, resulting in a register file, with 62% of the area of conventional register files.
Paper 20.7 describes circuit techniques for a bus-transceiver chip in 130nm CMOS using 10mm-long uninterrupted differential interconnects of 0.8'm pitch. The chip achieves 3Gb/s/ch using a pulse-width-pre-emphasis technique in combination with resistive termination with a power consumption of 6mW/ch froma 1.2V supply.
Digital
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Session: 21 [AP62] SESSION OVERVIEW
RF Trends: Above-IC Integration and mm-Wave
Chair: Ernesto Perea, ST Microelectronics, Grenoble, FranceAssociate Chair: Christian Enz, CSEM, Neuchâtel, Switzerland
This session highlights two important RF trends: the integration of various devices above the IC togetherwith advanced CMOS and BiCMOS circuits, and the design of high-frequency (60GHz to 110GHz) wide-band communication circuits. On one hand, the design of wireless circuits including above-IC bulk-acoustic-wave (BAW) resonators and filters opens the door to highly-integrated transceiver architectures for multi-band and multi-standard applications. On the other hand, there is now confirmed interest in 60GHz circuitsspurred in part by opening 7GHz of unlicensed bandwidth around 60GHz. This band was traditionally thedomain of III-V compound semiconductors. However, aggressive scaling of CMOS technology, and theincreasing capabilities of SiGe technology, make feasible the fabrication of highly-integrated CMOS or SiGemm-wave circuits for data-communication applications.
The focus of the first four papers in this session is on the use of RF-MEMS for both increasing the integra-tion level and reducing the power consumption of RF transceivers. An RF receiver architecture that inte-grates a combination of on-chip high-Q inductors and tunable MEMS varactors, together with an array ofparallel cantilever-beam mixer-filters is described in Paper 21.1. All the MEMS devices are fabricated bymicromachining in a standard RF foundry. Paper 21.2 demonstrates, for the first time, the feasibility of inte-grating BAW devices above a 0.25'm BiCMOS wafer, and connecting them to the RF circuits below. Thenew technology is illustrated by the design of an RF front-end lattice filter operating at 2.14GHz for WCDMA.A similar above-IC filter appears in Paper 21.3 for the integration of a complete RF front-end used in a zero-IF receiver for WCDMA. The front-end is integrated in a 0.25µm BiCMOS SiGe:C technology. It achieves again of 31.3dB, a 5.3dB noise figure, and consumes a total of 36mW. The authors of Paper 21.4 take advan-tage of the high-Q of FBAR BAWs to implement a very-low-power super-regenerative transceiver for wire-less-sensor-network applications.The receiver operates at 2GHz and consumes only 450µW from a 1V sup-ply, while achieving a #100.5dB sensitivity at 5kb/s for a 10-3 BER. The circuit is implemented in a 130'mCMOS technology and uses off-chip FBARs.
The second part of this session begins with Paper 21.5, in which a thin-film Cu/BCB technology with inte-grated inductors, resistors, and capacitors, for the realization of high quality on-chip and in-package Si-based passives, is presented. Thin-film SiP and SoC inductor and transmission-line performances are com-pared. A 60GHz direct-conversion receiver is presented in Paper 21.6 that features folded microstrip linesrealized in 0.13'm CMOS, and consumes 9mW from a 1.2V supply. The receiver provides a voltage gain of28dB with a noise figure of 12.5dB. The cascaded multi-stage distributed amplifier presented in Paper 21.7is integrated in a 90nm CMOS technology, and achieves better than 7dB gain with a bandwidth of 70GHz,10dBm output at the 1dB input compression points and 6.4dB average NF from 1 to 25GHz.The first D-band(110 to 170GHz) CMOS push-push VCO implemented in a standard bulk 0.13'm CMOS process is pre-sented in Paper 21.8. It features a phase noise of #107.6dBc/Hz at 10MHz offset, and power consumptionof only 8.4mW. The first integrated BiCMOS phase-locked loop for 60GHz applications, featuring a meas-ured PLL lock range of 53.3GHz to 55.7GHz, is described in Paper 21.9.
Technology Directions
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Session: 22 [AP64] SESSION OVERVIEW
PLLs , DLLs and VCOs
Chair: Roger Minear, Agere Systems, Allentown, PAAssociate Chair: Thomas Burger, Swiss Federal Institute of Technology, Zurich, Switzerland
The steadily increasing speed of chip-to-chip communication requires higher-performance PLLs, DLLs, andVCOs for high-frequency clock generation and clock recovery in multi-Gb/s transmitters and receivers.
Several key specifications must be considered in PLL design. First, PLLs must produce low phase noise, inorder to have superior jitter performance in receivers and transmitters. Second, the PLL must also consumeminimal power and area; clock generation and clock distribution are major contributors to overall power con-sumption.
Multi-phase PLLs for clock generation and clock distribution for multi-channel serial links are presented inPapers 22.1 and 22.3. The use of multi-phase PLLs in multi-channel serial links leads to very low power consumption and small area. Paper 22.1 includes a novel phase detector resulting in low phase jitter of <1psand a power consumption of only 20mW.
The PLL in Paper 22.2 uses a new charge-pump architecture to reduce the intrinsic deterministic jitter, lead-ing to 1.3ps rms jitter. The PLL occupies only 0.064mm2, while consuming only 15mW.
A self-biased PLL with current-mode filter for wide-frequency-range clock generation is presented in Paper 22.6. This PLL makes the bandwidth and jitter performance independent of the multiplication factor, temperature, and process variation. This is desirable for many applications, especially for multirate transceivers.
For very-low-jitter, PLLs with narrow bandwith, fully-integrated LC-VCOs are usually needed. A 44GHz differentially-tuned VCO in 0.12'm SOI CMOS technology is described in Paper 22.4. This VCO achieves aphase noise of #101.8dBc/Hz at 1MHz offset and consumes 7.5mW from a 1.5V supply.
Applications such as GSM and WCDMA require frequency synthesis with an absolute accuracy better than0.1ppm. DCXOs are very often used for this purpose. A DCXO that preserves the phase noise and stabilityof the crystal while permitting digitally-controlled tuning is described in Paper 22.5. Monotonicity of tuningand a step size of ~0.004ppm are achieved by a )*-modulation scheme.
DLLs have become an important component for clock synthesis. ADDLLs usually provide low power but suf-fer from large jitter. An all-digital DLL for clock deskewing in digital ICs is demonstrated in Paper 22.7. Itreduces power by nearly two orders of magnitude as compared with fast-lock mixed-mode DLLs, while alsoimproving jitter by 36%.
Wireline
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Session: 23 [AP66] SESSION OVERVIEW
Wireless Receivers For Consumer Applications
Chair: John Long, Delft University of Technology, The NetherlandsAssociate Chair: Tony Montalvo, Analog Devices, Raleigh, NC
Silicon IC implementations of emerging digital TV and radio standards are promising smaller lower-cost TV-and radio-tuner chips enabling mobility and feature-rich consumer electronics. In the TV world, smaller andlower-power tuners offer attractions like picture-in-picture and mobility, while substantially driving downcosts. Digital terrestrial radios boost audio quality to CD levels and extend new features to the listener, whilesatellite radio promises truly nationwide coverage.
Advancements in TV tuners are highlighted in the first four papers in this session. TV tuners are well-knownfor their extremely challenging technical requirements for RF designers. The tuning range encompasseshundreds of channels, leading to dynamic-range, local-oscillator-phase-noise, and spurious-signal-rejectionrequirements that are perhaps unmatched in our industry. The desire to add a tuner to hand-held portabledevices, such as laptop computers and wireless PDAs, adds power consumption to the list of critical designrequirements.
The session begins with a tuner designed for the digital-video-broadcasting-handheld (DVB-H) standard.The IC tunes to channels between 470 and 862 MHz, while consuming just 240mW, and does not requireexternal filters. A tuner for a mobile standard called Universal-Mobile TV (UMTV), which is intended fordeployment in PDAs, PCs, and mobile phones, is presented in the second paper (23.2). This chip featuresa low-noise amplifier (LNA) that includes an automatically-tuned integrated tracking filter to reduce thedynamic range required in subsequent circuits, and a low-IF topology to eliminate external passive filtering.
The digital-video-broadcasting-terrestrial (DVB-T) standard has especially stringent phase-noise require-ments. A tuner for DVB-T implemented in CMOS, using a superheterodyne architecture to avoid the track-ing filters used in traditional tuners, is described in the third paper of our session (23.3). The chip includes14b ADCs and digital channel filtering to eliminate the IF SAW filter often seen in superheterodyne radioreceivers.
A tuner designed for both U.S. and European set-top boxes that employs a dual-conversion topology is pre-sented in Paper 23.4. It uses a low-IF in order to satisfy difficult image-rejection requirements by filtering inthe digital domain.
Tuners for digital broadcast radio # one satellite and one terrestrial # are presented in the next two papers.An IC designed to satisfy Eureka-147, which is a European digital-audio-broadcasting (DAB) standard, thatincludes backward-compatibility with standard FM broadcast radio is the subject of Paper 23.5. The IC con-sumes only 150mW and uses a low-IF architecture to eliminate external passive filtering.
In Paper 23.6, a radio tuner for XM, which is the North American satellite radio standard, is described. The2.3GHz received signal is converted to a low-IF using the superheterodyne topology. The low-IF allows on-chip filters to be used which eliminate bulky external filters required by earlier receivers designed for thisapplication.
In the final paper of the session, a receiver front-end for digital-video-broadcast-satellite (DVB-S) applica-tions is discussed. This chip uses a low-noise PLL to generate a 10.2GHz local oscillator that converts two12GHz satellite channels to an intermediate frequency. The level of integration realized with this IC is thehighest published to date for this application.
Wireless
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Session: 24 [AP68] SESSION OVERVIEW
Baseband Processing
Chair: Albert Van der Werf, Phillips Research, Eindhoven, NetherlandsAssociate Chair: Yiwan Wong, ASTRI, Hong Kong, China
This Baseband Processing session covers ICs for a variety of digital communication systems ranging frompersonal-area networks to satellite communication. The reported advances in signal-processing technologyare in the area of error correction, increased application benefits of WLANs (802.11a/b/g), and ultra-wide-band communication. In addition, advances in integration offering high signal-processing performance, lowstandby power for cellular applications, and configurability for multiple standards, are also reported.Advanced channel-coding techniques utilizing low-density parity check (LDPC) codes are also reported, andapplied to both UWB and DVB-S2 applications.
A transceiver IC for impulse-radio UWB providing 62.5Mb/s is discussed in Paper 24.1. The IC consumes6.7mW and has a 2.72mm2 die area in a 0.18'm CMOS technology. An LDPC-COFDM-based transceiverIC for UWB is presented in Paper 24.2. The IC is capable of 480Mb/s consuming 523mW/575mW (TX/RX)and has a die size of 42.3mm2 in 0.18'm CMOS.
In Paper 24.3, a DVB-S2-compliant CODEC is presented including an LDPC CODEC. Two ICs are present-ed: one in 130nm and one in 90nm CMOS where the CODEC is integrated with ADC and demodulator. In130nm, the CODEC area is 49.6mm2 and consumes 1.5W at 90Mb/s; in 90nm CMOS, the CODEC area is15.8mm2 and consumes 700mW at 135Mb/s.
A reprogrammable EDGE-baseband and multimedia-handset IC integrating 6Mbit of embedded DRAM andprogrammable processors running at 156MHz is reported in Paper 24.4.The DRAM provides flexible instruc-tion storage allowing dynamic on-the-fly downloading of new multi-media applications. The IC measures57mm2 in 0.13'm CMOS, and draws 336mA for GPRS communication with multi media, and draws 690'Ain standby mode.
A multi-standard DSL central-office modem IC is presented in Paper 24.5. It supports 16 ADSL2+ modems,each running at 16Mb/s and configurable for multiple standards. The IC measures 145mm2 in 0.13'mCMOS, and consumes 2.7W from a 1.2V supply at 25°C.
A WLAN IC for video applications that supports PHY rates up to 108Mb/s and can handle 802.11a/b/g isdiscussed in Paper 24.6. The IC measures 51.9mm2 in 180nm CMOS, and consumes a maximum of 1.8W.In Paper 24.7 a wideband three-channel baseband and MAC processor for 802.11a/b/g is presented. TheIC occupies 70.6mm2 in 0.18'm CMOS, and consumes 2.1W when receiving three 54Mb/s channels simul-taneously .
Signal Processing
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Session: 25 [AP70] SESSION OVERVIEW
Dynamic Memory
Chair: Hideto Hidaka, Renesas Technology, Itami, JapanAssociate Chair: John Barth, IBM, Burlington, VT
Dynamic memory technologies have recently made tremendous progress in high-bandwidth applicationsand continue to represent the cutting-edge of memory technology intended for high-speed and high-densi-ty uses.We continue to see exploration of non-conventional memories such as SOI and dual-ported DRAMs,and high-frequency and low-power embedded memory designs. Sophisticated statistical analysis of corre-lated process parameters enables more accurate modeling of worst-case boundaries of device variation.
Recently-explored scalable capacitor-less DRAM on SOI is examined in Paper 25.1. A new 128Mb designhighlights a new mode of cell operation employing charge-replenishing to enhance retention characteristics.A proposed high-capacity array architecture also provides a virtually-static RAM mode, reducing contentionby allowing refresh interrupts.
Over 300MHz random access performance is a norm in today's embedded-DRAM arena. The authors ofPaper 25.2 show that precise tuning of circuits drastically improves the sensing margins and enables322MHz random-cycle operation. An effective dual-port approach to realizing a 400MHz random-cycle timeis presented in Paper 25.3, which utilizes a shallow-trench-capacitor cell. Array noise is reduced by mini-mizing data-line swing.
Evolution of CAM is another promising aspect of expanding embedded-memory applications. A new AND-type CAM structure is described in Paper 25.4. It provides a power-efficient approach yielding a competitiveperformance advantage over conventional NOR- and NAND-type CAM configurations.
High-density 1T1C DRAM requires consideration of statistical design when dealing with multiple-billions oftransistors. This topic is addressed this year by Papers 25.5 and 25.6.
A new concordant design methodology and associated tool for statistically incorporating device fluctuationsinto the SNR analysis in DRAM arrays is proposed in Paper 25.5 to precisely predict the minimum operat-ing voltage. 1.4V operation in a 100nm gigabit-DRAM is demonstrated. This statistical approach is not limit-ed to memory design, but is also well-suited to standard logic design.
A 2Gb DDR2 SDRAM, using 80nm technology, is described in Paper 25.6. Effective use of triple-level metaland statistical circuit analysis realizes a manufacturable die to cover many practical applications.
A 20GB/s interface using a precise quadrature PLL, controlled by a newly-devised tetrahedral oscillator, ispresented in Paper 25.7. A 256Mb DRAM chip, implemented in an 80nm technology, incorporates a cas-caded pre-emphasis transmitter to enhance the signal integrity in the multi-GHz regime.
Memory
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SRAM Memory
Chair: Alexander Shubat, Virage Logic, Fremont, CAAssociate Chair: Jinyong Chung, POSTECH, Pohang, Korea
Static Random Access Memories (SRAMs) have become increasingly important to a broad spectrum ofVLSI designs and applications, ranging from high-performance CPUs to low-power mobile handhelddevices. While technology scaling drives the density and performance of SRAMs, it also poses design chal-lenges in many technical areas. In this session, there is an array of papers that address some of the funda-mental issues in SRAM design and considers optimization schemes to meet various product needs. It cov-ers power and performance management, ultra-high-density SRAM design, low-voltage operation, reduc-tions in leakage current, and improvements in cell stability.
A 65nm CMOS 3GHz 70Mb SRAM is described in Paper 26.1.To achieve balanced power and performance,it introduces a dynamic-power switching scheme that allows the SRAM to integrate two different power sup-plies, based on the operating mode of the memory, whether read, write, or standby. In the column directionthe power-supply scheme uses various voltage levels to improve the cell read and write margins independ-ently, leading to a higher manufacturing yield.
A 256Mb synchronous-burst DDR SRAM design-based on a 0.16'm2 SRAM cell, using a stacked single-crystal silicon thin-film transistor, is introduced in Paper 26.2. The design adopts a hierarchical bitline archi-tecture to achieve optimal array efficiency with a robust sensing margin. A 280Mb/s data rate is achievedwith operating current of 17mA in a 61.1mm2 chip in an 80nm process technology.
Low-voltage operation of SRAMs is limited by static-noise-margin (SNM) degradation and loss of perform-ance due to higher-threshold transistors. These issues are addressed in Paper 26.3 by resorting to a 7-tran-sistor cell, thus allowing low-voltage operation at the expense of a 10% increase in area.
In addition to SNM in the read mode, the write margin is now limiting scaling. This topic is discussed inPaper 26.4, which uses write-margin expansion to achieve low-voltage operation.This expansion is achievedby VDD manipulation, and a special replica-tracking scheme. Operation at 450MHz is achieved with 7.8'A ofleakage standby current.
Leakage control is becoming of paramount importance in SRAM designs. In fact, leakage is perhapsdeemed to be the primary threat to SRAM scaling. A solution that offers 94% reduction in leakage, with only2% performance degradation, is described in Paper 26.5. The technique involves bit-cell ground control toreduce unwanted standby current.
Another important consideration in SRAM scaling is device-parameter fluctuation. This is specifically signif-icant when operating the device at very-low voltages, for example at 0.3V as described in Paper 26.6.Furthermore, at such low voltages, the soft-error rate needs to be significantly improved. The solution pre-sented uses a hidden ECC scheme that does not affect the access time.
SRAM caches continue to play a key role in supporting the improvements in microprocessor performance.Cache performance of 4.8GHz utilizing a 6-cycle pipeline and a 90nm SOI technology is described in Paper26.7. The largest on-chip SRAM-based cache memory reported to date is presented in Paper 26.8. The24MB level-3 cache memory operates from a 2GHz from a 0.8V supply while consuming 4.2W.
Session: 26 [AP72] SESSION OVERVIEWMemory
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Session: 27 [AP74] SESSION OVERVIEW
Filters and Continuous-Time )*Converters
Chair: Raf Roovers, Philips, Eindhoven, The NetherlandsAssociate Chair: Bill Redman-White, Southampton, United Kingdom
Achieving the optimum trade-off between the complexity of filtering to restrict analog bandwidth and thedynamic range in the data-conversion function with the lowest power, remains a central issue in many mobileand communication applications. Traditionally, filtering has been used in conjunction with gain control to limitthe resolution bandwidth of the ADC, and hence the power consumption, but the partitioning is constantlychanging as ADC technology advances.
In this session, we see how these issues are addressed using CT techniques while still pushing forward thestate-of-the-art in low-voltage fine-geometry processes. CT noise-shaping can yield valuable savings inpower in a )*,,ADC, and can also provide useful attenuation of interferes before the first sampling function.We also see, here, new techniques to reduce the power and voltage demands for providing classical filterfunctions for communication systems.
A multibit quantizer inside a )*,ADC improves dynamic range, but the power needed for the internal quantizer grows rapidly with the number of bits. A 2MHz BW 3rd-order converter in 0.13'm CMOS for cellular receivers is described in Paper 27.1. Using an internal-tracking 4b ADC with only 3 comparators, theoverhead is reduced significantly. The 78dB dynamic-range requirement in a digital-TV receiver isaddressed in Paper 27.2, by incorporating some gain control within the converter itself by means of a vari-able SC feedback DAC. The 1.3MHz 1.2V 0.11'm single-bit design with internal mixer also gains some ben-efits in jitter immunity from this approach.
The next two papers are CT )*,designs in 90nm CMOS. Showing another approach to power saving, a 4th-order noise-shaper employing passive poles and only 2 op-amps, is presented in Paper 27.3. Operatingat 267MHz, the design consumes 5.4mW from a 1.2V supply. In Paper 27.4, the issue of excess loop delayin CT modulators is tackled by adding a digital-compensation branch at the output. Pseudo-differential OTAstructures are optimized to give an input-referred noise of only 9nV/.Hz for cellular-baseband applications.
Complex )*,architectures are gaining popularity for I/Q receiver processing. Optimization of the signal-transfer function against the needs of out-of-band signal rejection is the subject of Paper 27.5. The modi-fied feedback modulator with variable gain has almost 90dB dynamic range for only 4.7mW. In Paper 27.6,the prime goal is to attain a single-sided bandwidth of 23MHz. The DR of 72.5dB and 45dB image rejectionfor only 42.5mW, permit direct digitization in a low-IF WLAN receiver with minimal additional analog func-tions.
The concluding papers of the session show that low-power filter techniques also continue to advance. Anew technique that trades power and noise floor dynamically in a high-linearity GSM baseband filter path isintroduced in Paper 27.7. Unlike traditional filter/AGC schemes, DR is enhanced by adding parallel pathsso that impedance levels and kT/C noise are traded with power consumption. The 0.45 to 2.6mW 5th-orderfilters occupy 1.2mm2 per path in 0.18'm CMOS. Finally, in Paper 27.8, it is shown that useful self-tuningfilters can be realized at extremely low voltages without resorting to special device thresholds. Employing anew transconductor design with body bias tuning, the 135kHz filter achieves a DR of 57dB with only 0.5Vsupply.
Analog
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Clocking and I/O
Chair: Dennis Fischette, AMD, Sunnyvale, CAAssociate Chair: Hannu Tenhunen, KTH Royal Institute of Technology, Stockholm, Sweden
Low jitter and low power are competing demands on the clock networks of systems running at GHz speeds.In addition, testability concerns require that low jitter be verified accurately, quickly, and at low cost. Thepapers in the first half of this session address high-speed clock generation, distribution, and testing.The sec-ond half of the session looks at three multi-Gb/s/pin I/O interfaces, and an innovative approach to interfac-ing today's deep-submicron chips with high-voltage legacy systems.
A multi-phase sampling system employing an analog DLL and two-level phase interpolation is presented inPaper 28.1. Redundancy and digital error correction reduce the effects of manufacturing mismatches by 6x,allowing sampling edges to be placed with 10ps accuracy. An analog on-chip jitter-measurement circuit thateliminates the need for a reference clock is described in Paper 28.2. It improves the measurement rangeand sensitivity using a combination of programmable delay elements and current sources, and reduces cir-cuit activity with an interleaving architecture.
In Paper 28.3, on-chip global clock-network wires are replaced by lossless package interconnects to dis-tribute a clock across a chip. The chip-package hybrid approach combines an on-chip DLL with package-level routing to reduce peak-to-peak clock jitter by more than 50%. In Paper 28.5, a differential global clock-network, based on distributed on-chip LC-tank oscillators, reduces jitter by an order of magnitude, whileusing three times less power at speeds ranging from 1.1 to 1.6GHz.
Pressing low-power concerns demand instantaneous clock frequency changes, a difficult feat for a PLL-based clock generator. A DLL-based clock generator for dynamic frequency scaling is described in Paper28.4. This 120MHz-to-1.8GHz clock generator in 0.35'm CMOS can change its output frequency in oneclock cycle with only 13ps peak-to-peak jitter at 1.3GHz.
In the second half of the session, high-performance I/O issues are presented. A 3Gb/s/pin performance fora 4-drop DRAM interface is demonstrated in Paper 28.6. Receiver equalization and digital offset-cancella-tion are employed, while a DLL loop with phase interpolation allows for data de-skew. In Paper 28.7, a pulsedAC-coupled receiver capable of 3Gb/s performance across a 15cm FR4 circuit-board interconnect with only15mW/pin and a 60mV input swing is presented. The receiver incorporates clock recovery from the datastream using a semi-digital DLL with phase interpolation. A parallel 6.4Gb/s/pin I/O interface with an aggre-gate bandwidth of more than 0.5Tb/s is described in Paper 28.9. The parallel I/O is incorporated into a first-generation CELL processor and must combat the twin challenges of floating-body effects in a 90nm SOICMOS technology, and reference-clock tracking.
In many applications, low-voltage circuits need to be interfaced to higher-voltage legacy circuits. The I/Obuffer design in Paper 28.8 tolerates 3x VDD input levels without gate-oxide reliability problems, using only 1xVDD transistors and a single VDD supply. A dynamic gate bias circuit auto-detects the received input-voltagelevels.
Session: 28 [AP76] SESSION OVERVIEWDigital
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Session: 29 [AP78] SESSION OVERVIEW
RF Techniques
Chair: Mario Paparo, STMicrolectronics, Catania, ItalyAssociate Chair: Qiuting Huang, ETH Zurich, Switzerland
New applications for silicon-based IC technologies are in the process of being defined in frequency bandswell above 10GHz, including short-range automotive radar in the 24GHz ISM band, local-multipoint distri-bution systems (LMDS) at 28 to 30GHz (IEEE 802.16) for broadband WLAN, and multiple bands between10 and 66GHz. In the first paper in this session (29.1), on-chip transformers are used extensively in theimplementation of a 3-stage 21 to 26GHz power amplifier, implemented in 0.18'm SiGe BiCMOS. A maxi-mum power-added efficiency (PAE) of 19% and output power of +23dBm are achieved # a very competitiveresult for circuits operating at these frequencies. Quadrature VCOs, used extensively in monolithic silicontransceivers, are described in Paper 29.5. The design presented extends the frequency range of such cir-cuits beyond 30GHz, with very low quadrature phase error.
The trend towards wideband wireless transceiver circuits, for applications such as 3G cellphones and UWBsystems, is supported by the circuit developments presented in Papers 29.2 and 29.4. In Paper 29.2 a newarchitecture for D/A conversion is applied to a high-performance direct-digital I/Q transmitter chip imple-mented in 0.13'm CMOS. It realizes better than #43dBc LO leakage and #47dBc image rejection.Quadrature signal generation over a wide range of frequencies is of critical importance to the successfuldevelopment of UWB transceivers. In Paper 29.4, a quadrature VCO embedded in a feedback loop with asingle-sideband mixer and two frequency dividers is used to implement a quadrature LO source that is con-tinuously tunable over the 0.75 to 2.2GHz range. The ±20% tuning range of the VCO is extended to ±50%with only a 0.01mm2 increase in die area.
Continuing evolution in the wireless-equipment domain requires extended battery life, reduced weight, andlower cost. This has stimulated the development of low-power RF building blocks in silicon. In Paper 29.6,an LC-VCO in 0.18'm CMOS is described, that operates at 2GHz with #103dBc/Hz phase noise at 100kHzoffset and just 1mW power dissipation from a 1.25V supply. A low-power LNA and a quadrature VCO suit-able for the 4 to 6 GHz WLAN band in 0.18'm CMOS are proposed in Paper 29.3. The LNA uses a gm-boosting technique to reach a remarkable 7.6dBm IIP3 and 2.5dB NF, while drawing just 1.9mA from a 1.8Vsupply. The Q VCO utilizes a modified Colpitts-oscillator architecture, and exhibits a 20% tuning range witha phase noise of #127dBc/Hz at 1MHz offset, while consuming 8.6mW.
A state-of-the-art fully-integrated low-power direct-conversion receiver for the 2.4GHz ISM band in 0.25'mCMOS is described in Paper 29.10. The receiver is intended for low-bit-rate communication and includes acomplete frequency synthesizer. It draws a total of 9.5mA from a 1.8V supply, and occupies less that 1mm2
of silicon area.
The opportunity to integrate calibration circuitry together with a wireless transceiver is open to designersusing silicon IC technology. Two excellent examples of auto-calibration schemes are presented in this ses-sion. As described in Paper 29.7 over 50dB of image rejection is achieved when I and Q mismatch is adap-tively minimized in a 90nm CMOS receiver chip targeted for GSM applications. A gear-shifting algorithm isemployed for fast acquisition of the adaptive filter coefficients. As demonstrated in Paper 29.9, when appliedto a WLAN direct up-conversion transmitter, automatic calibration can realize over 40dB of sideband sup-pression without the need for external circuitry or a high-precision receiver.
It is well-known that flicker noise constrains the performance of CMOS transceiver circuits. Presented inPaper 29.8, is a mixer which employs a new method of reducing the effect of 1/f noise. Reduction by an orderof magnitude, with no penalty in power consumption, chip area, gain or, linearity is described. A prototypeGilbert-type mixer implemented in a 0.13'm CMOS is presented as a proof of the concept.
Wireless
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Session: 30 [AP80] SESSION OVERVIEW
Displays and Biosensors
Chair: Tiemin Zhao, Reflectivity, Sunnyvale, CAAssociate Chair: Roland Thewes, Infineon Technologies, Munich, Germany
This session is the combination of two parts. The first part focuses on display technology and highlights amicrodisplay for portable electronics, and driver technologies for LCD TVs. The second part focuses onbiosensing, and highlights advanced approaches for neural-signal monitoring, and bio-molecule detection.
In Paper 30.1, the authors report a 360x200 CMOS-based microdisplay. It provides silicon light emitters foruse in conjunction with image intensifiers to meet the low-power requirement for portable electronics.
The authors of Paper 30.2 report the first panel-sized TFT-LCD scan driver with 768 outputs, which is use-ful for low-cost TFT-LCD modules for large-panel LCD TV applications.
An LCD column driver using a switched capacitor DAC is described in Paper 30.3. Each DAC performs itsconversion in less than 15's and draws less than 2.5'A.This architecture allows 10b independent color con-trol in a 17mm2 die, for the LCD television market.
The remaining papers deal with CMOS-based biosensor applications. In Paper 30.4, a three-dimensionalmicrosystem for monitoring neural activity on the basis of 256 sensor sites is described. Whereas data trans-mission in such systems represents a severe bottleneck if full analog-signal information is transferred, herean event-detection-based method decreases the volume of data by 92%.
Paper 30.5, a battery-driven low-power radio chip is described for a similar application area namely, FM-based wireless data transmission of neural signals. It requires only three off-chip components for operation.
In the final two papers, chips for detecting bio-molecules are described. In Paper 30.6 a chip is describedthat includes various sensors that operates in a sample solution with a wireless interface. Experimentaldetection of a DNA single nucleotide polymorphism is demonstrated.
Finally, in Paper 30.7, a 10x5 sensor array, fabricated in a 0.18'm CMOS technology, provides sensor sitesusing a variety of different detection principles. It demonstrates the versatility of an integrated sensors asenabling building blocks in important bioelectronics applications.
Imagers, MEMs, Displays,
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Session: 31 [AP82] SESSION OVERVIEW
Mass Storage
Chair: David Parlour, Xilinx, Pittsburgh, PAAssociate Chair: Ram Krishnamurthy, STMicroelectronics, Cornaredo, Italy
Advances in materials and solid-state electronics have led to evolving standards for removable optical stor-age media which provide the consumer with cheap reliable read/write mass storage. The existing CD andDVD formats provide 650MB and 4.7GB capacity, respectively, while the emerging Blu-ray format offers25GB single-layer capacity with a minimum 36Mb/s transfer rate. This session presents a variety of solutionsto the challenges of supporting many formats spanning a wide range of data-transfer rates, and disk capac-ities, in a low-cost consumer setting.
In Paper 31.1, a DVD write channel IC, extracts additional performance from an existing format with a volt-age-folding technique. Applied to the VCO loop filter, this reduces gain while expanding tuning range, thusenabling support for 1x to 16x write speed. A DLL-based clock-recovery technique is described in Paper31.2. It has improved noise-rejection and jitter-accumulation characteristics as compared to those of imple-mentations using PLLs. The technique is demonstrated to operate over both Blu-ray and DVD PRML readchannels. A single device that can read and write multiple formats (CD, DVD, and Blu-Ray) is presented inPaper 31.3. This IC provides backward compatibility to today's popular standards, while extending Blu-rayperformance to 7x read and write, compared to the 2x speed reported at ISSCC 2004.
Signal Processing
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Session: 32 [AP32] SESSION OVERVIEW
Advanced Array Structures
Chair: Eugenio Cantatore, Philips Research, Eindhoven, The NetherlandsAssociate chair: Koji Kotani, Tohoku University, Sendai, Japan
Large circuits, like stand-alone or embedded memories and addressing matrices for LED displays, that arebuilt as an array of devices, have a paramount importance in the electronics market.
Memory arrays have to face a number of technology and circuit challenges in order to keep pace with CMOStransistor scaling. These challenges are addressed in the first part of this session.
A detailed overview of the issues related to the scaling of conventional memories (DRAM, SRAM and Flash)and emerging memories (FeRAM, MRAM, and PRAM) towards nanometer scale size is presented in Paper32.1.
A 3T DRAM cell that combines very-low leakage with embedded gain is presented in Paper 32.2. This cellcan be potentially scaled down to nanometer dimensions, allowing low-power operation and a retention timelonger than 100ms, by using only 10 electrons per cell.
In the second part of the session, new large-area circuit concepts, based on organic- transistor technology,are presented. Organic transistors can be processed at low temperature on flexible and transparent sub-strates that can be integrated with displays or sensors to enable new applications.
A complete flexible display, based on an organic-transistor active matrix is presented in Paper 32.3. This dis-play embodies the concept of electronic paper and is addressed by integrated row drivers to reduce thenumber of interconnects and the display footprint.A functional prototype is presented.
A sheet-type scanner based on the integration of an organic photodiode array with an organic TFT-basedreadout circuit is described in Paper 32.4. The integration is achieved by stacking three flexible layers: onefoil with the image-sensor array with two foils containing the organic TFTs for the readout circuitry. A doubleword-line double-bit-line readout architecture allows a 5-fold improvement in speed and a 7-fold reduction inpower over claims reported earlier.
Technology Directions
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THE BTHE BAATTLE OF TTLE OF THE SIGMA-DELTHE SIGMA-DELTTA ADCSA ADCS
While Sigma-Delta Analog-to-Digital Converters have been considered to be a mainstream technology fornearly two decades, the 2005 International Solid-State Circuits Conference (ISSCC) will set a new stan-dard, with more than two sessions dedicated to such converters featuring oversampling techniques.
Switched-Capacitor circuit technology has been the long-standing favorite for implementing Sigma-DeltaADCs, and there are several examples which push the state-of-the-art in this area, extending the band-width to 24MHz for wireless-LAN applications, and pushing the technique onto 90nm processes for inte-gration in SoCs.
An alternative technique is to implement the Sigma-Delta modulator in the continuous-time domain.ISSCC 2005 will feature a full session dedicated to these architectures, adapted to a wide variety of appli-cations. The Continuous-Time Sigma-Delta A/D converters post some very remarkable power-efficiencynumbers(the special strength of this approach.
Rounding out the attractions for the Sigma-Delta fans are two Digital-to-Analog Converters implementedwith Sigma-Delta techniques.
Overall, one can conclude that Sigma-Delta converter techniques have now expanded beyond their tradi-tional low-speed/high-resolution/audio niche to become a pervasive technology touching a broad range ofevolving applications.
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VVOLOLTTAAGE AND GE AND TECHNOLOGY TECHNOLOGY CONTINUE CONTINUE TTO DRIVE ANALOG-CIRCUITO DRIVE ANALOG-CIRCUIT
INNOINNOVVAATIONTION
Integrated-circuit technology continues to drive itself down to finer and finer features, allowing more andmore transistors to be packed onto a single chip. For digital circuits, the benefits are great(more inte-gration, higher clock rates, and more processing muscle. With each generational advance in lithography,however, power-supply voltages are reduced. This presents a particular challenge to the analog-circuitdesigner, who is constantly battling to maintain her/his sensitive signal above the "noise floor".
In some cases, the analog circuitry can be moved to a separate chip with higher supply voltages, imple-mented in older technology. In other cases, however, the need to totally integrate is compelling: analogcircuits that can operate on supply voltages below 1V are required. Furthermore, these circuits must copewith other special challenges posed by fabrication processes at 90nm, and below: high leakage currentsand low gain, for example.
Much of today's analog-circuit innovation is directed toward solving the resulting problems. Correspondingly, presentations at ISSCC 2005 will reflect some of the advances in circuit techniques for very-deep-submicron design. In view of the difficulty of deep-submicronanalog design, architectures where digital complexity can be added in exchange for simplification of theanalog design are favored. Accordingly, Sigma-Delta converters are popular. But the Conference will alsoexplore effective more-analog implementations of high-speed pipelined A/D converters in 90nm CMOS, aswell as integrated filters. Such presentations show that, while their design is challenging, analog circuitsare certainly possible in 90nm technology!
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Advances in signal processing are often measured by increasing speed (or bandwidth) and increasingdynamic range (or resolution). Digital-to-Analog Converters (DACs) are a key element in the signal chain,taking the signal from the digital domain back to the "real world" of analog signals. In many cases, theDAC can be the ultimate performance-limiting link in the signal-processing chain.
This year, ISSCC features an entire session dedicated to DACs, establishing new benchmarks in performance. In the high-speed arena, the emphasis is on DACs that can directly synthe-size radio signals, a critical component in bringing more and more of the radio functionality into the dig-ital domain. At ISSCC 2005, DACs with clock rates up to 22gigasamples per second will be presented,DACs with the ability to directly synthesize signals up to 1GHz and beyond(critical for cellular telephonyand emerging broadband radio applications.
At the other end of the spectrum, Sigma-Delta techniques used in the new generation of high-performance Class-D audio amplifiers, provide a technique whereby a specially-processed digital signal directly drives the loudspeaker. A special version of this technique presented at ISSCC 2005. As usual, this year, ISSCC is the Conference at which innovation in electron-ics, whether audio or radio is normal fare!
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TRENDS IN IMATRENDS IN IMAGE SENSORSGE SENSORS
As will be reported at ISSCC 2005, advancements continue in image-sensor design, enabling increasedperformance and functionality in smaller packages. These developments demonstrate several importanttrends:
(1) Pixels continue to shrink to allow more pixels per unit area, improving the image-resolution-to-costtradeoff. A CCD imager with 1.56 micron pixels [19.1] and a CMOS imager with 2.0 micron pixels is to bepresented [19.2].
(2) Process scaling continues, unabated, following the digital-logic lead: Image sensors use standardCMOS processes down to 0.15 micron, along with enhancements to obtain color response and increasedresponsivity. Such scaling allows additional integration to permit the incorporation of ADCs, providingincreased functionality in signal-processing and control, to enable increased performance, and to enableadditional pixel-processing in the focal plane. Examples of this direction include pixel structures providingincreased dynamic range, 12b ADC for HDTV video operation, binning in a CCD for increased viewfindersensitivity for a cell-phone camera, and region-of-interest tracking to allow high-speed readout of infract-ing license plates [19.3]
(3) Applications of image sensors, beyond simple photography, continue unabated. Applications to be pre-sented at ISSCC 2005 include wide-dynamic-range imaging for automotive and surveillance, use 3D imag-ing with a precision of millimeters per meter, and motion detection. The increased possibilities enabled byincreased integration allow multi-functional pixel arrays to provide detection as well as imaging, allow mul-tiple exposures that can be fused into higher-quality images, and allow on-chip calibration to smoothly tran-sition the intensity response from a linear to a logarithmic transfer function [19.4]
(4) Advancements in processing, such as wafer bonding and wafer-to-wafer vias within the pixel, enablethe demonstration of a one-megapixel image sensor with processing behind every pixel [19.6].
And so, pixel pace proceeds, as presented in February, at ISSCC 2005!
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GLOSSARY
©COPYRIGHT 2004 ISSCC#DO NOT REPRODUCE WITHOUT PERMISSION
214
FIR Finite Impulse Response Filter
FLOTOX Floating Gate Tunnel Oxide
FM Frequency Modulation
FN Fowler Nordheim
FOM Figure Of Merit
FPGA Field-Programmable Gate Array
FSK Frequency Shift Keying
FSM Finite State Machine
GBW Gain-Bandwidth Product
GCA Gain-Controlled Amplifier
GDDR Graphics Double Data Rate RAM
GFSK Gaussian Frequency-Shift Keying
GIDL Gate Induced Drain Leakage
GMSK Gaussian Minimum Shift Keying
GOPS Giga-Operations Per Second
GPRS General Packet Radio Service
GPS Global Positioning System
GSM Global Standard for Mobile Communication
HBT Hetero-junction Bipolar Transistor
HCI Host Controller Interface
HD High Density
HDL Hardware Description Language
HDTV High-Definition TeleVision
HPF High-Pass Filter
HVCMOS High Voltage Complementary MOS
HVMOS High Voltage MOS
I/O Input-Output
I/Q In Phase and Quadrature
IC Integrated Circuit
IF Intermediate Frequency
IIP3 Input referred Input Third-order Intercept Point
IIR Infinite Impulse Response Filter
IMD Inter-Modulation Distortion
INL Integral Non-Linearity
InP Indium Phosphide
IP Intellectual Property
IPSEC Internet (Network) Protocol for Security
ISI Inter Symbol Interference
ISM Industrial, Scientific and Medicine Band
JPEG Joint Photographic Expert Group
JTAG Joint Test Automation Group
LAN Local-Area Network
LCD Liquid Crystal Display
LDCMOS Laterally Diffused Complementary Metal Oxide Silicon
LDMOS Laterally Diffused Metal Oxide Silicon
LDO Low drop-out
LDPC Low-Density Parity Check
LED Light Emitting Diode
LFSR Linear Feedback Shift Register
LNA Low-Noise Amplifier
LO Local Oscillator
LPF Low-Pass Filter
LSB Least Significant Bit
LSI Large Scale Integration
LTPS Low Temperature Poly Silicon
LVDS Low Voltage Differential Signalling
LVS Layout Verification to Schematic
MAC Media Access Controller
MASH Multi-stage noise shaping
MB-OFDM Multi-Band OFDM
MCM Multi-Chip Module
MCU Micro Controller Unit
MEMS Micro-Electro-Mechanical System
MIM Metal-Insulator-Metal
MIMO Multiple Inputs, Multiple Outputs
MMIC Monolithic Microwave Integrated Circuit
MODEM Modulator-Demodulator
MOS Metal-Oxide-Semiconductor
MOST MOS Transistor
MPEG Motion Picture Expert Group
MSB Most Significant Bit
MRAM Magnetic Random Access Memory
MTJ Magnetic Tunnel Junction
MUX Multiplexer
NF Noise Figure
NMOS n-channel MOS transistor
NMOST NMOS transistor
NPN Negative-Positive-Negative bipolar transistor
NRTZ Non Return To Zero
NRZ Non-Return to Zero (also NRTZ)
NVM Non Volatile Memory
NVRAM Non Volatile Random Access Memory
OFDM Orthogonal Frequency Division Multiplexing
OIF Optical Internetworking Forum
OIP3 Output referred Third-Order Intercept Point
ONO Oxide Nitride Oxide
OOK On-Off Keying
OSR Over-Sampling Ratio
OTA Operational Trans-conductance Amplifier
OTP One Time Programmable
P1dB 1dB gain compression point
PA Power Amplifier
PAE Power Added Efficiency
PAM Pulse Amplitude Modulation
PAN Personal Area Network
PCB Printed Circuit Board
PCM Pulse Code Modulation
PDA Personal Data Assistant
PFD Phase and Frequency Detector
PGA Programmable Gain Amplifier
PHEMT Pseudomorphic High-Electron-Mobility Transistor
PHY Physical Layer
PLA Programmable Logic Array
PLC Power-Line Communication
PLD Programmable Logic Device
PLL Phase-Locked Loop
PMOS p-channel MOS transistor
PMOST PMOS transistor
PNP Positive-Negative-Positive bipolar transistor
PON Passive Optical Network
POTS Plain Old Telephone Service
PPM Pulse-Position Modulation
PRAM Phase-change RAM
PRBS Psuedo-Random Binary Sequence
PRML Partial Response, Maximum Likelihood
PROM Programmable Read-Only Memory
PSD Power Spectral Density
PSK Phase Shift Keying
PSNR Peak SNR
PSRR Power Supply Rejection Ratio
PTAT Proportional to Absolute Temperature
PVD Physical Vapor Deposition
PVT Process, Voltage, Temperature
PWM Pulse-Width Modulation
QAM Quadrature Amplitude Modulation
QDR Quad Data Rate
QoS Quality of Service
QPSK Quadrature Phase Shift Keying
QVCO Quadrature Voltage Controlled Oscillator
QVGA Quarter Video Graphics Array
RAM Random-Access Memory
RF Radio Frequency
RISC Reduced Instruction Set Computer
ROM Read-Only Memory
rms Root Mean Square
GLOSSARY
©COPYRIGHT 2004 ISSCC#DO NOT REPRODUCE WITHOUT PERMISSION
215
RSA A public-key cryptographic system, named after: Ron
Rivest, Adi Shamir, and Leonard Adleman
RSSI Received Signal Strength Indicator
RTL Resistor-Transistor Logic
RTZ Return To Zero
RX Receiver
RZ Return to Zero (also denoted by RTZ)
SATA Serail AT-Attachment
SC Switched Capacitor
SCP Source-coupled pair
SCR Silicon Controlled Rectifier
SDRAM Synchronous Dynamic Random-Access Memory
SEM Scanning Electron Microscope
SER Soft Error Rate
SerDes Serializer/Deserializer
SFDR Spurious Free Dynamic Range
SFI Serdes Framer Interface
S/H Sample-and-Hold
SHA Sample-and-Hold Amplifier
SiGe Silicon Germanium
SILC Stress Induced Leakage Current
SIMD Single Instruction, Multiple Data
SIP Single Inline Package
SiP System in a Package
SMP Symmetric Multi-Processing
SNDR Signal-to-Noise and Distortion Ration
SNR Signal-to-Noise Ratio
SoC System on a Chip
SOI Semiconductor on Insulator
SONET Synchronous Optical Network
SONOS Silicon-Oxide-Nitride-Oxide-Silicon
SOS Silicon On Saphire
SPI System Packet Interface
SRAM Static Random-Access Memory
SSB Single Side Band
SSTL Stub Series Terminated Logic
TC Temperature Coefficient
TCAM Ternary Content Addressable Memory
TDDB Time Dependent Dielectric Breakdown
TDMA Time Division Multiple Access
TEM Tunneling Electron Microscope
TFT Thin-Film Transistor
T/H Track and Hold
THA Track-and-Hold Amplifier
THD Total Harmonic Distortion
THD+N THD plus noise
TOPS Tera Operations Per Second
TTL Transistor-Transistor Logic
TX Transmitter
UDTV Ultra-High Definition Television
UHF Ultra-High Frequency
UI Unit Interval
UIPP Unit Interval Peak-to-Peak
U-NII Unlicensed National Information Infrastructure
UMTS Universal Mobile Telecommunication System
UPROM Unerasable Programmable Read Only Memory
USB Universal Serial Bus
UWB Ultra WideBand
VCCS Voltage-Controlled Current Source
VCDL Voltage-Controlled Delay Line
VCO Voltage-Controlled Oscillator
VCVS Voltage-Controlled Voltage Source
VCXO Voltage-Controlled Crystal Oscillator
VCSEL Vertical Cavity Surface Emitting Laser
VDMOS Vertically diffused MOS
VGA Variable-Gain Amplifier, Video Graphics Array
VLIW Very Long Instruction Word
VLF Very Low Frequency
VLSI Very Large-Scale Integration
VSWR Voltage Standing-Wave Ratio
WAN Wide-Area Network
WCDMA wideband Code-Division Multiple Access
WEP Wired Equivalent Privacy
WiFi Wireless Fideleity; an interoperability certification for
WLAN products based on the IEEE 802.11 standard
WL Word Line
WLAN Wireless Local-Area Network
XAUI 10 Gigabit eXtended Attachment Unit Interface
GLOSSARY
©COPYRIGHT 2004 ISSCC#DO NOT REPRODUCE WITHOUT PERMISSION
216
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2005
PRESS KIT
ISSCC.ORG
Produced by: S3 Digital Publishing, Inc.
Lisbon Falls, Maine USA
