IP UNIDIG I E Manual Unidig

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User Manual

IP-Unidig-I-E

24 Line Input/Output withInterrupts and

LineSafeESD ProtectionIndustryPack


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Manual Revision: i Hardware Revision: C


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IP-Unidig-I-E

24 Line Input/Outputwith Interrupts and LineSafeTM

ESD ProtectionIndustryPack

GreenSpring Computers1204 OBrien DriveMenlo Park, CA 94025(415) 327-1200(415) 327-3808 FAX

ent contains information of proprietary interest tong Computers. It has been supplied in confidence annt, by accepting this material, agrees that the subjectl not be copied or reproduced, in whole or in part, nos revealed in any manner or to any person except tourpose for which it was delivered.

ng Computers has made every effort to ensure that taccurate and complete. Still, the company reserves take improvements or changes in the product describeument at any time and without notice. Furthermore,ng Computers assumes no liability arising out of theor use of the device described herein.

onic equipment described herein generates, uses, andradio frequency energy. Operation of this equipmential area is likely to cause radio interference, in whiser, at his own expense, will be required to take

easures may be required to correct the interference.

ngs products are not authorized for use as criticalts in life support devices or systems without theitten approval of the president of GreenSpring

s, Inc.

ct has been designed to operate with IndustryPackd compatible user-provided equipment. Connectionble hardware is likely to cause serious damage.

nSpring Computers, Inc.veda registered trademark of GreenSpring Computers.gistered trademark of GreenSpring Computers.registered trademark of Apple Computers.n i. Revised 11/13/95.


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Table of Contents

Product Description .......................................................................................................................... 1

VMEbus Addressing......................................................................................................................... 3

NuBus Addressing ............................................................................................................... ............. 7

ISA (IBM PC-AT) Addressing ......................................................................................................... 8

I/O Pin Wiring ................................................................................................................................ 11

IndustryPack Logic Interface Pin Assignment................ .............. ............... .............. .............. ....... 12

Programming .................................................................................................................................. 13

ID PROM........................................................................................................................................ 16Theory of Operation........................................................................................................................ 17

Construction and Reliability ........................................................................................................... 20

Warranty and Repair ....................................................................................................................... 21

Specifications.................................................................................................................................. 22

Order Information........................................................................................................................... 23

Schematics...................................................................................................................................... 24


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List of Figures

Figure 1 Simplified Block Diagram ......................................................................................... 2

Figure 2 VME Bus Addressing, Word Access......................................................................... 3

Figure 3 VME Bus Addressing, Byte Access........................................................................... 4

Figure 4 VME Bus Addressing, Long Word Access................................................................5

Figure 5 ISA Bus Addressing, Word Access............................................................................ 8

Figure 6 ISA Bus Addressing, Byte Access............................................................................. 9

Figure 7 I/O Pin Assignment.................................................................................................. 11

Figure 8 Logic Pin Assignment..............................................................................................12

Figure 9 ID PROM Data (hex)............................................................................................... 16

Figure 10 I/O Line Block Diagram .......................................................................................... 19


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1

Product Description


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2

ID PROM

I/P Bus

Interface

LineSafeESD

Circuit

Output

Register 1

Input

Register 1

Output

Register 24

Input

Register 24

I/O 1

I/O 24

Xilinx FPGAs

LineSafe

ESD

Circuit

Interrupt

Control

Registers

Interrupt

Register 1

Interrupt

Register 24


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3

VMEbus Addressing

Standard Word Access, I/O Space

Bit map of words at base + $0, base + $4, base + $12,base + $16 and base + $1A

Bit map of words at base + $2, base + $6, base + $14,base + $18 and base + $1C


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Bit map of the Interrupt Vector Register at base + $10

Alternate Byte Access, I/O Space

Bit map of bytes at base + $1, base + $5, base + $13,base + $17 and base + $1B


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Bit map of bytes at base + $0, base + $4, base + $12,base + $16 and base + $1A

Bit map of bytes at base + $3, base + $7, base + $15,base + $19 and base + $1D


Alternate Long Word Access, I/O Space

Bit map of long words at base + $0, base + $4, base + $12, base + $16and base + $1A


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Bit map of long word at base + $10


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7

NuBus Addressing


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ISA (IBM PC-AT) Addressing

Standard Word Access, I/O Space

Bit map of words at base + $0, base + $4, base + $12, base + $16 andbase + $1A

Bit map of words at base + $2, base + $6, base + $14, base + $18 andbase + $1C


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Alternate Byte Access, I/O Space

Bit map of bytes at base + $0, base + $4, base + $12,

base + $16 and base + $1A


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Bit map of bytes at base + $1, base + $5, base + $13,base + $17 and base + $1B


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Bit map of bytes at base + $2, base + $6, base + $14,base + $18 and base + $1C



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12

I/O Pin Wiring

I/O 1 1 GND 2I/O 2 3 GND 4I/O 3 5 GND 6I/O 4 7 GND 8I/O 5 9 GND 10I/O 6 11 GND 12I/O 7 13 GND 14I/O 8 15 GND 16I/O 9 17 GND 18I/O 10 19 GND 20I/O 11 21 GND 22

I/O 12 23 GND 24I/O 13 25 GND 26I/O 14 27 GND 28I/O 15 29 GND 30I/O 16 31 GND 32I/O 17 33 GND 34I/O 18 35 GND 36I/O 19 37 GND 38I/O 20 39 GND 40I/O 21 41 GND 42I/O 22 43 GND 44I/O 23 45 GND 46I/O 24 47 GND 48n/c 49 GND 50

Caution


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IndustryPack Logic Interface PinAssignment

GND GND 1 26

CLK +5V 2 27

Reset* R/W* 3 28

D0 IDSel* 4 29

D1 n/c 5 30

D2 n/c 6 31

D3 n/c 7 32D4 INTSel* 8 33

D5 n/c 9 34

D6 IOSel* 10 35

D7 n/c 11 36

D8 A1 12 37

D9 n/c 13 38

D10 A2 14 39

D11 n/c15 40

D12 A3 16 41

D13 IntReq0* 17 42

D14 A4 18 43

D15 n/c19 44

BS0* A5 20 45

BS1* n/c21 46

12V A6 22 47

+12V Ack* 23 48

+5V n/c 24 49

GND GND 25 50

Note 1: The no-connect (n/c) signals above are defined by the IndustryPack Logic Interface

Specification, but not used by this IP. See the Specification for more information.

Note 2: The layout of the pin numbers in this table corresponds to the physical placement of pins

on the IP connector. Thus this table may be used to easily locate the physical pin corresponding

to a desired signal. Pin 1 is marked with a square pad on the IndustryPack.


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Programming

Initialization

Data I/O

Interrupts


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Interrupt Enable Register

Interrupt Polarity Register

Clear Interrupt Register andPending Interrupt Register


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Interrupt Vector Register


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ID PROM

3F(available for user)

19

17 CRC for bytes used (87)

15 No of bytes used (0C)

13 Driver ID, high byte (00)

11 Driver ID, low byte (00)

0F reserved (00)

0D Revision (A1)

0B Model No IP-Unidig-I-E (67)

09 Manufacturer ID GreenSpring (F0)

07 ASCII C (43)

05 ASCII A (41)

03 ASCII P (50)

01 ASCII I (49)


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Theory of OperationIndustryPack Standards

Control Logic

I/O Data Lines

Interrupts


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8 MHzIP Clk

Data Bus

OutputLatch

InputLatch

InterruptRegister

Polarity

Polarity Chip Select Pulse

I/O LineD Q

Y A

Read BackBuffer

DQ

DQ

EdgeDetect

LevelDetect

Interrupt Clear

Interrupt

Clr

InterruptEnable

+5V

10K

PendingInterrupt


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Construction and Reliability


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Warranty and Repair

Service Policy

Out of Warranty Repairs

For Service Contact:

Customer Service DepartmentGreenSpring Computers1204 OBrien DriveMenlo Park, CA 94025

(415) 327-1200(415) 327-3808 fax


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Specifications


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Order Information


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Schematics

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